Texas-Instruments-CSD17573Q5B
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Download  | Texas-Instruments-CSD17573Q5B |
SLPS492B
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CSD17573Q5B 30-V N-Channel NexFET™ Power MOSFETs
1 Features
Product Summary
1
•
•
•
•
•
•
•
•
Low Q
g
and Q
gd
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Ultra-Low R
DS(on)
Drain-to-Source Voltage
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
30
49
Low-Thermal Resistance
Avalanche Rated
Q
g
nC
nC
Q
gd
11.9
V
GS
= 4.5 V
V
GS
= 10 V
1.4
1.19
0.84
Lead-Free Terminal Plating
RoHS Compliant
R
DS(on)
Drain-to-Source On Resistance
V
GS(th)
Threshold Voltage
m
Ω
V
Halogen Free
SON 5-mm × 6-mm Plastic Package
DEVICE
QTY
2500 13-Inch
Reel
250 7-Inch
Reel
MEDIA
PACKAGE
SHIP
2 Applications
CSD17573Q5B
CSD17573Q5BT
SON
Tape
and
Reel
5.00-mm × 6.00-mm
Plastic Package
•
Point-of-Load Synchronous Buck Converter for
Applications in Networking, Telecom, and
Computing Systems
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
Optimized for Synchronous FET Applications
Absolute Maximum Ratings
3 Description
T
A
= 25°C
VALUE
UNIT
V
This 0.84-m
Ω
, 30-V, SON 5-mm × 6-mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
V
DS
Drain-to-Source Voltage
V
GS
Gate-to-Source Voltage
Continuous Drain Current (Package Limited)
30
±20
V
100
Continuous Drain Current (Silicon Limited),
T
C
= 25°C
I
D
332
A
Top View
43
400
3.2
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
I
DM
P
D
A
W
Power Dissipation, T
C
= 25°C
195
T
J
,
T
stg
Operating Junction,
Storage Temperature
–55 to 150
289
°C
Avalanche Energy, Single Pulse
I
D
= 76, L = 0.1 mH, R
G
= 25
Ω
E
AS
mJ
D
D
(1) Typical R
θ
JA
0.06-in thick FR4 PCB.
= 40°C/W on a
a
1-in
2
, 2-oz Cu pad on
P0093-01
(2) Max
R
θ
JC
= 0.8°C/W, pulse duration
≤
100
μ
s, duty cycle
≤
1%.
R
DS(on)
vs V
GS
Gate Charge
5
4.5
4
10
9
T
C
= 25°C,I
D
= 35A
T
C
= 125°C,I
D
= 35A
8
3.5
3
7
6
2.5
2
5
4
1.5
1
3
2
I
D
= 35A
V
DS
= 15V
0.5
0
1
0
0
2
4
6
8
10
12
14
16
18
20
0
10 20 30 40 50 60 70 80 90
100 110 120
Q
g
– Gate Charge
(nC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
7
Mechanical, Packaging, and Orderable
6
4 Revision
History
Changes from Revision A (February 2015) to Revision B
Page
•
•
•
Changed the dimension between pads 3 and 4 from 0.028 inches : to 0.050 inches in the
Recommended PCB
Changes from Original (June 2014) to Revision A
Page
•
2
Copyright © 2014–2017, Texas Instruments Incorporated
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5 Specifications
5.1 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
30
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 24 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 35 A
V
GS
= 10 V, I
D
= 35 A
V
DS
= 15 V, I
D
= 35 A
1
100
1.8
μ
A
nA
V
I
GSS
V
GS(th)
1.1
1.4
1.19
0.84
181
1.45
1.00
R
DS(on)
g
ƒs
Drain-to-source on resistance
Transconductance
m
Ω
S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input capacitance
6920
769
300
0.9
49
9000
1000
390
1.8
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 15 V, ƒ = 1 MHz
Q
g
64
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
11.9
17.1
8.6
21
V
DS
= 15 V, I
D
= 35 A
V
DS
= 30 V, V
GS
= 0 V
Turnon delay time
Rise time
6
20
V
DS
= 15 V, V
GS
= 10 V,
I
DS
= 35 A, R
G
= 0
Ω
t
d(off)
t
ƒ
Turnoff delay time
Fall Time
40
7
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
SD
= 35 A, V
GS
= 0 V
0.8
29
21
1
V
nC
ns
V
DS
= 15 V, I
F
= 35 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
(1)
Junction-to-ambient thermal resistance
(1
)
(
2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
θ
JC
R
θ
JA
0.8
50
(1)
R
θ
JC
is determined with the device mounted on a 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu.
Copyright © 2014–2017, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 50°C/W
when mounted on 1 in
2
(6.45 cm
2
) of
2-oz (0.071-mm) thick
Cu.
Max R
θ
JA
= 125°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical
MOSFET Characteristics
T
A
= 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
200
200
180
160
140
120
100
80
180
160
140
120
100
80
60
60
V
GS
=10V
V
GS
=6V
V
GS
=4.5V
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
40
20
0
40
20
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
0
10 20 30 40 50 60 70 80 90
100 110 120
Q
g
– Gate Charge
(nC)
3
6
9
12
15
18
21
24
27
30
V
DS
– Drain-to-Source Voltage (V)
G001
G001
I
D
= 35 A
V
DS
= 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
2
1.8
1.6
1.4
1.2
1
5
4.5
4
T
C
= 25°C,I
D
= 35A
T
C
= 125°C,I
D
= 35A
3.5
3
2.5
2
1.5
1
0.8
0.6
0.4
0.5
0
−75 −50 −25
0
25
50
75 100
125 150 175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (ºC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2014–2017, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
2
100
10
V
GS
= 4.5V
V
GS
= 10V
T
C
= 25°C
T
C
= 125°C
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
−75 −50 −25
0
25
50
75 100
125 150 175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (ºC)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
I
D
= 35 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
T
C
= 25ºC
T
C
= 125ºC
10
0.01
0.1
0.1
0.1
1
1
10
100
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (mS)
G001
D010
Single pulse, max R
θ
JC
= 0.8°C/W
Figure 11. Single Pulse Unclamped Inductive Switching
Figure 10. Maximum Safe Operating Area
120
100
80
60
40
20
0
−50 −25
0
25
50
75 100
125 150 175 200
T
C
– Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
6
Copyright © 2014–2017, Texas Instruments Incorporated
SLPS492B
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6 Device
and Documentation Support
6.1 Receiving
Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2014–2017, Texas Instruments Incorporated
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q5B
Package Dimensions
K
c1
H
L
E1
•
d1
d2
Top View
Side View
Bottom View
•
Front View
MILLIMETERS
DIM
MIN
0.80
0.36
0.15
0.15
0.20
4.90
4.12
3.90
0.20
NOM
MAX
1.05
0.46
0.25
0.25
0.30
5.10
4.32
4.10
0.30
A
b
1.00
0.41
0.20
0.20
0.25
5.00
4.22
4.00
0.25
c
c1
c2
D1
D2
D3
d
d1
d2
E
0.085 TYP
0.319
4.90
5.90
3.48
0.369
5.00
6.00
3.58
0.419
5.10
6.10
3.68
E1
E2
e
1.27 TYP
1.40 TYP
H
0.36
0.46
0.57
0°
0.46
0.56
0.67
—
0.56
0.66
0.77
—
L
L1
θ
K
8
Copyright © 2014–2017, Texas Instruments Incorporated
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7.2 Recommended
PCB Pattern
(SLPA005).
7.3 Recommended
Stencil Pattern
(0.020)
(0.014)
0.508
x4
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
0.350
(0.086)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.050)
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
Copyright © 2014–2017, Texas Instruments Incorporated
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7.4 Q5B
Tape and Reel Information
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
Notes:
1. 10-sprocket
hole-pitch cumulative tolerance ±0.2.
2. Camber
not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material:
black static-dissipative polystyrene.
4. All
dimensions are in mm (unless otherwise specified).
5. A0
and B0 measured on a plane 0.3 mm above the bottom of the pocket.
10
Copyright © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
31-May-2016
PACKAGING INFORMATION
Orderable Device
CSD17573Q5B
CSD17573Q5BT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSON-CLIP
VSON-CLIP
DNK
8
8
2500 Pb-Free
(RoHS
Exempt)
CU NIPDAU
Level-1-260C-UNLIM
CSD17573
CSD17573
ACTIVE
DNK
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
31-May-2016
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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http://www.ti.com/sc/docs/stdterms.htm
) apply to the sale of packaged integrated
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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