Texas-Instruments-CSD17576Q5B
| Part # | Texas-Instruments-CSD17576Q5B |
Download  | Texas-Instruments-CSD17576Q5B |
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
CSD17576Q5B 30V N
通道
NexFET™
功率金属氧化物半导体场效应晶体
管
(MOSFET)
1
特性
产品概要
1
•
•
•
•
•
•
•
•
低
Q
g
和
Q
gd
低
R
DS(on)
T
A
= 25°C
V
DS
典型值
30
单位
V
漏源电压
低热阻
Q
g
栅极电荷总量
(4.5V)
栅极电荷（栅极到漏极）
25
nC
nC
m
Ω
m
Ω
V
雪崩级
Q
gd
5.4
V
GS
= 4.5V
V
GS
= 10V
1.4
2.4
1.7
无铅引脚镀层
符合
RoHS
标准
无卤素
R
DS(on)
漏源导通电阻
V
GS(th)
阈值电压
SON 5mm × 6mm
塑料封装
器件
数量
2500 13
英寸卷带
250 7
英寸卷带
介质
封装
出货
卷带封装
2
应用范围
CSD17576Q5B
CSD17576Q5BT
SON 5mm x 6mm
塑料封装
•
用于网络互联、电信和计算系统的 负载点 同步降
压转换器
(1)
要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
•
已针对同步
FET
应用进行 优化
绝对最大额定值
3
说明
T
A
= 25°C
值
30
单位
V
V
DS
V
GS
漏源电压
这款
30V
、
1.7m
Ω
、
SON 5 x 6mm NexFET™
功率
MOSFET
的设计旨在追求以最大限度降低功率转换应
用中的功率 损耗。
栅源电压
±20
100
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
T
C
= 25°C
时测得
I
D
184
A
顶视图
30
400
3.1
I
DM
P
D
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
功率耗散，
T
C
= 25°C
125
T
J
， 运行结温和
-55
至
150
°C
T
stg
储存温度范围
雪崩能量，单脉冲
I
D
= 48
，
L = 0.1mH
，
R
G
= 25
Ω
E
AS
115
mJ
D
(1) R
θ
JA
= 40°C/W
，这是在一个厚度
0.06
英寸环氧树脂
(FR4)
印
刷电路板
(PCB)
上的
1
英寸
2
，
2
盎司的铜过渡垫片上测得的
典型值。
D
P0093-01
(2)
最大
R
θ
JC
= 1.3°C/W
，脉冲持续时间
≤
100
μ
s
，占空比
≤
1%
。
R
DS(on)
与
V
GS
对比
栅极电荷
8
7
6
5
4
3
2
1
0
10
9
T
C
= 25°C,I
D
= 25A
T
C
= 125°C,I
D
= 25A
8
7
6
5
4
3
2
I
D
= 25A
V
DS
= 15V
1
0
0
2
4
6
8
10
12
14
16
18
20
0
5
10 15 20 25 30 35 40 45 50 55
Q
g
– Gate Charge
(nC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
目录
1
2
3
4
5
7
6
4
修订历史记录
Changes from Original (June 2014) to Revision A
Page
•
•
2
版权
© 2014–2017, Texas Instruments Incorporated
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
5 Specifications
5.1 Electrical
Characteristics
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain to Source Voltage
V
GS
= 0 V, I
D
= 250
μ
A
30
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
V
GS
= 0 V, V
DS
= 24 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 25 A
V
GS
= 10 V, I
D
= 25 A
V
DS
= 3 V, I
D
= 25 A
1
100
1.8
2.9
2.0
μ
A
nA
V
I
GSS
V
GS(th)
1.1
1.4
2.4
1.7
120
m
Ω
m
Ω
S
R
DS(on)
g
fs
Drain to Source On Resistance
Transconductance
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input Capacitance
3410
389
151
1.0
25
4430
506
196
2.0
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Total (10 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
V
GS
= 0V, V
DS
= 15 V, ƒ = 1 MHz
Q
g
32
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
g
53
68
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= 15 V, I
D
= 25 A
V
DS
= 30 V, V
GS
= 0 V
5.4
8.9
4.7
12.3
5
Turn On Delay Time
Rise Time
16
V
DS
= 15 V, V
GS
= 10 V,
I
DS
= 25 A, R
G
= 0
Ω
t
d(off)
t
f
Turn Off Delay Time
Fall Time
23
3
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
I
SD
= 25 A, V
GS
= 0V
0.8
14.7
14
1
V
nC
ns
V
DS
= 15 V, I
F
= 25 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
(T
A
= 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
UNIT
(1)
R
θ
JC
R
θ
JA
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance
1.3
50
°C/W
(1
)
(
2)
(1)
R
θ
JC
is determined with the device mounted on a 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-
cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu.
Copyright © 2014–2017, Texas Instruments Incorporated
3
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
GATE
Source
GATE
Source
Max R
θ
JA
= 50°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2-oz. (0.071-mm thick)
Cu.
Max R
θ
JA
= 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical
MOSFET Characteristics
(T
A
= 25°C unless otherwise stated)
Figure 1.
Transient Thermal Impedance
4
Copyright © 2014–2017, Texas Instruments Incorporated
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
200
200
180
160
140
120
100
80
180
160
140
120
100
80
60
60
V
GS
=10V
V
GS
=6V
V
GS
=4.5V
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
40
20
0
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
0
5
10 15 20 25 30 35 40 45 50 55
Q
g
– Gate Charge
(nC)
3
6
9
12
15
18
21
24
27
30
V
DS
– Drain-to-Source Voltage (V)
G001
G001
V
DS
= 15 V
I
D
= 25 A
Figure 4. Gate Charge
Figure 5. Capacitance
2
1.8
1.6
1.4
1.2
1
8
7
6
5
4
3
2
1
0
T
C
= 25°C,I
D
= 25A
T
C
= 125°C,I
D
= 25A
0.8
0.6
−75 −50 −25
0
25
50
75 100
125 150 175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (ºC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2014–2017, Texas Instruments Incorporated
5
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
2
100
10
V
GS
= 4.5V
V
GS
= 10V
T
C
= 25°C
T
C
= 125°C
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
−75 −50 −25
0
25
50
75 100
125 150 175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (ºC)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
I
D
= 25 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
5000
100
T
C
= 25ºC
T
C
= 125ºC
10us
100us
1ms
10ms
DC
1000
100
10
1
0.1
0.1
10
0.01
1
10
100
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (mS)
G001
G001
Single Pulse Max R
θ
JC
= 1.3°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
120
100
80
60
40
20
0
−50 −25
0
25
50
75 100
125 150 175 200
T
C
– Case Temperature (ºC)
G001
Figure 12.
Maximum Drain Current vs Temperature
6
Copyright © 2014–2017, Texas Instruments Incorporated
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
6
器件和文档支持
6.1
接收文档更新通知
要接收文档更新通知，请导航至
ti.com
上的器件产品文件夹。请单击右上角的
通知我
进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
6.2
社区资源
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
6.3
商标
NexFET, E2E are trademarks of Texas Instruments.
6.4
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
6.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
版权
© 2014–2017, Texas Instruments Incorporated
7
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
7
机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
7.1 Q5B
封装尺寸
K
c1
H
L
E1
•
d1
d2
Top View
Side View
Bottom View
•
Front View
毫米
标称值
1.00
DIM
最小值
最大值
A
b
0.80
0.36
0.15
0.15
0.20
4.90
4.12
3.90
0.20
1.05
0.46
0.25
0.25
0.30
5.10
4.32
4.10
0.30
0.41
c
0.20
c1
c2
D1
D2
D3
d
0.20
0.25
5.00
4.22
4.00
0.25
d1
d2
E
0.085
典型值
0.369
5.00
0.319
4.90
5.90
3.48
0.419
5.10
6.10
3.68
E1
E2
e
6.00
3.58
1.27
典型值
0.46
H
0.36
0.46
0.57
0°
0.56
0.66
0.77
–
L
0.56
L1
θ
0.67
–
K
1.40
典型值
8
版权
© 2014–2017, Texas Instruments Incorporated
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
7.2
建议
PCB
布局
，焊盘
3
和
4
之间的尺寸从
0.028
英寸更改为了
0.050
英寸
巧来减少振铃
。
版权
© 2014–2017, Texas Instruments Incorporated
9
ZHCSCL0A
–
J
UNE 201
4
–
R
EVISED MAY 2017
7.3
建议模板布局
(0.020)
0.508
(0.014)
0.350
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
x4
(0.086)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.050)
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
7.4 Q5B
卷带信息
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
注释：
1. 10
个链齿孔的累积容差为
±0.2
。
2.
每
100mm
长度的翘曲不能超过
1mm
，在
250mm
长度上不累积。
3.
材料：黑色抗静电聚苯乙烯。
4.
全部尺寸单位为
mm
（除非另外注明）。
5.
高于孔眼底部
0.3mm
的平面上测量得到
A0
和
B0
值
.
10
版权
© 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD17576Q5B
CSD17576Q5BT
ACTIVE
VSON-CLIP
VSON-CLIP
DNK
8
8
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CSD17576
CSD17576
ACTIVE
DNK
RoHS-Exempt
& Green
NIPDAU
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI
均以
“
原样
”
提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用
TI
产品进行设计使用。您将对以下行为独自承担全部责任：
(1)
针对您的应用选择合适的
TI
产品；
(2)
设计、
验证并测试您的应用；
(3)
确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。
TI
对您使用
所述资源的授权仅限于开发资源所涉及
TI
产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它
TI
或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，
TI
对此概不负责，并且您须赔偿由此对
TI
及其代表造成的损害。
束。
TI
提供所述资源并不扩展或以其他方式更改
TI
针对
TI
产品所发布的可适用的担保范围或担保免责声明。
IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道
1568
号中建大厦
32
楼，邮政编码：
200122
Copyright © 20
20
德州仪器半导体技术（上海）有限公司
