Texas-Instruments-CSD17578Q3A
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CSD17578Q3A 30 V N-Channel NexFET™ Power MOSFETs
1 Features
Product Summary
1
•
•
•
•
•
•
•
•
Low Q
g
and Q
gd
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Low R
DS(on)
Drain-to-Source Voltage
Gate Charge Total (4.5 V)
Gate Charge Gate to Drain
30
7.9
Low Thermal Resistance
Avalanche Rated
Pb-Free
Q
g
nC
nC
m
Ω
m
Ω
V
Q
gd
1.7
V
GS
= 4.5 V
V
GS
= 10 V
1.5
8.2
6.3
R
DS(on)
Drain-to-Source On-Resistance
V
GS(th)
Threshold Voltage
RoHS Compliant
Halogen Free
SON 3.3 mm × 3.3 mm Plastic Package
.
2 Applications
DEVICE
CSD17578Q3A 13-Inch
Reel 2500
CSD17578Q3AT 7-Inch
Reel 250
MEDIA
QTY
PACKAGE
SHIP
•
Point-of-Load Synchronous Buck Converter for
Applications in Networking, Telecom, and
Computing Systems
SON 3.3 x 3.3 mm
Tape and
Plastic Package
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
Optimized for Control FET Applications
Absolute Maximum Ratings
3 Description
This 30 V, 6.3 m
Ω
, SON 3.3 mm × 3.3 mm
NexFET™ power MOSFET is designed to minimize
losses in power conversion applications.
T
A
= 25°C
VALUE
UNIT
V
V
DS
V
GS
Drain-to-Source Voltage
30
Gate-to-Source Voltage
±20
20
V
Continuous Drain Current (Package limited)
Top View
Continuous Drain Current (Silicon limited),
T
C
= 25°C
I
D
54
A
14
142
2.5
37
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
I
DM
P
D
A
W
Power Dissipation, T
C
= 25°C
T
J
,
T
stg
Operating Junction Temperature,
Storage Temperature
–55 to 150
24
°C
D
D
Avalanche Energy, single pulse
I
D
= 22 A, L = 0.1 mH, R
G
= 25
Ω
E
AS
mJ
P0093-01
(1) Typical R
θ
JA
= 50°C/W on a 1 inch
2
, 2 oz. Cu pad on a
0.06 inch thick FR4 PCB.
.
.
(2) Max
R
θ
JC
= 4.2 °C/W, pulse duration
≤
100
μ
s, duty cycle
≤
1%
R
DS(on)
vs V
GS
Gate Charge
20
18
16
14
12
10
8
10
T
C
= 25
°
C
, I
D
= 10 A
T
C
= 125
°
C
, I
D
= 10 A
I
D
= 10 A, V
DS
= 15V
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
V
GS
– Gate-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
7
Mechanical, Packaging, and Orderable
6
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
•
2
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5 Specifications
5.1 Electrical
Characteristics
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-Source Voltage
V
GS
= 0 V, I
D
= 250
μ
A
30
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
V
GS
= 0 V, V
DS
= 24 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 10 A
V
GS
= 10 V, I
D
= 10 A
V
DS
= 3 V, I
D
= 10 A
1
100
1.9
9.4
7.3
μ
A
nA
V
I
GSS
V
GS(th)
1.1
1.5
8.2
6.3
48
m
Ω
m
Ω
S
Drain-to-Source
On-Resistance
R
DS(on)
g
fs
Transconductance
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input Capacitance
1150
134
56
1590
174
73
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Total (10 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at V
th
V
GS
= 0 V, V
DS
= 15 V, ƒ = 1 MHz
1.8
7.9
17.1
1.7
3.3
1.6
4.2
2
3.6
Q
g
10.3
22.2
nC
Q
g
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= 15 V, I
D
= 10 A
V
DS
= 15 V, V
GS
= 0 V
nC
nC
nC
nC
ns
Output Charge
Turn On Delay Time
Rise Time
6
ns
V
DS
= 15 V, V
GS
= 10 V,
I
DS
= 10 A, R
G
= 0
Ω
t
d(off)
t
f
Turn Off Delay Time
Fall Time
13
ns
1
ns
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
I
SD
= 10 A, V
GS
= 0 V
0.8
4.4
6
1.0
V
nC
ns
V
DS
= 15 V, I
F
= 10 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
(T
A
= 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
UNIT
(1)
R
θ
JC
R
θ
JA
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance
(1
)
(
2)
4.2
60
°C/W
(1)
R
θ
JC
is determined with the device mounted on a 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu.
Copyright © 2014–2016, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 60°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2-oz. (0.071-mm thick)
Cu.
Max R
θ
JA
= 145°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical
MOSFET Characteristics
(T
A
= 25°C unless otherwise stated)
Figure 1.
Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
V
GS
= 4.5 V
V
GS
= 6 V
V
GS
= 10 V
T
C
= 125
°
C
T
C
= 25
°
C
T
C
= -55
°
C
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
1
1.5
2
2.5
3
3.5
4
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D002
D003
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
1000
100
10
9
8
7
6
5
4
3
2
1
0
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
10
0
2
4
6
8
10
12
14
16
18
0
3
6
9
12
15
18
21
24
27
30
Q
g
– Gate Charge (nC)
V
DS
– Drain-to-Source Voltage (V)
D004
D005
I
D
= 10 A
V
DS
= 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
20
18
16
14
12
10
8
T
C
= 25
°
C
, I
D
= 10 A
T
C
= 125
°
C
, I
D
= 10 A
6
4
2
0
0
-75 -50 -25
0
25
50
75 100
125 150 175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (
°
C
)
V
GS
– Gate-to-Source Voltage (V)
D006
D007
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
100
10
1.8
T
C
= 25
°
C
T
C
= 125
°
C
V
GS
= 4.5 V
V
GS
= 10 V
1.6
1
1.4
1.2
1
0.1
0.01
0.001
0.0001
0.8
0.6
-75 -50 -25
0
25
50
75 100
125 150 175
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
SD
– Source-to-Drain Voltage (V)
1
T
C
– Case Temperature (
°
C
)
D008
D009
I
D
= 10 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
10
1
T
C
= 25
è
C
T
C
= 125
è
C
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
0.1
0.1
1
10
100
0.01
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (ms)
D010
D011
Single Pulse,
Max R
θ
JC
= 4.2°C/W
Figure 10. Maximum Safe Operating Area (SOA)
Figure 11. Single Pulse Unclamped Inductive Switching
25
20
15
10
5
0
-50
-25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (
°
C
)
D012
Figure 12.
Maximum Drain Current vs Temperature
6
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6 Device
and Documentation Support
6.1 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2014–2016, Texas Instruments Incorporated
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A
Package Dimensions
3.1
2.9
A
B
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
3.1
TYP
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
0.52
0.32
4X
0.565±0.1
4
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
0.35
8X
0.55
4X
0.25
0.25
0.1
C B
C
A
4X 1.45
0.05
2X
NOTE 4
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This
drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized
features are supplier options and may not be on the package.
5. All
dimensions do not include mold flash or protrusions.
8
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7.2 Q3A
Recommended PCB Pattern
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
(0.245)
(
0.2) VIA
TYP
METAL UNDER
SOLDER MASK
(0.905)
TYP
(1.55)
1. This
package is designed to be soldered to a thermal pad on the board. For more information, see
QFN/SON
2. Vias
are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
7.3 Q3A
Recommended Stencil Pattern
(0.905)
PKG
8X (0.6)
8X (0.3)
(0.208)
SOLDER MASK EDGE
1
8
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
METAL
TYP
4X 0.705
(3.1)
1. Laser
cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
Copyright © 2014–2016, Texas Instruments Incorporated
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7.4 Q3A
Tape and Reel Information
4.00 0.ꢀ0
ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
Notes: 1.
10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF-reflow compatible
10
Copyright © 2014–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
11-Jan-2016
PACKAGING INFORMATION
Orderable Device
CSD17578Q3A
CSD17578Q3AT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSONP
VSONP
DNH
8
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
17578
17578
ACTIVE
DNH
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
11-Jan-2016
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (
http://www.ti.com/sc/docs/stdterms.htm
) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
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remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
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