Texas-Instruments-CSD17579Q3AT
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CSD17579Q3A 30V N
通道
NexFET™
功率
MOSFET
1
特性
产品概要
1
•
•
•
•
•
•
•
•
低
Q
g
和
Q
gd
T
A
= 25°C
V
DS
典型值
单位
V
低
R
DS(on)
低热阻
漏源电压
30
5.3
1.2
Q
g
总栅极电荷
(4.5V)
栅极电荷（栅极到漏极）
nC
nC
m
Ω
m
Ω
V
雪崩级
Q
gd
V
GS
= 4.5V
V
GS
= 10V
1.5
11.8
8.7
无铅
R
DS(on)
漏源导通电阻
V
GS(th)
阈值电压
符合
RoHS
标准
无卤素
小外形尺寸无引线
(SON) 3.3mm × 3.3mm
塑料封
装
.
数量
器件
包装介质
封装
发货
卷带封装
2
应用
CSD17579Q3A 13
英寸卷带
2500
CSD17579Q3AT 7
英寸卷带
250
SON 3.3mm x
3.3mm
塑料封装
•
用于网络、电信和计算系统中的 负载点 同步降压
转换器
(1)
如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
针对控制场效应晶体管
(FET)
应用进行了优化
3
说明
绝对最大额定值
T
A
= 25°C
值
30
单位
V
这款
30V
，
8.7m
Ω
，
SON 3.3mm × 3.3mm NexFET™
功率
MOSFET
旨在最大限度地降低功率转换应用中的
损耗提供了灵活性和便利性。
V
DS
V
GS
漏源电压
栅源电压
±20
20
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
T
C
= 25°C
时测得
I
D
39
A
顶视图
11
106
2.5
29
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
I
DM
P
D
A
W
功率耗散，
T
C
= 25°C
T
J
， 工作结温，
–55
至
150
°C
T
stg
储存温度
D
D
雪崩能量，单一脉冲
I
D
= 17A
，
L = 0.1mH
，
R
G
= 25
Ω
E
AS
14
mJ
P0093-01
(1) R
θ
JA
= 50°C/W
，这是在厚度为
0.06
英寸的环氧板
(FR4)
印刷
电路板
(PCB)
上的
1
英寸
2
2
盎司的铜过渡垫片上测得的典型
值。
.
.
(2)
最大
R
θ
JC
= 5.4°C/W
，脉冲持续时间
≤
100
μ
s
，占空比
≤
1%
R
DS(on)
与
V
GS
对比
栅极电荷
30
27
24
21
18
15
12
9
10
T
C
= 25
°
C
, I
D
= 8 A
T
C
= 125
°
C
, I
D
= 8 A
I
D
= 8 A, V
DS
= 15 V
9
8
7
6
5
4
3
2
1
0
6
3
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
V
GS
– Gate-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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目录
1
2
3
4
5
7
6
4
修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
•
2
版权
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5 Specifications
5.1 Electrical
Characteristics
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
30
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 24 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 8 A
V
GS
= 10 V, I
D
= 8 A
V
DS
= 3 V, I
D
= 8 A
1
100
1.9
μ
A
nA
V
I
GSS
V
GS(th)
1.1
1.5
11.8
8.7
14.2
10.2
m
Ω
m
Ω
S
R
DS(on)
g
fs
Drain-to-source on-resistance
Transconductance
37
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input capacitance
768
93
998
121
49
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 15 V, ƒ = 1 MHz
38
1.9
5.3
11.5
1.2
2.2
1.1
3.0
2
3.8
Q
g
6.9
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
g
15.0
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= 15 V, I
D
= 8 A
V
DS
= 15 V, V
GS
= 0 V
Turn on delay time
Rise time
5
V
DS
= 15 V, V
GS
= 10 V,
I
DS
= 8 A, R
G
= 0
Ω
t
d(off)
t
f
Turn off delay time
Fall time
11
1
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
SD
= 8 A, V
GS
= 0 V
0.8
3.4
5
1.0
V
nC
ns
V
DS
= 15 V, I
F
= 8 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
(T
A
= 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
UNIT
°C/W
°C/W
(1)
R
θ
JC
R
θ
JA
Junction-to-case thermal resistance
Junction-to-ambient thermal resistance
(1
)
(
2)
5.4
60
(1)
R
θ
JC
is determined with the device mounted on a 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu.
Copyright © 2014–2016, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 60°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2 oz. (0.071 mm thick)
Cu.
Max R
θ
JA
= 145°C/W
when mounted on a
minimum pad area of 2
oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical
MOSFET Characteristics
(T
A
= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
Copyright © 2014–2016, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
50
50
45
40
35
30
25
20
15
10
5
40
30
20
10
V
GS
= 4.5 V
V
GS
= 6 V
V
GS
= 10 V
T
C
= 125
°
C
T
C
= 25
°
C
T
C
= -55
°
C
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
DS
– Drain-to-Source Voltage (V)
1
0
0.5
1
1.5
2
2.5
3
3.5
4
V
GS
– Gate-to-Source Voltage (V)
D002
D003
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
1000
100
10
9
8
7
6
5
4
3
2
1
0
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
10
0
2
4
6
8
10
12
0
3
6
9
12
15
18
21
24
27
30
Q
g
– Gate Charge (nC)
V
DS
– Drain-to-Source Voltage (V)
D004
D005
I
D
= 8 A
V
DS
= 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
30
27
24
21
18
15
12
9
T
C
= 25
°
C
, I
D
= 8 A
T
C
= 125
°
C
, I
D
= 8 A
6
3
0
0
-75 -50 -25
0
25
50
75 100
125 150 175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (
°
C
)
V
GS
– Gate-to-Source Voltage (V)
D006
D007
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2014–2016, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
100
10
1.8
T
C
= 25
°
C
T
C
= 125
°
C
V
GS
= 4.5 V
V
GS
= 10 V
1.6
1
1.4
1.2
1
0.1
0.01
0.001
0.0001
0.8
0.6
-75 -50 -25
0
25
50
75 100
125 150 175
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
SD
– Source-to-Drain Voltage (V)
1
T
C
– Case Temperature (
°
C
)
D008
D0
1
0
0
9
I
D
= 8 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
70
T
C
= 25
è
C
T
C
= 125
è
C
50
100
10
1
30
20
10
7
5
3
2
DC
10 ms
1 ms
100 µs
10 µs
0.1
0.1
1
0.01
1
10
100
0.02 0.03
0.050.07 0.1
0.2 0.3
0.5 0.7
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (ms)
D010
D011
Single Pulse, Max R
θ
JC
= 5.4°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
25
20
15
10
5
0
-50
-25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (
°
C
)
D012
Figure 12. Maximum Drain Current vs Temperature
6
Copyright © 2014–2016, Texas Instruments Incorporated
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6
器件和文档支持
6.1
社区资源
下列链接提供到
TI
社区资源的连接。链接的内容由各个分销商
“
按照原样
”
提供。这些内容并不构成
TI
技术规范，
e2e.ti.com
中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI
参考设计支持
可帮助您快速查找有帮助的
E2E
论坛、设计支持工具以及技术支持的联系信息。
6.2
商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
6.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
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© 2014–2016, Texas Instruments Incorporated
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7
机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
7.1 Q3A
封装尺寸
3.1
2.9
A
B
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
3.1
TYP
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
0.52
0.32
4X
0.565±0.1
4
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
0.35
8X
0.55
4X
0.25
0.25
0.1
C B
C
A
4X 1.45
0.05
2X
NOTE 4
1.
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合
ASME Y14.5M
标准。
2.
本图如有变更，恕不另行通知。
3.
必须在印刷电路板上焊接封装散热焊盘，以获得良好的散热和机械性能。
4.
金属化 特性 为供应商选配特性，因此封装上可能不具备。
5.
所有尺寸不包括模具毛边或突出部分。
8
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7.2 Q3A
建议的
PCB
布局
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
(0.245)
(
0.2) VIA
TYP
METAL UNDER
SOLDER MASK
(0.905)
TYP
(1.55)
1.
此封装设计用于焊接到电路板的散热焊盘上。有关更多信息，请参阅
《
QFN/SON
PCB
连接》
应用报
2.
根据应用决定是否选用过孔，详情请参见器件产品说明书。如果实现了部分或全部过孔，则会显示建议的过孔
位置。
巧来减少振铃
。
7.3 Q3A
建议的模板布局
(0.905)
PKG
8X (0.6)
8X (0.3)
(0.208)
SOLDER MASK EDGE
1
8
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
METAL
TYP
4X 0.705
(3.1)
1.
具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。
IPC-7525
可能提供其他替代性设计建议。
版权
© 2014–2016, Texas Instruments Incorporated
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7.4 Q3A
卷带信息
4.00 0.ꢀ0
ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
Notes: 1.
10
链轮孔距累积容差
±0.2
2.
每
100mm
长度的翘曲不能超过
1mm
，在
250mm
长度上不累积
3.
材料：黑色抗静电聚苯乙烯
4.
全部尺寸单位为
mm
，除非另外注明。
5.
厚度：
0.30 ± 0.05mm
6. MSL1 260°C
（红外
(IR)
和传导）
PbF
回流焊兼容
10
版权
© 2014–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD17579Q3A
CSD17579Q3AT
ACTIVE
ACTIVE
VSONP
VSONP
DNH
DNH
8
8
2500 RoHS
& Green
250 RoHS
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
17579
17579
SN
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
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