Texas-Instruments-CSD18504Q5A
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CSD18504Q5A 40-V N-Channel NexFET™ Power MOSFET
1 Features
Product Summary
1
•
•
•
•
•
•
•
•
Ultra-Low Q
g
and Q
gd
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Low Thermal Resistance
Avalanche Rated
Drain-to-Source Voltage
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
40
7.7
2.4
Q
g
nC
nC
m
Ω
m
Ω
V
Logic Level
Q
gd
V
GS
= 4.5 V
V
GS
= 10 V
1.9
7.5
5.3
Pb Free Terminal Plating
RoHS Compliant
R
DS(on)
Drain-to-Source On-Resistance
V
GS(th)
Threshold Voltage
Halogen Free
SON 5 mm × 6 mm Plastic Package
Device
Qty
Media
Package
Ship
2 Applications
CSD18504Q5A 2500
13-Inch Reel
CSD18504Q5AT 250 7-Inch
Reel
SON 5 mm × 6 mm
Plastic Package
Tape and
Reel
•
•
•
DC-DC Conversion
Secondary Side Synchronous Rectifier
Battery Motor Control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
3 Description
This 5.3 m
Ω
, SON 5 × 6 mm, 40 V NexFET™ power
MOSFET is designed to minimize losses in power
conversion applications.
T
A
= 25°C
VALUE
UNIT
V
V
DS
V
GS
Drain-to-Source Voltage
40
Gate-to-Source Voltage
±20
50
V
Continuous Drain Current (Package limited)
Continuous Drain Current (Silicon limited),
T
C
= 25°C
Top View
I
D
75
A
15
275
3.1
77
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
I
DM
P
D
A
W
Power Dissipation, T
C
= 25°C
T
J
,
T
stg
Operating Junction and
Storage Temperature Range
–55 to 150
92
°C
Avalanche Energy, single pulse
I
D
= 43 A, L = 0.1 mH, R
G
= 25
Ω
E
AS
mJ
D
D
(1) Typical R
θ
JA
= 40°C/W on a 1-inch
2
, 2-oz. Cu pad on a
0.06-inch thick FR4 PCB.
P0093-01
(2) Max R
θ
JC
= 2.0 °C/W, pulse duration
≤
100
μ
s, duty cycle
≤
1%
R
DS(on)
vs V
GS
Gate Charge
20
18
16
14
12
10
8
10
T
C
= 25°C
Id = 17A
T
C
= 125ºC Id = 17A
I
D
= 17A
V
DS
= 20V
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
Q
g
– Gate Charge
(nC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
7
Mechanical, Packaging, and Orderable
6
4 Revision
History
Changes from Revision D (August 2014) to Revision E
Page
•
•
Changes from Revision C (May 2013) to Revision D
Page
•
•
•
•
Changes from Revision B (November 2012) to Revision C
Page
•
•
Changes from Revision A (October 2012) to Revision B
Page
•
•
•
Changes from Original (June 2012) to Revision A
Page
•
•
Changed the Turn On and Turn Off Delay Time, Rise and Fall Time Test Conditions From: I
DS
= 17 A, R
G
= 2
Ω
To:
•
2
Copyright © 2012–2014, Texas Instruments Incorporated
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5 Specifications
5.1 Electrical
Characteristics
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-Source Voltage
V
GS
= 0 V, I
D
= 250
μ
A
40
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
V
GS
= 0 V, V
DS
= 32 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 17 A
V
GS
= 10 V, I
D
= 17 A
V
DS
= 20 V, I
D
= 17 A
1
100
2.4
9.8
6.6
μ
A
nA
V
I
GSS
V
GS(th)
1.5
1.9
7.5
5.3
71
m
Ω
m
Ω
S
R
DS(on)
g
ƒs
Drain-to-Source On-Resistance
Transconductance
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input Capacitance
1380
310
8
1656
372
9.6
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Total (10 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at V
th
V
GS
= 0 V, V
DS
= 20 V, ƒ = 1 MHz
1.4
7.7
16
2.8
Q
g
9.2
nC
Q
g
19
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= 20 V, I
D
= 17 A
V
DS
= 20 V, V
GS
= 0 V
2.4
3.2
2.2
21
nC
nC
nC
nC
ns
Output Charge
Turn On Delay Time
Rise Time
3.2
6.8
12
ns
V
DS
= 20 V, V
GS
= 10 V,
I
DS
= 17 A, R
G
= 0
Ω
t
d(off)
t
ƒ
Turn Off Delay Time
Fall Time
ns
2
ns
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
I
SD
= 17 A, V
GS
= 0 V
0.8
39
28
1
V
nC
ns
V
DS
= 20 V, I
F
= 17 A,
di/dt = 300 A/
μ
s
5.2 Thermal
Information
(T
A
= 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-Case Thermal Resistance
(1)
Junction-to-Ambient Thermal Resistance
(1
)
(
2)
MIN
TYP
MAX
UNIT
R
θ
JC
R
θ
JA
2.0
50
°C/W
(1)
R
θ
JC
is determined with the device mounted on a 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu.
Copyright © 2012–2014, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 50°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2-oz. (0.071-mm thick)
Cu.
Max R
θ
JA
= 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical
MOSFET Characteristics
(T
A
= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
100
100
80
60
40
20
0
V
DS
= 5V
80
60
40
V
GS
=10V
V
GS
=6.5V
V
GS
=4.5V
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
20
0
0
0.2
0.4
0.6
0.8
1
1.2
0
0
0
1
2
3
4
5
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
I
D
= 17A
V
DS
= 20V
10
0
2
4
6
8
10
12
14
16
4
8
12
16
20
24
28
32
36
40
Q
g
– Gate Charge
(nC)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
20
18
16
14
12
10
8
I
D
= 250uA
T
C
= 25°C
Id = 17A
T
C
= 125ºC Id = 17A
6
4
2
0
−75
−25
25
75
125
175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (ºC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2012–2014, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
2.2
100
10
V
GS
= 4.5V
V
GS
= 10V
I
D
= 17A
T
C
= 25°C
T
C
= 125°C
2
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (ºC)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
5000
100
T
C
= 25ºC
T
C
= 125ºC
10us
100us
1ms
10ms
DC
1000
100
10
1
Single Pulse
Max R
thetaJC
= 2.0ºC/W
0.1
0.1
10
0.01
1
10
100
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
60
50
40
30
20
10
0
−50 −25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (ºC)
G001
Figure 12.
Maximum Drain Current vs Temperature
6
Copyright © 2012–2014, Texas Instruments Incorporated
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6 Device
and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
6.2 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2012–2014, Texas Instruments Incorporated
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q5A
Package Dimensions
MILLIMETERS
DIM
MIN
0.90
0.33
0.20
4.80
3.61
5.90
5.70
3.38
3.03
1.17
0.27
0.15
0.41
1.10
0.51
0.06
0°
NOM
1.00
0.41
0.25
4.90
3.81
6.00
5.75
3.58
3.13
1.27
0.37
0.25
0.56
—
MAX
1.10
0.51
0.34
5.00
4.02
6.10
5.80
3.78
3.23
1.37
0.47
0.35
0.71
—
A
b
c
D1
D2
E
E1
E2
E3
e
e1
e2
H
K
L
0.61
0.13
—
0.71
0.20
12°
L1
θ
8
Copyright © 2012–2014, Texas Instruments Incorporated
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7.2 Recommended
PCB Pattern
F1
F7
F6
F10
M0139-01
MILLIMETERS
INCHES
DIM
MIN
MAX
6.305
4.56
4.56
0.7
MIN
MAX
0.248
0.18
F1
F2
6.205
4.46
4.46
0.65
0.62
0.63
0.7
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F3
0.18
F4
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.18
F5
0.67
0.68
0.8
F6
F7
F8
0.65
0.62
4.9
0.7
F9
0.67
5
F10
F11
4.46
4.56
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
Copyright © 2012–2014, Texas Instruments Incorporated
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7.3 Recommended
Stencil Opening
(0.020) 8x
0.500
(0.020)
0.500
0.500
(0.020) 8x
1.235
(0.049)
1.585
(0.062)
(0.024)
0.620
(0.170)
4.310
0.385
(0.015)
(0.062)
4x
1.570
(0.050)
1.270
0.615
1.105
(0.024)
(0.044)
3.020
(0.119)
7.4 Q5A
Tape and Reel Information
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
Notes:
1. 10-sprocket
hole-pitch cumulative tolerance ±0.2
2. Camber
not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material:
black static-dissipative polystyrene
4. All
dimensions are in mm (unless otherwise specified).
5. A0
and B0 measured on a plane 0.3 mm above the bottom of the pocket.
10
Copyright © 2012–2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
5-Sep-2014
PACKAGING INFORMATION
Orderable Device
CSD18504Q5A
CSD18504Q5AT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 150
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSONP
VSONP
DQJ
8
8
2500 Pb-Free
(RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
CSD18504
CSD18504
ACTIVE
DQJ
250
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
5-Sep-2014
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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