Texas-Instruments-CSD18534Q5AT
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ZHCSAE1D
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CSD18534Q5A 60V N
沟道
NexFET™
功率
MOSFET
1
特性
产品概要
1
•
•
•
•
•
•
•
•
超低
Q
g
和
Q
gd
T
A
= 25°C
V
DS
典型值
单位
V
低热阻
漏源电压
60
17
雪崩额定值
Q
g
栅极电荷总量
(10V)
栅极电荷（栅极到漏极）
nC
nC
m
Ω
m
Ω
V
逻辑电平
Q
gd
3.5
V
GS
= 4.5V
V
GS
= 10V
1.9
9.9
7.8
无铅引脚镀层
R
DS(on)
漏源导通电阻
V
GS(th)
阈值电压
符合
RoHS
标准
无卤素
小外形尺寸无引线
(SON) 5mm x 6mm
塑料封装
器件
CSD18534Q5A 2500
13
英寸卷带
CSD18534Q5AT 250
7
英寸卷带
数量
包装介质
封装
发货
卷带封装
2
应用
小外形尺寸无引线
(SON) 5mm × 6mm
塑料封装
•
•
•
•
直流
–
直流转换
次级侧同步整流器
隔离式转换器主级侧开关
电机控制
(1)
如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
绝对最大额定值
T
A
= 25°C
值
60
单位
V
3
说明
V
DS
V
GS
漏源电压
此
7.8m
Ω
、
60V
、
SON 5 × 6mm NexFET™
功率
MOSFET
旨在最大限度地降低功率转换应用中的 损
耗。
栅源电压
±20
50
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
T
C
= 25°C
时测得
I
D
69
A
13
229
3.1
77
顶视图
I
DM
P
D
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
功耗，
T
C
= 25°C
T
J
， 工作结温，
–55
至
150
°C
T
stg
储存温度
雪崩能量，单一脉冲
I
D
= 40A
，
L = 0.1mH
，
R
G
= 25
Ω
E
AS
80
mJ
(1) R
θ
JA
= 40°C/W
，这是在厚度为
0.06
英寸的环氧板
(FR4)
印刷
电路板
(PCB)
上的
1
英寸
2
2
盎司的铜过渡垫片上测得的典型
值。
D
D
(2)
最大
R
θ
JC
= 2.0°C/W
，脉冲持续时间
≤
100
μ
s
，占空比
≤
1%
P0093-01
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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R
DS(on)
与
V
GS
对比
栅极电荷
28
10
9
8
7
6
5
4
3
2
1
0
T
C
= 25°C
Id = 14A
T
C
= 125ºC Id = 14A
I
D
= 14A
V
DS
= 30V
24
20
16
12
8
4
0
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
Q
g
– Gate Charge
(nC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
2
版权
© 2012–2015, Texas Instruments Incorporated
ZHCSAE1D
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目录
1
2
3
4
5
7
6
4
修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (August 2014) to Revision D
Page
•
•
Changes from Revision B (July 2014) to Revision C
Page
•
•
•
Changes from Revision A (January 2013) to Revision B
Page
•
•
•
Changes from Original (October 2012) to Revision A
Page
•
Copyright © 2012–2015, Texas Instruments Incorporated
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5 Specifications
5.1 Electrical
Characteristics
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
60
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 48 V
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 4.5 V, I
D
= 14 A
V
GS
= 10 V, I
D
= 14 A
V
DS
= 30 V, I
D
= 14 A
1
100
2.3
μ
A
nA
V
I
GSS
V
GS(th)
1.5
1.9
9.9
7.8
72
12.4
9.8
m
Ω
m
Ω
S
R
DS(on)
g
fs
Drain-to-source on-resistance
Transconductance
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input capacitance
1360
167
5
1770
217
6.5
3
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 30 V, ƒ = 1 MHz
1.5
8.5
17
Q
g
11.1
22
nC
Q
g
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= 30 V, I
D
= 14 A
3.5
3.2
2.6
19
nC
nC
nC
nC
ns
V
DS
= 30 V, V
GS
= 0 V
Turn on delay time
Rise time
5.2
5.5
15
ns
V
DS
= 30 V, V
GS
= 10 V, I
DS
= 14 A, R
G
= 0
Ω
t
d(off)
t
f
Turn off delay time
Fall time
ns
2
ns
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
SD
= 14 A, V
GS
= 0 V
0.8
54
40
1
V
nC
ns
V
DS
= 30 V, I
F
= 14 A, di/dt = 300 A/
μ
s
5.2 Thermal
Information
(T
A
= 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
(1)
Junction-to-ambient thermal resistance
(1
)
(
2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
θ
JC
R
θ
JA
2.0
50
(1)
R
θ
JC
is determined with the device mounted on a 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu.
4
Copyright © 2012–2015, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 50°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2 oz. (0.071 mm thick)
Cu.
Max R
θ
JA
= 125°C/W
when mounted on a
minimum pad area of
2 oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical
MOSFET Characteristics
(T
A
= 25°C unless otherwise stated)
Figure 1.
Transient Thermal Impedance
Copyright © 2012–2015, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
100
60
50
40
30
20
10
0
V
DS
= 5V
80
60
40
V
GS
=10V
V
GS
=6.5V
V
GS
=4.5V
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
20
0
0
0.2
0.4
0.6
0.8
1
1.2
0
0
0
1
2
3
4
5
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
I
D
= 14A
V
DS
= 30V
10
0
4
8
12
16
20
10
20
30
40
50
60
Q
g
– Gate Charge
(nC)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
28
24
20
16
12
8
I
D
= 250uA
T
C
= 25°C
Id = 14A
T
C
= 125ºC Id = 14A
4
0
−75
−25
25
75
125
175
2
4
6
8
10
12
14
16
18
20
T
C
– Case Temperature (ºC)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
Copyright © 2012–2015, Texas Instruments Incorporated
ZHCSAE1D
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Typical MOSFET Characteristics (continued)
(T
A
= 25°C unless otherwise stated)
2.2
100
10
V
GS
= 4.5V
V
GS
= 10V
I
D
= 14A
T
C
= 25°C
T
C
= 125°C
2
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (ºC)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
5000
100
T
C
= 25ºC
T
C
= 125ºC
10us
100us
1ms
10ms
DC
1000
100
10
1
Single Pulse
Max R
thetaJC
= 2.0ºC/W
0.1
0.1
10
0.01
1
10
100
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
70
60
50
40
30
20
10
0
−50 −25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (ºC)
G001
Figure 12.
Maximum Drain Current vs Temperature
版权
© 2012–2015, Texas Instruments Incorporated
7
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6
器件和文档支持
6.1
社区资源
下列链接提供到
TI
社区资源的连接。链接的内容由各个分销商
“
按照原样
”
提供。这些内容并不构成
TI
技术规范，
e2e.ti.com
中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI
参考设计支持
可帮助您快速查找有帮助的
E2E
论坛、设计支持工具以及技术支持的联系信息。
6.2
商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
6.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
8
版权
© 2012–2015, Texas Instruments Incorporated
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7
机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
7.1 Q5A
封装尺寸
毫米
DIM
最小值
0.90
0.33
0.20
4.80
3.61
5.90
5.70
3.38
3.03
1.17
0.27
0.15
0.41
1.10
0.51
0.06
0°
标称值
1.00
0.41
0.25
4.90
3.81
6.00
5.75
3.58
3.13
1.27
0.37
0.25
0.56
—
最大值
1.10
0.51
0.34
5.00
4.02
6.10
5.80
3.78
3.23
1.37
0.47
0.35
0.71
—
A
b
c
D1
D2
E
E1
E2
E3
e
e1
e2
H
K
L
0.61
0.13
—
0.71
0.20
12°
L1
θ
版权
© 2012–2015, Texas Instruments Incorporated
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7.2
建议印刷电路板
(PCB)
布局
建议印刷电路板
(PCB)
布局
(
接下页
)
毫米
英寸
F1
DIM
F7
F6
最小值
6.205
4.46
4.46
0.65
0.62
0.63
0.7
最大值
6.305
4.56
4.56
0.7
最小值
最大值
0.248
0.18
F1
F2
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F3
0.18
F4
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.18
F5
0.67
0.68
0.8
F6
F7
F8
0.65
0.62
4.9
0.7
F9
0.67
5
F10
F10
F11
4.46
4.56
M0139-01
要获得与印刷电路板
(PCB)
设计相关的建议电路布局布线，请参见应用说明
《通过
PCB
布局布线技巧来减少振
7.3
建议模板开口
(0.020) 8x
0.500
(0.020)
0.500
0.500
(0.020) 8x
1.235
(0.049)
1.585
(0.062)
(0.024)
0.620
(0.170)
4.310
0.385
(0.015)
(0.062)
4x
1.570
(0.050)
1.270
0.615
1.105
(0.024)
(0.044)
3.020
(0.119)
10
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7.4 Q5A
卷带信息
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
注：
1. 10
个链齿孔的累积容差为
±0.2
2.
每
100mm
长度的翘曲不能超过
1mm
，在
250mm
长度上不累积
3.
材料：黑色抗静电聚苯乙烯
4.
全部尺寸为
mm
（除非另外注明）。
5.
高于孔眼底部
0.3mm
的平面上测量得到
A0
和
B0
值
.
版权
© 2012–2015, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD18534Q5A
CSD18534Q5AT
ACTIVE
VSONP
VSONP
DQJ
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD18534
CSD18534
ACTIVE
DQJ
RoHS-Exempt
& Green
SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI
均以
“
原样
”
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