Texas-Instruments-CSD25484F4T
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SLPS551A
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CSD25484F4 –20-V P-Channel FemtoFET™ MOSFET
1 Features
Product Summary
1
•
•
•
•
Low On-Resistance
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Ultra-Low Q
g
and Q
gd
Drain-to-Source Voltage
Gate Charge Total (–4.5 V)
Gate Charge Gate-to-Drain
–20
1090
150
Low-Threshold Voltage
Q
g
pC
pC
Ultra-Small Footprint (0402 Case Size)
Q
gd
V
GS
= –1.8 V
V
GS
= –2.5 V
V
GS
= –4.5 V
V
GS
= –8.0 V
–0.95
405
–
1.0 mm × 0.6 mm
Ultra-Low Profile
0.2-mm Height
Integrated ESD Protection Diode
150
93
Drain-to-Source
On-Resistance
•
•
R
DS(on)
m
Ω
–
80
V
GS(th)
Threshold Voltage
V
–
–
Rated > 4-kV HBM
Rated > 2-kV CDM
DEVICE
QTY
MEDIA
PACKAGE
SHIP
•
•
Lead and Halogen Free
RoHS Compliant
CSD25484F4
3000
Femto (0402)
1.00-mm × 0.60-mm
Land Grid Array (LGA)
Tape
and
Reel
7-Inch Reel
CSD25484F4T
250
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Absolute Maximum Ratings
T
A
= 25°C
VALUE
–20
–12
–2.5
–22
–35
–350
500
4
UNIT
•
•
Battery Applications
V
DS
V
GS
I
D
Drain-to-Source Voltage
V
V
A
A
Handheld and Mobile Applications
Gate-to-Source Voltage
Continuous Gate Clamp Current
3 Description
I
DM
This 80-m
Ω
, –20-V, P-Channel FemtoFET™
MOSFET is designed and optimized to minimize the
footprint in many handheld and mobile applications.
This technology is capable of replacing standard
small signal MOSFETs while providing at least a 60%
reduction in footprint size.
I
G
mA
mW
kV
P
D
Human-Body Model (HBM)
Charged-Device Model (CDM)
V
(ESD)
2
T
J
,
T
stg
Operating Junction,
Storage Temperature
–55 to 150
°C
(1) Typical
R
θ
JA
=
85°C/W on 1-in
2
(6.45-cm
2
), 2-oz
(0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4
PCB.
(2) Pulse
duration
≤
100
μ
s, duty cycle
≤
1%.
Typical Part Dimensions
Top View
5
0.20 mm
0.60 mm
D
{
1.00 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
7
Mechanical, Packaging, and Orderable
6
4 Revision
History
Changes from Original (May 2015) to Revision A
Page
•
•
Added the
Receiving Notification of Documentation Updates
and the
Community Resources
sections to
Device and
2
Copyright © 2015–2017, Texas Instruments Incorporated
SLPS551A
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5 Specifications
5.1 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
DS
= –250
μ
A
–20
V
nA
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= –16 V
V
DS
= 0 V, V
GS
= –12 V
V
DS
= V
GS
, I
DS
= –250
μ
A
V
GS
= –1.8 V, I
DS
= –0.1 A
V
GS
= –2.5 V, I
DS
= –0.5 A
V
GS
= –4.5 V, I
DS
= –0.5 A
V
GS
= –8 V, I
DS
= –0.5 A
V
DS
= –10 V, I
DS
= –0.5 A
–100
–50
–1.2
825
180
109
94
I
GSS
V
GS(th)
–0.7
–0.95
405
150
93
R
DS(on)
Drain-to-source on-resistance
Transconductance
m
Ω
80
g
fs
3.5
S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
R
G
Input capacitance
175
78
230
102
7.2
pF
pF
pF
Ω
V
GS
= 0 V, V
DS
= –10 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (–4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
5.5
20
Q
g
1090
150
350
210
1290
9.5
5
1415
pC
pC
pC
pC
pC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
V
DS
= –10 V, I
DS
= –0.5 A
V
DS
= –10 V, V
GS
= 0 V
Turnon delay time
Rise time
V
DS
= –10 V, V
GS
= –4.5 V,
I
DS
= –0.5 A, R
G
= 10
Ω
t
d(off)
t
f
Turnoff delay time
Fall Time
18
8.5
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
SD
= –0.5 A, V
GS
= 0 V
–0.75
970
V
pC
ns
V
DS
= –10 V, I
F
= –0.5 A, di/dt = 100 A/
μ
s
7.5
5.2 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance
(1)
Junction-to-ambient thermal resistance
(2)
TYPICAL VALUES
UNIT
85
R
θ
JA
°C/W
245
(1) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu.
(2) Device
mounted on FR4 material with minimum Cu mounting area.
Copyright © 2015–2017, Texas Instruments Incorporated
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5.3 Typical
MOSFET Characteristics
T
A
= 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
10
9
10
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
9
8
7
6
5
4
3
2
1
0
8
7
6
V
GS
= -1.8 V
5
4
3
2
1
0
V
GS
= -2.5 V
V
GS
= -4.5 V
V
GS
= -8 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
-V
DS
– Drain-to-Source Voltage (V)
-V
GS
– Gate-To-Source Voltage (V)
D002
D003
V
DS
= –5V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4
Copyright © 2015–2017, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
5000
1000
8
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
7
6
5
4
3
2
1
0
100
10
1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
2
4
6
8
10
12
14
16
18
20
Q
g
– Gate Charge (nC)
-V
DS
– Drain-to-Source Voltage (V)
D004
D005
I
D
= –0.5 A
V
DS
= –10 V
Figure 4. Gate Charge
Figure 5. Capacitance
250
225
200
175
150
125
100
75
1.25
1.15
1.05
0.95
0.85
0.75
0.65
0.55
T
C
= 25°C, I
D
= -0.5 A
T
C
= 125°C, I
D
= -0.5 A
50
25
0
-75 -50 -25
0
25
50
75 100
125 150 175
0
2
4
6
8
10
12
T
C
– Case Temperature (
è
C)
-V
GS
– Gate-To-Source Voltage (V)
D006
D007
I
D
= –250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
10
1.4
1.3
1.2
1.1
1
T
C
= 25
è
C
T
C
= 125
è
C
V
GS
= -2.5 V
V
GS
= -8.0 V
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
-75 -50 -25
0
25
50
75 100
125 150 175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (
è
C)
-V
SD
– Source-To-Drain Voltage (V)
D008
D009
I
D
= –0.5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
Copyright © 2015–2017, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
3
2.5
2
100
10
1
1.5
1
0.1
0.5
100 ms
10 ms
1 ms
100 µs
10 µs
0.01
0.01
0
-50
0.1
1
10
50
-25
0
25
50
75
100 125 150 175
-V
DS
– Drain-To-Source Voltage (V)
T
C
– Case Temperature (
è
C)
D010
D011
Single pulse, typical R
θ
JA
= 85°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Maximum Drain Current vs Temperature
6
Copyright © 2015–2017, Texas Instruments Incorporated
SLPS551A
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5
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6 Device
and Documentation Support
6.1 Receiving
Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
6.3 Trademarks
FemtoFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2015–2017, Texas Instruments Incorporated
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical
Dimensions
(1) All
linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
(2) This
drawing is subject to change without notice.
(3) This
package is a PB-free solder land design.
Table 1. Pin Configuration
POSITION
Pin 1
DESIGNATION
Gate
Pin 2
Source
Pin 3
Drain
8
Copyright © 2015–2017, Texas Instruments Incorporated
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7.2 Recommended
Minimum PCB Layout
(0.25)
0.05 MIN
2X (0.25)
PKG
2X (0.15)
1
ALL AROUND
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
(1) All
dimensions are in millimeters.
7.3 Recommended
Stencil Pattern
2X (0.25)
2X (0.2)
PKG
(0.25)
1
SYMM
3
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
(1) All
dimensions are in millimeters.
Copyright © 2015–2017, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
3-Aug-2017
PACKAGING INFORMATION
Orderable Device
CSD25484F4
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 150
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PICOSTAR
PICOSTAR
YJJ
3
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
G3
G3
CSD25484F4T
ACTIVE
YJJ
250
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
4-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CSD25484F4
PICOST
AR
YJJ
YJJ
3
3
3000
250
178.0
9.2
0.7
1.1
0.28
4.0
8.0
Q2
CSD25484F4T
PICOST
AR
178.0
9.2
0.7
1.1
0.28
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
4-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD25484F4
PICOSTAR
PICOSTAR
YJJ
YJJ
3
3
3000
250
220.0
220.0
220.0
220.0
35.0
35.0
CSD25484F4T
Pack Materials-Page 2
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http://www.ti.com/sc/docs/stdterms.htm
) apply to the sale of packaged integrated
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