Texas-Instruments-CSD86336Q3DT
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ZHCSHU1
–
M
ARCH 2018
CSD86336Q3D
同步降压
NexFET™
电源块
1
特性
3
说明
1
•
•
•
•
•
半桥电源块
CSD86336Q3D NexFET™
电源块是面向同步降压 应
用 的优化设计方案，能够以
3.3mm × 3.3mm
的小巧
外形提供高电流、高效率以及高频率性能。该产品针对
5V
栅极驱动 应用进行了优化，在与来自外部控制器
/
驱动器的任一
5V
栅极驱动配套使用时，可提供一套灵
活的解决方案来实现高密度电源。
12A
电流下系统效率高达
93.0%
工作电流高达
20A
高频工作（高达
1.5MHz
）
高密度小外形尺寸无引线
(SON) 3.3mm × 3.3mm
封装
•
•
•
•
•
•
针对
5V
栅极驱动进行了优化
开关损耗较低
俯视图
超低电感封装
V
IN
V
IN
T
G
V
SW
V
SW
V
SW
1
2
3
4
8
7
6
5
符合
RoHS
标准
无卤素
P
GND
无铅引脚镀层
(Pin 9)
2
应用
T
GR
B
G
•
同步降压转换器
P0116-01
–
–
高频 应用
高电流、低占空比 应用
数量
•
•
•
多相位同步降压转换器
器件
介质
封装
发货
负载点
(POL)
直流
/
直流转换器
IMVP
、
VRM
和
VRD “
应用
”
列表的
CSD86336Q3D 13
英寸卷带
2500
CSD86336Q3DT 7
英寸卷带
250
SON
3.30mm × 3.30mm
塑料封装
卷带封
装
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型电路
典型电源块效率与功率损耗
100
95
90
85
80
75
70
65
60
55
50
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
V
IN
BOOT
V
DD
VDD
GND
V
IN
T
G
Control
FET
DRVH
LL
V
SW
T
GR
V
OUT
V
IN
= 12 V
ENABLE
PWM
ENABLE
PWM
V
OUT
= 1.3 V
f
SW
= 500 kHz
V
GS
= 5 V
L
OUT
= 950 nH
T
J
= 25
è
C
Sync
FET
B
G
DRVL
P
GND
CSD86336Q3D
Driver IC
Copyright © 2017, Texas Instruments Incorporated
0
2
4
6
8
10
12
14
16
18
20
Output Current (A)
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ZHCSHU1
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目录
1
2
3
4
5
6.5 Calculating
Power Loss and Safe Operating Area
7
8
9
6
4
修订历史记录
日期
修订版本
说明
2018
年
3
月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
ZHCSHU1
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ARCH 2018
5 Specifications
5.1 Absolute
Maximum Ratings
TA =
25°C (unless otherwise noted)
(1)
MIN
MAX
25
25
27
10
10
60
6
UNIT
V
IN
to P
GND
V
SW
to P
GND
Voltage
V
SW
to P
GND
(10 ns)
T
G
to T
GR
V
–8
–8
B
G
to P
GND
Pulsed current rating, IDM
(2)
A
Power dissipation, P
D
W
Sync FET, I
D
= 40 A, L = 0.1 mH
80
34
150
Avalanche
energy, E
AS
mJ
°C
Control FET, I
D
= 26 A, L = 0.1 mH
T
J
and T
STG
Operating junction and storage temperature
–55
(1) Stresses
beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse
duration = 50 µS. Duty cycle = 0.01.
5.2 Recommended
Operating Conditions
T
A
= 25°C (unless otherwise noted)
MIN
MAX
8
UNIT
V
V
GS
V
IN
Gate drive voltage
4.5
Input supply voltage
(1)
Switching frequency C
BST
= 0.1 µF (min)
Operating current
22
V
ƒ
SW
1500
20
kHz
A
T
J
Operating temperature
Storage temperature
125
125
°C
°C
T
STG
(1) Operating
at high V
IN
can create excessive AC voltage overshoots on the switch node (V
SW
) during MOSFET switching transients. For
reliable operation, the switch node (V
SW
) to ground voltage must remain at or below the
Absolute Maximum Ratings
.
5.3 Thermal
Information
T
A
= 25°C (unless otherwise noted)
THERMAL METRIC
MIN
MAX
105
55
UNIT
°C/W
°C/W
°C/W
°C/W
R
θ
JA
R
θ
JA
R
θ
JC
R
θ
JC
Junction-to-ambient thermal resistance (min Cu)
(1)
Junction-to-ambient thermal resistance (max Cu)
(1) (2)
Junction-to-case thermal resistance (top of package)
(1)
Junction-to-case thermal resistance (P
GND
pin)
(1)
17
3.2
(1)
R
θ
JC
is determined with the device mounted on a 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R
θ
JC
is specified by design while R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
) Cu.
5.4 Power
Block Performance
T
A
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.8
10
MAX
UNIT
W
V
IN
= 12 V, V
GS
= 5 V, V
OUT
= 1.3 V, I
OUT
= 15 A,
ƒ
SW
= 500 kHz, L
OUT
= 950 nH, T
J
= 25°C
P
LOSS
I
QVIN
Power loss
(1)
V
IN
quiescent current
(1)
T
G
to T
GR
= 0 V, B
G
to P
GND
= 0 V, V
IN
= 12 V
µA
(1) Measurement
made with six 10-
μ
F (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V
IN
to P
GND
pins and
using a high-current 5-V driver IC.
Copyright © 2018, Texas Instruments Incorporated
3
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5.5 Electrical
Characteristics – Q1 Control FET
T
j
= 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
DS
= 250 µA
25
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 20 V
1
100
1.9
µA
nA
V
I
GSS
V
DS
= 0 V, V
GS
= +10 / –8 V
V
DS
= V
GS
, I
DS
= 250 µA
V
GS(th)
1.1
1.5
9.1
40
V
IN
= 12 V, V
GS
= 5 V, V
OUT
= 1.3 V,
I
OUT
= 20 A, ƒ
SW
= 500 kHz,
L
OUT
= 950 nH
Z
DS(on)
Effective AC on-impedance
m
Ω
g
fs
Transconductance
V
DS
= 2.5 V, I
DS
= 14 A
S
DYNAMIC CHARACTERISTICS
C
ISS
C
OSS
C
RSS
R
G
Input capacitance
380
263
14.1
4.0
2.9
0.6
1.4
0.6
5.4
5
494
342
18.3
8.0
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge – gate-to-drain
Gate charge – gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 12.5 V, ƒ = 1 Mhz
Q
g
3.8
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
OSS
t
d(on)
t
r
V
DS
= 12.5 V, I
DS
= 14 A
V
DS
= 12.5 V, V
GS
= 0 V
Turn on delay time
Rise time
10
V
DS
= 12.5 V, V
GS
= 4.5 V, I
DS
= 14 A,
R
G
= 0
Ω
t
d(off)
t
f
Turn off delay time
Fall time
7
2
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
DS
= 14 A, V
GS
= 0 V
0.86
14.7
15
1.0
V
nC
ns
V
DS
= 12.5 V, I
F
= 14 A, di/dt = 300 A/µs
4
Copyright © 2018, Texas Instruments Incorporated
ZHCSHU1
–
M
ARCH 2018
5.6 Electrical
Characteristics – Q2 Sync FET
T
j
= 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
DS
= 250 µA
25
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 20 V
1
100
1.6
µA
nA
V
I
GSS
V
DS
= 0 V, V
GS
= +10 / –8 V
V
DS
= V
GS
, I
DS
= 250 µA
V
GS(th)
1.0
1.3
3.4
57
V
IN
= 12 V, V
GS
= 5 V, V
OUT
= 1.3 V,
I
OUT
= 20 A, ƒ
SW
= 500 kHz,
L
OUT
= 950 nH
Z
DS(on)
Effective AC on-impedance
m
Ω
g
fs
Transconductance
V
DS
= 2.5 V, I
DS
= 14 A
S
DYNAMIC CHARACTERISTICS
C
ISS
C
OSS
C
RSS
R
G
Input capacitance
728
501
26
970
664
33
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge – gate-to-drain
Gate charge – gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 12.5 V, ƒ = 1 Mhz
0.65
5.7
1.2
2.1
1.0
10.3
4
1.3
7.4
Q
g
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
OSS
t
d(on)
t
r
V
DS
= 12.5 V, I
DS
= 14 A
V
DS
= 12.5 V, V
GS
= 0 V
Turn on delay time
Rise time
10
V
DS
= 12.5 V, V
GS
= 4.5 V, I
DS
= 14 A,
R
G
= 0
Ω
t
d(off)
t
f
Turn off delay time
Fall time
8
2
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
DS
= 14 A, V
GS
= 0 V
0.82
25.4
18
0.95
V
nC
ns
V
DS
= 12.5 V, I
F
= 14 A, di/dt = 300 A/µs
Max R
θ
JA
= 105°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
Max R
θ
JA
= 55°C/W
when mounted on 1 in
2
(6.45 cm
2
) of 2-oz
(0.071-mm) thick Cu.
版权
© 2018, Texas Instruments Incorporated
5
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5.7 Typical
Power Block Device Characteristics
Test conditions: V
IN
= 12 V, V
DD
= 5 V, ƒ
SW
= 500 kHz, V
OUT
= 1.3 V, L
OUT
= 0.95 µH, I
OUT
= 20 A, T
J
= 125°C, unless stated
otherwise.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0
2
4
6
8
10
12
14
16
18
20
-50
-25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (
è
C)
D001
D002
图
1. Power Loss vs Output Current
图
2. Power Loss vs Temperature
25
20
15
10
5
0
0
20
40
60
80
100
120
140
Board Temperature (
è
C)
D005
(1)
图
3. Typical Safe Operating Area (SOA)
(1) The
Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W)
× 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See
Application and Implementation
section for detailed
explanation.
6
版权
© 2018, Texas Instruments Incorporated
ZHCSHU1
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M
ARCH 2018
Typical Power Block Device Characteristics (
接下页
)
Test conditions: V
IN
= 12 V, V
DD
= 5 V, ƒ
SW
= 500 kHz, V
OUT
= 1.3 V, L
OUT
= 0.95 µH, I
OUT
= 20 A, T
J
= 125°C, unless stated
otherwise.
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
3.9
3.4
2.9
2.4
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
2.9
2.4
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
100
300
500
700
900 1100
1300 1500 1700
0
2
4
6
8
10
12
14
16
18
Switching Frequency (kHz)
Input Voltage (V)
D006
D007
图
4. Normalized Power Loss vs Switching Frequency
图
5. Normalized Power Loss vs Input Voltage
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
5.9
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
4.9
3.9
2.9
2.0
1.0
0.0
-1.0
-2.0
0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
Output Voltage (V)
50
200
350
500
650
800
950
1100
Output Inductance (nH)
D008
D009
图
6. Normalized Power Loss vs Output Voltage
图
7. Normalized Power Loss vs Output Inductance
版权
© 2018, Texas Instruments Incorporated
7
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ARCH 2018
5.8 Typical
Power Block MOSFET Characteristics
T
A
= 25°C, unless stated otherwise.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
20
V
GS
= 4.5 V
V
GS
= 6 V
V
GS
= 8.0 V
V
GS
= 4.5 V
V
GS
= 6 V
V
GS
= 8.0 V
10
0
0
0.3
0.6
0.9
1.2
1.5
1.8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
D010
D011
图
8. Control MOSFET Saturation
图
9. Sync MOSFET Saturation
100
100
10
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D012
D013
V
DS
= 5 V
V
DS
= 5 V
图
10. Control MOSFET Transfer
图
11. Sync MOSFET Transfer
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
0
0
0
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
Q
g
– Gate Charge (nC)
Q
g
– Gate Charge (nC)
D014
D015
I
D
= 14 A
V
DD
= 12.5 V
I
D
= 14 A
V
DD
= 12.5 V
图
12. Control MOSFET Gate Charge
图
13. Sync MOSFET Gate Charge
8
版权
© 2018, Texas Instruments Incorporated
ZHCSHU1
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ARCH 2018
Typical Power Block MOSFET Characteristics (
接下页
)
T
A
= 25°C, unless stated otherwise.
5000
10000
1000
100
10
1000
100
10
1
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
1
0
5
10
15
20
25
0
5
10
15
20
25
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
D016
D017
图
14. Control MOSFET Capacitance
图
15. Sync MOSFET Capacitance
1.9
1.7
1.5
1.3
1.1
0.9
0.7
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-75 -50 -25
0
25
50
75 100
125 150 175
-75 -50 -25
0
25
50
75 100
125 150 175
T
C
– Case Temperature (°C)
T
C
– Case Temperature (°C)
D018
D019
I
D
= 250 µA
I
D
= 250 µA
图
16. Control MOSFET V
GS(th)
图
17. Sync MOSFET V
GS(th)
20
18
16
14
12
10
8
10
T
C
= 25°C, I
D
= 14 A
T
C
= 125°C, I
D
= 14 A
T
C
= 25°C, I
D
= 14 A
T
C
= 125°C, I
D
= 14 A
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D020
D021
图
18. Control MOSFET R
DS(on)
vs V
GS
图
19. Sync MOSFET R
DS(on)
vs V
GS
版权
© 2018, Texas Instruments Incorporated
9
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ARCH 2018
Typical Power Block MOSFET Characteristics (
接下页
)
T
A
= 25°C, unless stated otherwise.
1.6
1.4
1.2
1
1.6
V
GS
= 4.5 V
V
GS
= 8.0 V
V
GS
= 4.5 V
V
GS
= 8.0 V
1.4
1.2
1
0.8
0.8
0.6
0.6
-75 -50 -25
0
25
50
75 100
125 150 175
-75 -50 -25
0
25
50
75 100
125 150 175
T
C
– Case Temperature (°C)
T
C
– Case Temperature (°C)
D022
D023
I
D
= 14 A
V
GS
= 4.5 V
I
D
= 14 A
V
GS
= 4.5 V
图
20. Control MOSFET Normalized R
DS(on)
图
21. Sync MOSFET Normalized R
DS(on)
100
100
T
C
= 25°C
T
C
= 25°C
T
C
= 125°C
T
C
= 125°C
10
1
10
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
V
SD
– Source-to-Drain Voltage (V)
V
SD
– Source-to-Drain Voltage (V)
D024
D025
图
22. Control MOSFET Body Diode
图
23. Sync MOSFET Body Diode
100
10
1
100
10
1
T
C
= 25
è
C
T
C
= 125
è
C
T
C
= 25
è
C
T
C
= 125
è
C
0.01
0.1
1
0.01
0.1
1
T
AV
– Time in Avalanche (ms)
T
AV
– Time in Avalanche (ms)
D026
D027
图
24. Control MOSFET Unclamped Inductive Switching
图
25. Sync MOSFET Unclamped Inductive Switching
10
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6 Application
and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application
Information
6.1.1 Equivalent
System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see
图
26
). As such, optimization of the power semiconductors in these applications, needs to go beyond simply
reducing R
DS(ON)
.
Power Stage
Components
Power Block
Components
C
i
+
–
Input
Supply
Control
FET
Driver
Driver
PWM
L
o
I
L
Switch
Node
C
o
Sync
FET
Load
Copyright © 2017, Texas Instruments Incorporated
图
26. Synchronous
Buck Topology
The CSD86336Q3D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with Q
GD
, Q
GS
, and Q
RR
. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see
图
27
). A key challenge
solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI).
CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and
reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection
process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be
modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of
switching loss equations are outlined in
Power Loss Calculation With Common Source Inductance Consideration
for Synchronous Buck Converters
(SLPA009).
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Application Information (
接下页
)
Input
Supply
R
PCB
C
ESR
L
DRAIN
C
INPUT
Control
FET
Driver
PWM
C
ESL
L
SOURCE
Switch
Node
L
o
C
o
I
L
Load
L
DRAIN
C
TOTAL
Sync
FET
Driver
L
SOURCE
图
27. Elimination
of Common Source Inductance
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar R
DS(ON)
and MOSFET
CSD86336Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86336Q3D clearly highlights the importance of considering the effective AC on-impedance
(Z
DS(ON)
) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
R
DS(ON)
specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
96
94
92
90
88
86
84
82
80
4.8
4.2
3.6
3.0
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/4.6 m
W
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/4.6 m
W
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/3.4 m
W
V
GS
= 5 V
V
IN
= 12 V
V
OUT
= 1.3 V
V
GS
= 5 V
V
IN
= 12 V
V
OUT
= 1.3 V
L
OUT
= 950 nH
f
SW
= 500 kHz
T
A
= 25
è
C
2.4 L
OUT
= 950 nH
f
SW
= 500 kHz
T
A
= 25
è
C
1.8
1.2
0.6
0.0
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/4.6 m
W
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/4.6 m
W
PowerBlock HS/LS R
DS(ON)
= 9.1 m
W
/3.4 m
W
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Output Current (A)
Output Current (A)
D030
D031
图
28. Efficiency
图
29. Power Loss
12
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Application Information (
接下页
)
表
1
compares the traditional DC measured R
DS(ON)
of CSD86336Q3D versus its Z
DS(ON)
. This comparison takes
into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured R
DS(ON)
values that are equivalent to the Z
DS(ON)
value of CSD86336Q3D in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
表
1. Comparison of R
DS(ON)
vs Z
DS(ON)
HS
LS
PARAMETER
TYP
9.1
MAX
—
TYP
3.4
MAX
—
Effective AC on-impedance Z
DS(ON)
(V
GS
= 5 V)
DC measured R
DS(ON)
(V
GS
= 4.5 V)
9.1
11.4
4.6
5.7
The CSD86336Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-
centric environment. System-level performance curves such as power loss, safe operating area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.2 Power
Loss Curves
MOSFET centric parameters such as R
DS(ON)
and Q
gd
are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves.
图
1
plots the power loss of the CSD86336Q3D as a function of load current. This curve is
measured by configuring and running the CSD86336Q3D as it would be in the final application (see
图
30
). The
measured power loss is the CSD86336Q3D loss and consists of both input conversion loss and gate drive loss.
(V
IN
× I
IN
) + (V
DD
× I
DD
) – (V
SW_AVG
× I
OUT
) = power loss
(1)
The power loss curve in
图
1
is measured at the maximum recommended junction temperatures of 125°C under
isothermal test conditions.
6.3 Safe
Operating Area (SOA) Curves
The SOA curve in the CSD86336Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss.
图
3
outlines the temperature
conditions required for a given load current. The area under the curve dictates the safe operating area. All the
curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in
(T) and 6 copper layers of 1-oz copper thickness.
6.4 Normalized
Curves
The normalized curves in the CSD86336Q3D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change in system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
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Normalized Curves (
接下页
)
Input Current (I
IN
)
Gate Drive
Current (I
DD
)
V
IN
A
V
BOOT
DRVH
LL
V
DD
A
VDD
Input Voltage (V
IN
)
V
IN
Control
Gate Drive
V
T
G
FET
Voltage (V
DD
)
ENABLE
PWM
Output Current (I
OUT
V
OUT
)
V
SW
A
T
GR
Sync
FET
PWM
B
G
DRVL
GND
P
GND
Averaged Switch
V
Node Voltage
Averaging
Circuit
CSD86336Q3D
Driver IC
(V
SW_AVG
)
Copyright © 2017, Texas Instruments Incorporated
图
30. Typical
Application
6.5 Calculating
Power Loss and Safe Operating Area (SOA)
The user can estimate power loss and SOA boundaries by arithmetic means (see
Design Example
). Though the
power loss and SOA curves in this data sheet are taken for a specific set of
test conditions,
the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
6.5.1 Design
Example
Operating conditions:
•
•
•
•
•
Output current = 18.0 A
Input voltage = 5.0 V
Output voltage = 1.8 V
Switching frequency = 750 kHz
Inductor = 290 nH
6.5.2 Calculating
Power Loss
•
•
•
•
•
•
Final calculated power loss = 3.03 W × 1.1 × 1.07 × 1.08 × 1.0
≈
3.85 W
6.5.3 Calculating
SOA Adjustments
•
•
•
•
•
Final calculated SOA adjustment = 1.0 + 0.68 + 0.75 + 0.02
≈
2.45°C
14
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Calculating Power Loss and Safe Operating Area (SOA) (
接下页
)
In the design example above, the estimated power loss of the CSD86336Q3D would increase to 3.85 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 2.45°C.
图
31
graphically shows how the SOA curve would be adjusted accordingly.
1. Start
by drawing a horizontal line from the application current to the SOA curve.
2. Draw
a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust
the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 2.45°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
图
31. Power
Block SOA
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7 Layout
7.1 Recommended
Schematic Overview
There are several critical components that must be used in conjunction with this power block device.
图
32
shows a portion of a schematic with the critical components needed for proper operation.
•
•
•
•
•
•
•
•
C22: Bypass capacitor for V
IN
to help with ringing reduction
C20: Bootstrap capacitor
C21: Bypass capacitor for V
DD
C7-C14: Bypass capacitors for V
IN
(minimum of 40 µF)
C15: Electrolytic capacitor for V
IN
R14, R16: Place holder for gate resistor (optional)
R15: Place holder for bootstrap resistor (optional)
R17, C16: Place holder for snubber (optional)
+VIN
GND
GND
GND
GND
GND
GND
L1
GND
GND
GND
Q1
GND
Vin
1
Vsw
8
7
6
5
V_OUT
HS
0603
R15
Vsw
LS
0603
0
C20
R16
0.
1
µ
F
3
4
Tg
Vsw
Bg
U2
BOOT
0
1
2
3
4
8
7
6
5
0603
HG
+PWM
Tgr
PWM PHASE
Pgnd
R9
0
ENABLE
GND
LG
FCCM
VCC
0603
CSD86336Q3D
+VDD
GND
GND
GND
C21
1
0
µ
F
0603
GND
GND
GND
R14
0
0603
Copyright © 2017, Texas Instruments Incorporated
图
32. Recommended
Schematic
16
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7.2 Recommended
PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter follows.
7.2.1 Electrical
Performance
The power block has the ability to switch at voltage rates greater than 10 kV/
μ
s. Special care must be taken with
the PCB layout design and placement of the input capacitors, inductor, driver IC and output capacitors.
•
The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see
图
33
). It is
recommended that one 3.3-nF (or similar), 0402, 50-V ceramic capacitor be placed on the top side of the
board as close as possible to VIN and PGND pins. In addition, a minimum of 40
μ
F of bulk ceramic
capacitance should be placed as close as possible to the power block in a design. For high-density design,
some of these ceramic capacitors can be placed on the bottom layer of PCB with appropriate number of vias
interconnecting both layers.
•
•
The driver IC should be placed relatively close to the power block gate pins. T
G
and B
G
should connect to the
outputs of the driver IC. The T
GR
pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1.0
Ω
to 4.7
Ω
depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
Theory, Design and Application
(SLUP100) for more details on how to properly tune the RC snubber values.
(1)
(1) Keong
W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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Recommended PCB Design Overview (
接下页
)
7.2.2 Thermal
Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The examples in
图
33
and
图
34
use vias with a 10-mil drill
hole and a 16-mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
图
33. Recommended
PCB Layout (Top Down View)
图
34. Recommended
PCB Layout (Bottom View)
18
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8
器件和文档支持
8.1
接收文档更新通知
要接收文档更新通知，请导航至
TI.com
上的器件产品文件夹。请单击右上角的
提醒我
进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
8.2
社区资源
下列链接提供到
TI
社区资源的连接。链接的内容由各个分销商
“
按照原样
”
提供。这些内容并不构成
TI
技术规范，
e2e.ti.com
中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI
参考设计支持
可帮助您快速查找有帮助的
E2E
论坛、设计支持工具以及技术支持的联系信息。
8.3
商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
8.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
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9
机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
9.1 Q3D
封装尺寸
3.4
3.2
A
B
PIN 1 INDEX AREA
3.4
3.2
C
1.05 MAX
SEATING PLANE
0.08
0.05
0.00
C
1.8 0.1
2X (0.98)
(0.2) TYP
4X (0.2)
4
EXPOSED
THERMAL PAD
6X 0.65
5
2X
9
SYMM
1.95
2.7 0.1
8
1
0.40
0.28
8X
0.32
0.12
SYMM
0.1
C A B
0.5
0.4
8X
0.05
C
4218873/A 10/2016
1.
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合
ASME Y14.5M
标准。
2.
本图如有变更，恕不另行通知。
3.
封装散热焊盘必须焊接在印刷电路板上，以实现最佳的散热和机械性能。
9.2
引脚配置
位置
名称
V
IN
引脚
1
引脚
2
引脚
3
引脚
4
引脚
5
引脚
6
引脚
7
引脚
8
引脚
9
V
IN
T
G
T
GR
B
G
V
SW
V
SW
V
SW
P
GND
20
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9.3
焊盘图案建议
(1.8)
2X (0.65)
(
0.2) VIA
PKG
TYP
2X (0.65)
(0.22)
6X (0.65)
6X (0.34)
1
8
2X (0.34)
METAL UNDER
SOLDER MASK
9
PKG
(2.7)
SOLDER MASK
OPENING
3
4
2X (1.1)
6X (0.65)
5
(R0.05) TYP
4X (0.5)
4X (0.2)
2X (1.18)
(3.05)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
PREFERRED FOR PADS 3-9
SOLDER MASK
DEFINED
PADS 1 & 2 (OPTIONAL FOR OTHERS)
1.
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合
ASME Y14.5M
标准。
3.
根据应用决定是否选用过孔，详情请参见器件产品说明书。如果实现了部分或全部过孔，则会显示建议的过孔
位置。
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9.4
模版建议
2X (1.63)
PKG
2X (0.65)
(0.22)
6X (0.65)
6X (0.34)
9
1
8
2X (0.34)
2X
(1.19)
METAL UNDER
SOLDER MASK
PKG
2X (3.34)
3
4
2X
(0.695)
6X (0.65)
5
(R0.05) TYP
METAL
TYP
4X (0.22)
2X (1.18)
(3.05)
4X (0.36)
1.
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合
ASME Y14.5M
标准。
2.
具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。
IPC-7525
可能提供替代设计建议。
22
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PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD86336Q3D
CSD86336Q3DT
ACTIVE
VSON-CLIP
VSON-CLIP
DPB
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
86336D
86336D
ACTIVE
DPB
RoHS-Exempt
& Green
SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension
designed to accommodate the component width
B0 Dimension
designed to accommodate the component length
K0 Dimension
designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch
between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CSD86336Q3D
CSD86336Q3DT
VSON-
CLIP
DPB
DPB
8
8
2500
250
330.0
12.4
3.6
3.6
1.2
8.0
12.0
Q1
VSON-
CLIP
330.0
12.4
3.6
3.6
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD86336Q3D
CSD86336Q3DT
VSON-CLIP
VSON-CLIP
DPB
DPB
8
8
2500
250
336.6
336.6
336.6
336.6
41.3
41.3
Pack Materials-Page 2
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