Texas-Instruments-CSD86360Q5D
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CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
Synchronous Buck NexFET™ Power B
l
ock
1
FEATURES
DESCRIPTION
The CSD86360Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high current, high efficiency, and high
frequency capability in a small 5-mm × 6-mm outline.
Optimized for 5V gate drive applications, this product
offers a flexible solution capable of offering a high
density power supply when paired with any 5V gate
drive from an external controller/driver.
2
•
•
•
•
•
•
•
•
•
•
•
Half-Bridge Power Block
91% system Efficiency at 25A
Up To 50A Operation
High Frequency Operation (Up To 1.5MHz)
High Density – SON 5-mm × 6-mm Footprint
Optimized for 5V Gate Drive
Low Switching Losses
TEXT ADDED FOR SPACING
Top View
Ultra Low Inductance Package
RoHS Compliant
V
IN
V
IN
T
G
V
SW
V
SW
V
SW
1
2
3
4
8
7
6
5
Halogen Free
Pb-Free Terminal Plating
P
GND
(Pin 9)
APPLICATIONS
T
GR
B
G
•
Synchronous Buck Converters
P0116-01
–
–
High Frequency Applications
TEXT ADDED FOR SPACING
ORDERING INFORMATION
High Current, Low Duty Cycle Applications
•
•
•
Multiphase Synchronous Buck Converters
POL DC-DC Converters
Device
Package
Media
Qty
Ship
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD86360Q5D
2500
IMVP, VRM, and VRD Applications
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS
TYPICAL CIRCUIT
100
90
80
70
60
50
40
30
7
6
5
V
GS
= 5V
V
IN
= 12V
V
OUT
= 1.3V
L
OUT
= .29µH
f
SW
= 500kHz
T
A
= 25ºC
4
3
2
1
0
0
5
10
15
20
25
Output Current (A)
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
T
A
= 25°C (unless otherwise noted)
Parameter
Conditions
VALUE
UNIT
MIN
MAX
25
V
IN
to P
GND
V
SW
to P
GND
V
25
Voltage range
V
SW
to P
GND
(10 ns)
T
G
to T
GR
27
-8
-8
10
V
V
B
G
to P
GND
10
(2)
Pulsed Current Rating, I
DM
120
13
A
(3)
Power Dissipation, P
D
W
Sync FET, I
D
= 110A, L = 0.1mH
Control FET, I
D
= 61A, L = 0.1mH
605
186
150
Avalanche Energy E
AS
mJ
°C
Operating Junction and Storage Temperature Range, T
J
, T
STG
-55
(1) Stresses
beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse
Duration
≤
50 µS. Duty cycle
≤
0.01.
(3)
T
PCB
≤
95°C.
RECOMMENDED OPERATING CONDITIONS
T
A
= 25° (unless otherwise noted)
Parameter
Conditions
MIN
MAX
8
UNIT
V
Gate Drive Voltage, V
GS
Input Supply Voltage, V
IN
4.5
22
V
Switching Frequency, f
SW
Operating Current
C
BST
= 0.1
μ
F (min)
200
1500
50
kHz
A
Operating Temperature, T
J
125
°C
POWER BLOCK PERFORMANCE
T
A
= 25° (unless otherwise noted)
Parameter
Conditions
V
IN
= 12V, V
GS
= 5V,
MIN
TYP
MAX
UNIT
V
OUT
= 1.3V, I
OUT
= 25A,
f
SW
= 500kHz,
L
OUT
= 0.3µH, T
J
= 25ºC
(1)
Power Loss, P
LOSS
2.6
10
W
T
G
to T
GR
= 0V
B
G
to P
GND
= 0V
V
IN
Quiescent Current, I
QVIN
µA
(1) Measurement
made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V
IN
to P
GND
pins and
using a high current 5V driver IC.
2
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
THERMAL INFORMATION
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
(1)
Junction to ambient thermal resistance (Min Cu)
Junction to ambient thermal resistance (Max Cu)
102
R
θ
JA
(2
)
(
1)
50
°C/W
20
(1)
Junction to case thermal resistance (Top of package)
R
θ
JC
(1)
Junction to case thermal resistance (P
GND
Pin)
2
(1)
R
θ
JC
is determined with the device mounted on a 1-inch
2
(6.45-cm
2
), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. R
θ
JC
is specified by design while R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1-inch
2
(6.45-cm
2
) Cu.
Copyright © 2012–2013, Texas Instruments Incorporated
3
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
ELECTRICAL CHARACTERISTICS
T
A
= 25°C (unless otherwise stated)
Q1 Control FET
Q2 Sync FET
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNIT
Static Characteristics
BV
DSS
I
DSS
Drain to Source Voltage
V
GS
= 0V, I
DS
= 250
μ
A
25
25
V
Drain to Source Leakage
Current
V
GS
= 0V, V
DS
= 20V
1
100
2.1
1
100
μ
A
nA
V
Gate to Source Leakage
Current
I
GSS
V
DS
= 0V, V
GS
= +10 / -8
Gate to Source Threshold
Voltage
V
GS(th)
V
DS
= V
GS
, I
DS
= 250
μ
A
1
0.75
1.15
V
In
= 12V, V
DD
= 5V, V
Out
=
Drain to Source On
Impedance
Z
DS(on)
g
fs
1.3V I
Out
= 25A, f
SW
=
3.7
0.7
m
Ω
500kHz, L
Out
= 0.3
μ
H
Transconductance
V
DS
= 10V, I
DS
= 20A
113
169
S
Dynamic Characteristics
(1)
C
ISS
Input Capacitance
Output Capacitance
1590
840
2060
1090
3910
1970
5080
2560
pF
pF
(1)
C
OSS
V
GS
= 0V, V
DS
= 12.5V,
f = 1MHz
Reverse Transfer
C
RSS
R
G
42
1.2
9.7
54
2.5
53
1.1
23
69
2.2
30
pF
Ω
(1)
Capacitance
(1)
Series Gate Resistance
Gate Charge Total (4.5V)
Q
g
12.6
nC
(1)
Gate Charge – Gate to
Drain
Q
gd
Q
gs
2.3
3.5
3.6
6.0
nC
nC
V
DS
= 12.5V,
I
DS
= 20A
Gate Charge – Gate to
Source
Q
g(th)
Q
OSS
t
d(on)
t
r
Gate Charge at Vth
Output Charge
Turn On Delay Time
Rise Time
1.9
15.1
8.4
3.5
33
nC
nC
ns
ns
ns
ns
V
DS
= 12.5V, V
GS
= 0V
9.5
20.4
14.5
4.3
14.8
29.3
6.6
V
DS
= 12.5V, V
GS
= 4.5V,
I
DS
= 20A, R
G
= 2
Ω
t
d(off)
t
f
Turn Off Delay Time
Fall Time
Diode Characteristics
V
SD
Q
rr
t
rr
Diode Forward Voltage
I
DS
= 20A, V
GS
= 0V
0.85
27
1
.75
50
34
.82
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
V
dd
= 12V, I
F
= 20A,
di/dt = 300A/
μ
s
22
(1) Specified
by design
HD
LD
HD
LD
Max R
θ
JA
= 50°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of 2-
oz. (0.071-mm thick)
Cu.
Max R
θ
JA
= 102°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
LG HS
HG
LG HS
LS
HG
LS
M0189-01
M0190-01
4
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
T
J
= 125°C, unless stated otherwise.
14
12
10
8
1.4
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.3µH
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.3µH
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
6
4
2
0
0
5
10
15
20
25
30
35
40
45
50
−50
−25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (ºC)
G001
G001
Figure 1. Power Loss vs Output Current
Figure 2. Normalized Power Loss vs Temperature
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.3µH
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.3µH
400LFM
200LFM
100LFM
Nat Conv
400LFM
200LFM
100LFM
Nat Conv
0
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (ºC)
Ambient Temperature (ºC)
G001
G001
Figure 3. Safe Operating Area – PCB Vertical Mount
(1)
Figure 4. Safe Operating Area – PCB Horizontal Mount
(1)
60
55
50
45
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
120
140
Board Temperature (ºC)
G001
Figure 5. Typical Safe Operating Area
(1)
(1) The
Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
Copyright © 2012–2013, Texas Instruments Incorporated
5
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
T
J
= 125°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.5
1.4
1.3
1.2
1.1
1
24.1
20.1
16.1
12.1
8.0
1.6
1.5
1.4
1.3
1.2
1.1
1
24.1
20.1
16.1
12.1
8.0
V
IN
= 12V
V
GS
= 5V
V
GS
= 5V
V
OUT
= 1.3V
L
OUT
= 0.3µH
f
SW
= 500kHz
I
OUT
= 50A
V
OUT
= 1.3V
L
OUT
= 0.3µH
I
OUT
= 50A
4.0
4.0
0.0
0.0
0.9
0.8
−4.0
−8.0
0.9
0.8
−4.0
−8.0
0
200
400
600
800 1000
1200 1400
1550
2
4
6
8
10 12 14 16 18 20 22 24
Input Voltage (V)
Switching Frequency (kHz)
G001
G001
Figure 6. Normalized Power Loss vs Switching Frequency
Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.2
2
45.7
38.1
30.5
22.9
15.2
7.6
1.5
1.4
1.3
1.2
1.1
1
20.1
V
IN
= 12V
V
GS
= 5V
V
IN
= 12V
V
GS
= 5V
16.1
12.1
8
f
SW
= 500kHz
L
OUT
= 0.3µH
I
OUT
= 50A
V
OUT
= 1.3V
f
SW
= 500kHz
I
OUT
= 50A
1.8
1.6
1.4
1.2
1
4
0
0
0.9
0.8
−4
−8
0.8
0.6
−7.6
−15.2
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Inductance (µH)
1
1.1
Output Voltage (V)
G001
G001
Figure 8. Normalized Power Loss vs. Output Voltage
Figure 9. Normalized Power Loss vs. Output Inductance
6
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
T
A
= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
80
60
40
20
0
200
180
160
140
120
100
80
60
V
GS
= 8.0V
V
GS
= 4.5V
V
GS
= 4.0V
V
GS
= 8.0V
V
GS
= 4.5V
V
GS
= 4.0V
40
20
0
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0
0
0.1
0.2
0.3
0.4
0.5
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 10.
Control MOSFET Saturation
TEXT ADDED FOR SPACING
Figure 11. Sync MOSFET Saturation
TEXT ADDED FOR SPACING
100
10
100
10
V
DS
= 5V
V
DS
= 5V
1
1
0.1
0.1
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
0.01
0.001
0.01
0.001
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
Figure 12. Control MOSFET Transfer
TEXT ADDED FOR SPACING
Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
I
D
= 20A
V
DD
= 12.5V
I
D
= 20A
V
DD
= 12.5V
4
8
12
16
20
24
5
10 15 20 25 30 35 40 45 50 55
Q
g
– Gate Charge
(nC)
Q
g
– Gate Charge
(nC)
G001
G001
Figure 14. Control MOSFET Gate Charge
Figure 15. Sync MOSFET Gate Charge
Copyright © 2012–2013, Texas Instruments Incorporated
7
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
T
A
= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
f = 1MHz
V
GS
= 0V
f = 1MHz
V
GS
= 0V
0
5
10
15
20
25
0
5
10
15
20
25
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 16. Control MOSFET Capacitance
TEXT ADDED FOR SPACING
Figure 17. Sync MOSFET Capacitance
TEXT ADDED FOR SPACING
1.8
1.6
1.4
1.2
1
1.4
1.2
1
I
D
= 250µA
I
D
= 250µA
0.8
0.6
0.4
0.2
0.8
0.6
−75
−25
25
75
125
175
−75
−25
25
75
125
175
T
C
– Case Temperature (ºC)
T
C
– Case Temperature (ºC)
G001
G001
Figure 18. Control MOSFET V
GS(th)
TEXT ADDED FOR SPACING
Figure 19. Sync MOSFET V
GS(th)
TEXT ADDED FOR SPACING
15
15
I
D
= 20A
T
C
= 25°C
T
C
= 125ºC
I
D
= 20A
T
C
= 25°C
T
C
= 125ºC
12
9
12
9
6
6
3
3
0
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to- Source Voltage (V)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
Figure 20. Control MOSFET R
DS(on)
vs V
GS
Figure 21. Sync MOSFET R
DS(on)
vs V
GS
8
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
T
A
= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.4
1.2
1
1.6
1.4
1.2
1
I
D
= 20A
V
GS
= 8V
I
D
= 20A
V
GS
= 8V
0.8
0.6
0.8
0.6
−75
−25
25
75
125
175
−75
−25
25
75
125
175
T
C
– Case Temperature – ºC
T
C
– Case Temperature – ºC
G001
G001
Figure 22. Control MOSFET Normalized R
DS(on)
TEXT ADDED FOR SPACING
Figure 23. Sync MOSFET Normalized R
DS(on)
TEXT ADDED FOR SPACING
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
T
C
= 25°C
T
C
= 125°C
T
C
= 25°C
T
C
= 125°C
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8 1
V
SD
− Source-to-Drain Voltage (V)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
Figure 24. Control MOSFET Body Diode
TEXT ADDED FOR SPACING
Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING
200
100
200
100
T
C
= 25°C
T
C
= 25°C
T
C
= 125°C
T
C
= 125°C
10
0.01
10
0.01
0.1
1
10
0.1
1
10
t
– Time in Avalanche (ms)
t
(
AV
)
– Time in Avalanche (ms)
(
AV
)
G001
G001
Figure 26. Control MOSFET Unclamped Inductive Switching
Figure 27. Sync MOSFET Unclamped Inductive Switching
Copyright © 2012–2013, Texas Instruments Incorporated
9
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
APPLICATION INFORMATION
Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
Application (see
Figure 28
). As such, optimization of the power semiconductors in these applications, needs to
.
Figure 28.
The CSD86360Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with Q
GD
, Q
GS
, and Q
RR
. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see
Figure 29
). A key
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
Figure 29.
10
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
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EPTEMBER 201
2
–
R
EVISED MAY 2013
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar R
DS(ON)
and MOSFET
chipsets with lower R
DS(ON)
.
Figure 30
and
Figure 31
compare the efficiency and power loss performance of the
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86360Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(Z
DS(ON)
) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
R
DS(ON)
specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
100
98
96
94
92
90
88
86
84
82
80
78
14
12
10
8
PowerBlock HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/1.5m
Ω
Discrete HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/1.5m
Ω
Discrete HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/0.7m
Ω
PowerBlock HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/1.5m
Ω
Discrete HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/1.5m
Ω
Discrete HS/LS
R
DS
(
ON
)
= 3.7m
Ω
/0.7m
Ω
V
GS
= 5V
V
IN
= 12V
V
OUT
= 1.3V
L
OUT
= 1µH
f
SW
= 500kHz
T
A
= 25ºC
6
V
GS
= 5V
V
IN
= 12V
V
OUT
= 1.3V
L
OUT
= 1µH
f
SW
= 500kHz
T
A
= 25ºC
4
2
0
0
5
10 15 20 25 30 35 40 45 50 55 60
Output Current (A)
0
5
10 15 20 25 30 35 40 45 50 55 60
Output Current (A)
G001
G001
Figure 30. Efficiency Comparison for Discrete
Parts vs. Power Block
Figure 31. Power Loss Comparison for Discrete
Parts vs. Power Block
The chart below compares the traditional DC measured R
DS(ON)
of CSD86360Q5D versus its Z
DS(ON)
. This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured R
DS(ON)
values that are equivalent to CSD86360Q5D’s Z
DS(ON)
value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Comparison of R
DS(ON)
vs. Z
DS(ON)
HS
LS
Parameter
Typ
3.7
3.7
Max
–
Typ
0.7
1.5
Max
–
Effective AC On-Impedance Z
DS(ON)
(V
GS
= 5V)
DC Measured R
DS(ON)
(V
GS
= 4.5V)
4.5
1.9
Copyright © 2012–2013, Texas Instruments Incorporated
11
CSD86360Q5D
SLPS327A
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The CSD86360Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as R
DS(ON)
and Q
gd
are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves.
Figure 1
plots the power loss of the CSD86360Q5D as a function of load current. This curve
Figure 32
).The measured power loss is the CSD86360Q5D loss and consists of both input conversion loss and
(V
IN
x I
IN
) + (V
DD
x I
DD
) – (V
SW_AVG
x I
OUT
) = Power Loss
(1)
The power loss curve in
Figure 1
is measured at the maximum recommended junction temperatures of 125°C
Safe Operating Curves (SOA)
The SOA curves in the CSD86360Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss.
Figure 3
to
Figure 5
outline the
temperature and airflow conditions required for a given load current. The area
under the
curve dictates
the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x
3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD86360Q5D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Figure 32.
Typical Application
12
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
•
•
•
•
•
Output Current = 25A
Input Voltage = 7V
Output Voltage = 1V
Switching Frequency = 800kHz
Inductor = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Final calculated Power Loss = 3.5W x 1.03 x 0.90 x 1.15 x 1.03
≈
3.84W
Calculating SOA Adjustments
•
•
•
•
•
Final calculated SOA adjustment = 1.3 + (-2.5) + 6.0 + 1.3
≈
6.1ºC
In the design example above, the estimated power loss of the CSD86360Q5D would increase to 3.84W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 6.1ºC.
Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start
by drawing a horizontal line from the application current to the SOA curve.
2. Draw
a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust
the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 6.1ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 33.
Power Block SOA
Copyright © 2012–2013, Texas Instruments Incorporated
13
CSD86360Q5D
SLPS327A
–
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EPTEMBER 201
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RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
•
The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see
Figure 34
).
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
•
•
The Driver IC should be placed relatively close to the Power Block Gate pins. T
G
and B
G
should connect to
the outputs of the Driver IC. The T
GR
pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended Boost Resistor value will range between 1.0 Ohms to 4.7 Ohms
depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC
snubber values can range from 0.5 Ohms to 2.2 Ohms for the R and 330pF to 2200pF for the C. Please refer
(1)
(1) Keong
W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
14
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in
Figure 34
uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Input Capacitors
Input Capacitors
T
GR
T
G
V
IN
P
GND
Output Capacitors
Driver IC
Power Block
B
G
V
SW
V
SW
V
SW
RC Snubber
Power Block
Location on
T
o
p
Layer
Bottom Layer
Figure 34.
Recommended PCB Layout (Top Down View)
Top Layer
Output Inductor
Copyright © 2012–2013, Texas Instruments Incorporated
15
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
MECHANICAL DATA
Q5D Package Dimensions
E2
d2
K
L
E1
c1
d1
L
q
b
9
E
D1
D2
d
e
d3
f
Top View
Side View
Bottom View
Pinout
Position
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Designation
V
IN
Exposed Tie Bar May Vary
q
V
IN
T
G
T
GR
a
B
G
V
SW
V
SW
V
SW
P
GND
c
E1
Front View
M0187-01
MILLIMETERS
MIN
INCHES
DIM
MAX
MIN
MAX
0.059
0.018
0.010
0.010
0.068
0.015
0.012
0.015
0.201
0.172
0.201
0.240
0.126
a
b
1.40
1.5
0.055
0.014
0.006
0.006
0.064
0.011
0.008
0.012
0.193
0.168
0.193
0.232
0.122
0.360
0.460
0.250
0.250
1.730
0.380
0.300
0.391
5.100
4.369
5.100
6.100
3.206
c
0.150
c1
d
0.150
1.630
d1
d2
d3
D1
D2
E
0.280
0.200
0.291
4.900
4.269
4.900
E1
E2
e
5.900
3.106
1.27 TYP
0.396
0.050
0.032
f
0.496
0.710
–
0.016
0.020
–
0.020
0.028
–
L
0.510
θ
0.00
K
0.812
16
Copyright © 2012–2013, Texas Instruments Incorporated
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
2
–
R
EVISED MAY 2013
Land Pattern Recommendation
3.480 (0.137)
0.345 (0.014)
0.530 (0.021)
0.415 (0.016)
0.650 (0.026)
0.650 (0.026)
4.460
(0.176)
0.620
(0.024)
0.620 (0.024)
4.460
(0.176)
1.270
(0.050)
1.920
(0.076)
0.850 (0.033)
0.400 (0.016)
6.240 (0.246)
0.850 (0.033)
M0188-01
NOTE: Dimensions
are in mm (inches).
Text For Spacing
Stencil Recommendation
0.250 (0.010)
0.610 (0.024)
0.410 (0.016)
0.300 (0.012)
0.341 (0.013)
Stencil Opening
0.300 (0.012)
0.300 (0.012)
1.710
(0.067)
1.680
(0.066)
0.950 (0.037)
1.290 (0.051)
PCB Pattern
M0208-01
NOTE: Dimensions
are in mm (inches).
Text
For
Spacing
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
Copyright © 2012–2013, Texas Instruments Incorporated
17
CSD86360Q5D
SLPS327A
–
S
EPTEMBER 201
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–
R
EVISED MAY 2013
Q5D Tape and Reel Information
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
K0
+0.10
–0.00
0.30 0.05
2.00 0.05
Ø 1.50
1.75 0.10
5.50 0.05
12.00 0.30
B0
R 0.20 MAX
A0
8.00 0.10
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 5.30
0.10
B0 = 6.50
0.10
K0 = 1.90
0.10
M0191-01
NOTES: 1.
10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
spacer
REVISION HISTORY
Changes from Original (September 2012) to Revision A
Page
•
18
Copyright © 2012–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
13-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD86360Q5D
ACTIVE
LSON-CLIP
DQY
8
2500 Pb-Free
(RoHS CU
NIPDAU | CU SN
Exempt)
Level-1-260C-UNLIM
-55 to 150
86360D
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
23-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CSD86360Q5D
LSON-
CLIP
DQY
8
2500
330.0
15.4
5.3
6.3
1.2
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
23-Oct-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
LSON-CLIP DQY
SPQ
Length (mm)
Width (mm)
Height (mm)
335.0 335.0
32.0
CSD86360Q5D
8
2500
Pack Materials-Page 2
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