Texas-Instruments-CSD87350Q5D
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ZHCS110E
–
M
ARCH 201
1
–
R
EVISED FEBRUARY 2017
CSD87350Q5D
同步降压
NexFET™
电源块
1
特性
3
说明
1
•
•
•
•
•
•
•
•
•
•
•
半桥电源块
CSD87350Q5D NexFET™
电源块是面向同步降压 应
用 的优化设计方案，能够以
5mm × 6mm
的小巧外形
提供高电流、高效率以及高频率性能。该产品针对
5V
栅极驱动 应用进行了优化，可提供一套灵活的解决方
案，在与来自外部控制器或驱动器的任一
5V
栅极驱动
配套使用时，均可提供高密度电源。
25A
电流下系统效率达
90%
工作电流高达
40A
高频工作（高达
1.5MHz
）
高密度
SON 5mm × 6mm
封装
针对
5V
栅极驱动进行了优化
开关损耗较低
俯视图
超低电感封装
V
IN
V
IN
T
G
V
SW
V
SW
V
SW
1
2
3
4
8
7
6
5
符合
RoHS
标准
无卤素
P
GND
(Pin 9)
无铅引脚镀层
T
GR
B
G
2
应用范围
P0116-01
•
同步降压转换器
数量
–
–
高频 应用
器件
包装介质
封装
运输
高电流、低占空比 应用
小外形尺寸无引线
(SON)
5mm × 6mm
塑料封装
•
•
•
多相位同步降压转换器
负载点直流
–
直流转换器
IMVP
、
VRM
和
VRD
应用
CSD87350Q5D
13
英寸卷带
2500
卷带封装
(1)
要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型电源块效率与功率损耗
典型电路
96
94
92
90
88
86
84
82
80
78
76
74
11
10
9
ë
Lb
.hhÇ
5wëI
[[
ë
55
ë55
Db5
ë
Lb
Ç
D
/ontrol
C9Ç
8
V
GS
= 5 V
V
IN
= 12 V
V
OUT
= 1.3 V
L
OUT
= 0.3
m
H
f
SW
= 500 kHz
T
A
= 25
è
C
ë
{í
Ç
Dw
7
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hÜÇ
9b!.[9
tía
9b!.[9
tía
6
{ync
C9Ç
.
D
5wë[
5
t
Db5
4
/{5873ꢀ0ꢁꢀ5
5river L/
3
2
1
0
0
5
10
15
20
25
30
35
40
Output Current (A)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ZHCS110E
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ARCH 201
1
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EVISED FEBRUARY 2017
目录
1
2
3
4
5
7
8
9
6
4
修订历史记录
Changes from Revision D (September 2014) to Revision E
Page
•
•
Changes from Revision C (October 2011) to Revision D
Page
•
Changes from Revision B (September 2011) to Revision C
Page
•
Changes from Revision A (August 2011) to Revision B
Page
•
•
•
•
Changes from Original (March 2011) to Revision A
Page
•
Changed Power Dissipation, P
D
in the Absolute Maximum Ratings table From; 13 W to 12 W……………………………………..
3
2
版权
© 2011–2017, Texas Instruments Incorporated
ZHCS110E
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ARCH 201
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EVISED FEBRUARY 2017
5 Specifications
5.1 Absolute
Maximum Ratings
T
A
= 25°C (unless otherwise noted)
(1)
MIN
–0.8
–8
MAX
30
UNIT
V
V
IN
to P
GND
T
G
to T
GR
Voltage
10
V
B
G
to P
GND
–8
10
V
I
DM
P
D
Pulsed current rating
(2)
Power dissipation
120
12
A
W
Sync FET, I
D
= 105 A, L = 0.1 mH
Control FET, I
D
= 60 A, L = 0.1 mH
551
180
150
150
E
AS
Avalanche energy
mJ
T
J
Operating junction temperature
Storage temperature
–55
–55
°C
°C
T
stg
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse
duration
≤
50 µs. Duty cycle
≤
0.01%.
5.2 Recommended
Operating Conditions
T
A
= 25° (unless otherwise noted)
MIN
MAX UNIT
V
GS
V
IN
Gate drive voltage
4.5
8
27
V
V
Input supply voltage
ƒ
SW
Switching frequency C
BST
= 0.1
μ
F (min)
Operating current
200
1500
40
kHz
A
T
J
Operating temperature
125
°C
5.3 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
102 °C/W
50 °C/W
20 °C/W
Junction-to-ambient thermal resistance (min Cu)
(1
)
(
2)
Junction-to-ambient thermal resistance (max Cu)
(1
)
(
2)
Junction-to-case thermal resistance (top of package)
(2)
Junction-to-case thermal resistance (P
GND
pin)
(2)
R
θ
JA
R
θ
JC
2
°C/W
(1) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
) Cu.
(2)
θ
JC
is determined with the device mounted on a 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
R
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R
θ
JC
is specified by design while R
θ
JA
is determined by the user’s board
design.
5.4 Power
Block Performance
T
A
= 25° (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
W
V
IN
= 12 V V
GS
= 5 V, V
OUT
= 1.3 V,
I
OUT
= 25 A, ƒ
SW
= 500 kHz,
L
OUT
= 0.3 µH, T
J
= 25°C
P
LOSS
I
QVIN
Power loss
(1)
3
V
IN
quiescent current
T
G
to T
GR
= 0 V ,B
G
to P
GND
= 0 V
10
µA
(1) Measurement
made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V
IN
to P
GND
pins and
using a high-current 5-V driver IC.
Copyright © 2011–2017, Texas Instruments Incorporated
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EVISED FEBRUARY 2017
5.5 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
Q1 CONTROL FET
Q2 SYNC FET
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX MIN
TYP MAX
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
DS
= 250
μ
A
V
GS
= 0 V, V
DS
= 20 V
V
DS
= 0 V, V
GS
= +10 / –8
V
DS
= V
GS
, I
DS
= 250
μ
A
30
30
V
μ
A
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
1
1
100
1.4
I
GSS
100
V
GS(th)
1
2.1 0.75
V
IN
= 12 V, V
GS
= 5 V,
V
OUT
= 1.3 V, I
OUT
= 20 A,
ƒ
SW
= 500 kHz,
(1)
Z
DS(on)
Effective AC on-impedance
Transconductance
5
1.2
m
Ω
L
OUT
= 0.3 µH
g
ƒs
V
DS
= 15 V, I
DS
= 20 A
97
157
S
DYNAMIC CHARACTERISTICS
C
ISS
C
OSS
C
RSS
R
G
Input capacitance
1360
565
19
1770
2950 3835
1300 1690
pF
pF
pF
Ω
V
GS
= 0 V, V
DS
= 15 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
735
25
50
0.8
20
3.6
4.3
2.3
28
8
65
2
1.3
8.4
1.6
2.6
1.6
9.7
7
3
Q
g
10.9
26
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
OSS
t
d(on)
t
r
V
DS
= 15 V,
I
DS
= 20 A
V
DS
= 17 V, V
GS
= 0 V
Turnon delay time
Rise time
17
10
33
4.7
V
DS
= 15 V, V
GS
= 4.5 V,
I
DS
= 20 A, R
G
= 2
Ω
t
d(off)
t
ƒ
Turnoff delay time
Fall time
13
2.3
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
I
DS
= 20 A, V
GS
= 0 V
0.85
12.5
22
1
0.77
32
1
V
Reverse recovery charge
Reverse recovery time
nC
ns
V
dd
= 17 V, I
F
= 20 A,
di/dt = 300 A/
μ
s
28
HD
LD
HD
LD
Max R
θ
JA
= 50°C/W
when mounted on 1 in
2
(6.45 cm
2
) of
2-oz (0.071-mm) thick
Cu.
Max R
θ
JA
= 102°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
LG HS
LG HS
HG
LS
HG
LS
M0189-01
M0190-01
4
Copyright © 2011–2017, Texas Instruments Incorporated
ZHCS110E
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M
ARCH 201
1
–
R
EVISED FEBRUARY 2017
5.6 Typical
Power Block Device Characteristics
T
J
= 125°C, unless stated otherwise. The typical power block system characteristic curves
Figure 3
,
Figure 4
, and
Figure 5
are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper
10
9
8
7
6
5
4
3
2
1
0
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0
5
10
15
20
25
30
35
40
-50 -30 -10 10
30
50
70
90 110
130 150
Output Current (A)
T
C
– Junction Temperature (
è
C)
D002
D003
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
Figure 1. Power Loss vs Output Current
Figure 2. Normalized Power Loss vs Temperature
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
400 LFM
200 LFM
100 LFM
Nat. conv.
400 LFM
200 LFM
100 LFM
Nat. conv.
10
5
0
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (
è
C)
Ambient Temperature (
è
C)
D004
D005
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
Figure 3. Safe Operating Area (SOA) – PCB Vertical Mount
Figure 4. Safe Operating Area (SOA) – PCB Horizontal
Mount
45
40
35
30
25
20
15
10
5
1.5
1.4
1.3
1.2
1.1
1
14.7
11.8
8.8
5.9
2.9
0.0
0
0.9
-2.9
0
20
40
60
80
100
120
140
200
400
600
800
1000
1200
1400
1600
Board Temperature (
è
C)
Switching Frequency (kHz)
D006
D007
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
V
IN
= 12 V
L
OUT
= 0.3 µH
V
GS
= 5 V
V
OUT
= 1.3 V
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
I
OUT
= 40 A
Figure 5. Typical Safe Operating Area (SOA)
Figure 6. Normalized Power Loss vs Switching Frequency
Copyright © 2011–2017, Texas Instruments Incorporated
5
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Typical Power Block Device Characteristics (continued)
T
J
= 125°C, unless stated otherwise. The typical power block system characteristic curves
Figure 3
,
Figure 4
, and
Figure 5
are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper
1.25
7.3
5.9
4.4
2.9
1.5
0.0
-1.5
1.4
1.35
1.3
-11.7
-10.3
-8.8
-7.3
-5.9
-4.4
-2.9
-1.5
0.0
1.2
1.25
1.2
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
1.5
0.95
2.9
0
2
4
6
8
10 12 14 16 18 20 22 24
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
Input Voltage (V)
Output Voltage (V)
D008
D009
V
IN
= 12 V
V
OUT
= 1.3 V
I
OUT
= 40 A
L
OUT
= 0.3 µH
V
IN
= 12 V
V
GS
= 5 V
I
OUT
= 40 A
ƒ
SW
= 500 kHz
ƒ
SW
= 500 kHz
L
OUT
= 0.3 µH
Figure 7. Normalized Power Loss vs Input Voltage
Figure 8. Normalized Power Loss vs Output Voltage
1.125
3.7
1.1
1.075
1.05
1.025
1
2.9
2.2
1.5
0.7
0.0
-0.7
-1.5
-2.2
0.975
0.95
0.925
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1
Output Inductance (
m
H)
D010
V
IN
= 12 V
V
GS
= 5 V
V
OUT
= 1.3 V
ƒ
SW
= 500 kHz
I
OUT
= 40 A
Figure 9. Normalized Power Loss vs Output Inductance
6
Copyright © 2011–2017, Texas Instruments Incorporated
ZHCS110E
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ARCH 201
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EVISED FEBRUARY 2017
5.7 Typical
Power Block MOSFET Characteristics
T
A
= 25°C, unless stated otherwise.
80
70
60
50
40
30
80
70
60
50
40
30
20
10
0
20
V
GS
= 8.0 V
V
GS
= 4.5 V
V
GS
= 4.0 V
V
GS
= 8.0 V
V
GS
= 4.5 V
V
GS
= 4.0 V
10
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
V
DS
– Drain-to-Source Voltage (V)
0
0.02 0.04 0.06 0.08
0.1 0.12
0.14 0.16 0.18
0.2
V
DS
– Drain-to-Source Voltage (V)
D011
D012
Figure 10. Control MOSFET Saturation
Figure 11. Sync MOSFET Saturation
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
T
C
= 125
è
C
T
C
= 25
è
C
T
C
= -55
è
C
T
C
= 125
è
C
T
C
= 25
è
C
T
C
= -55
è
C
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D013
D014
V
DS
= 5 V
V
DS
= 5 V
Figure 12. Control MOSFET Transfer
Figure 13. Sync MOSFET Transfer
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
0
0
0
2
4
6
8
10
12
14
16
5
10
15
20
25
30
35
Qg – Gate Charge (nC)
Qg – Gate Charge (nC)
D015
D016
I
D
= 20 A
V
DD
= 15 V
I
D
= 20 A
V
DD
= 15 V
Figure 14. Control MOSFET Gate Charge
Figure 15. Sync MOSFET Gate Charge
Copyright © 2011–2017, Texas Instruments Incorporated
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Typical Power Block MOSFET Characteristics (continued)
T
A
= 25°C, unless stated otherwise.
10
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
D017
D018
ƒ = 1 MHz
V
GS
= 0
ƒ = 1 MHz
V
GS
= 0
Figure 16. Control MOSFET Capacitance
Figure 17. Sync MOSFET Capacitance
1.8
1.6
1.4
1.2
1
1.4
1.2
1
0.8
0.6
0.4
0.2
0.8
0.6
-75 -50 -25
0
25
50
75 100
125 150 175
-75 -50 -25
0
25
50
75 100
125 150 175
T
C
– Case Temperature (
°
C
)
T
C
– Case Temperature (
°
C
)
D019
D020
I
D
= 250 µA
I
D
= 250 µA
Figure 18. Control MOSFET V
GS(th)
Figure 19. Sync MOSFET V
GS(th)
16
14
12
10
8
8
7
6
5
4
3
2
1
0
T
C
= 25
°
C
T
C
= 125
°
C
T
C
= 25
°
C
T
C
= 125
°
C
6
4
2
0
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D021
D022
Figure 20. Control MOSFET R
DS(on)
vs V
GS
Figure 21. Sync MOSFET R
DS(on)
vs V
GS
8
Copyright © 2011–2017, Texas Instruments Incorporated
ZHCS110E
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M
ARCH 201
1
–
R
EVISED FEBRUARY 2017
Typical Power Block MOSFET Characteristics (continued)
T
A
= 25°C, unless stated otherwise.
1.5
1.4
1.3
1.2
1.1
1
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.9
0.8
0.7
-75 -50 -25
0
25
50
75 100
125 150 175
-75 -50 -25
0
25
50
75 100
125 150 175
T
C
– Case Temperature (
°
C
)
T
C
– Case Temperature (
°
C
)
D023
D0
0
2
1
4
I
D
= 20 A
V
GS
= 8 V
I
D
= 20 A
V
GS
= 8 V
Figure 22. Control MOSFET Normalized R
DS(on)
Figure 23. Sync MOSFET Normalized R
DS(on)
100
100
10
1
10
1
0.1
0.01
0.1
0.01
0.001
0.0001
0.001
T
C
= 25
°
C
T
C
= 125
°
C
T
C
= 25
°
C
T
C
= 125
°
C
0.0001
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
V
SD
– Source-to-Drain Voltage (V)
V
SD
– Source-to-Drain Voltage (V)
D025
D026
Figure 24. Control MOSFET Body Diode
Figure 25. Sync MOSFET Body Diode
100
10
1
1000
100
10
T
C
= 25
°
C
T
C
= 125
°
C
T
C
= 25
°
C
T
C
= 125
°
C
1
0.01
0.1
1
10
0.01
0.1
1
10
t
AV
– Time in Avalanche (ms)
t
AV
– Time in Avalanche (ms)
D027
D028
Figure 26. Control MOSFET Unclamped Inductive Switching
Figure 27. Sync MOSFET Unclamped Inductive Switching
Copyright © 2011–2017, Texas Instruments Incorporated
9
ZHCS110E
–
M
ARCH 201
1
–
R
EVISED FEBRUARY 2017
6 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application
Information
The CSD87350Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-
centric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.1 Equivalent
System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see
Figure 28
). As such, optimization of the power semiconductors in these applications, needs to go beyond
.
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Figure 28.
Equivalent System Schematic
The CSD87350Q5D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with Q
GD
, Q
GS
, and Q
RR
. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see
Figure 29
). A key
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in
Power Loss Calculation With Common Source
10
Copyright © 2011–2017, Texas Instruments Incorporated
ZHCS110E
–
M
ARCH 201
1
–
R
EVISED FEBRUARY 2017
Application Information (continued)
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