Texas-Instruments-CSD87588N
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CSD87588N
SLPS384D
–
M
ARCH 201
3
–
R
EVISED APRIL 2015
CSD87588N Synchronous Buck NexFET™ Power Block II
1 Features
3 Description
The CSD87588N NexFET™ power block II is a
1
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•
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Half-Bridge Power Block
90% System Efficiency at 20 A
Up to 25 A Operation
highly-optimized design for synchronous buck
applications offering high current and high efficiency
capability in a small 5 mm × 2.5 mm outline.
Optimized for 5 V gate drive applications, this product
offers an efficient and flexible solution capable of
providing a high density power supply when paired
High Density – 5 mm x 2.5 mm LGA Footprint
Double Side Cooling Capability
Ultra-Low Profile – 0.48 mm Max
Optimized for 5 V Gate Drive
Low Switching Losses
with any
5
V
gate driver from an external
controller/driver.
Low Inductance Package
RoHS Compliant
Device
Media
Qty
2500
250
Package
Ship
CSD87588N
CSD87588NT
13-Inch Reel
7-Inch Reel
Halogen Free
Tape and
Reel
5 x 2.5 LGA
Pb Free
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Synchronous Buck Converters
High-Current, Low Duty Cycle Applications
TEXT ADDED FOR SPACING
–
•
•
Multiphase Synchronous Buck Converters
POL DC-DC Converters
Typical Circuit
Typical Power Block Efficiency and Power Loss
100
90
80
70
60
50
40
30
7
6
5
4
3
2
1
0
V
IN
BOOT
V
DD
VDD
GND
V
IN
TG
DRVH
LL
V
GS
= 5V
V
IN
= 12V
V
OUT
= 1.3V
L
OUT
= 0.29µH
f
SW
= 500kHz
T
A
= 25ºC
V
SW
V
OUT
ENABLE
PWM
ENABLE
PWM
BG
DRVL
P
GND
CSD87588N
Driver IC
0
5
10
15
20
25
Output Current (A)
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87588N
SLPS384D
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M
ARCH 201
3
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R
EVISED APRIL 2015
Table of Contents
1
2
3
4
5
7
8
9
Mechanical, Packaging, and Orderable
6
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2014) to Revision D
Page
•
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Changes from Revision B (January 2014) to Revision C
Page
•
Changes from Revision A (May 2013) to Revision B
Page
•
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Changes from Original (March 2013) to Revision A
Page
•
2
Copyright © 2013–2015, Texas Instruments Incorporated
CSD87588N
SLPS384D
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M
ARCH 201
3
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R
EVISED APRIL 2015
5 Specifications
5.1 Absolute
Maximum Ratings
(1)
T
A
= 25°C (unless otherwise noted)
MIN
MAX
30
UNIT
V
IN
to P
GND
–0.8
V
SW
to P
GND
V
SW
to P
GND
(10 ns)
T
G
to V
SW
30
Voltage
32
V
–20
–20
20
B
G
to P
GND
20
I
DM
P
D
Pulsed Current Rating
(2)
Power Dissipation
(3)
50
A
6
W
Sync FET, I
D
= 45, L = 0.1 mH
Control FET, I
D
= 26, L = 0.1 mH
101
34
E
AS
Avalanche Energy
mJ
T
J
Operating Junction
–55
–55
150
150
°C
°C
T
stg
Storage Temperature Range
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse
Duration
≤
50 µs, duty cycle
≤
0.01
(3) Device
mounted on FR4 material with 1 inch
2
(6.45 cm
2
) Cu
5.2 Recommended
Operating Conditions
T
A
= 25°C (unless otherwise noted)
MIN
MAX
16
UNIT
V
V
GS
V
IN
Gate Drive Voltage
Input Supply Voltage
Switching Frequency
4.5
24
V
ƒ
SW
C
BST
= 0.1
μ
F (min)
No Airflow
200
1500
25
kHz
A
Operating Current
With Airflow (200 LFM)
With Airflow + Heat Sink
30
A
35
A
T
J
Operating Temperature
125
°C
5.3 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
(1)
Junction-to-ambient thermal resistance (Min Cu)
170
R
θ
JA
(2) (1)
Junction-to-ambient thermal resistance (Max Cu)
70
°C/W
3.7
(1)
Junction-to-case thermal resistance (Top of package)
R
θ
JC
(1)
(1)
Junction-to-case thermal resistance (P
GND
Pin)
1.25
R
θ
JC
is determined with the device mounted on a 1 inch
2
(6.45 cm
2
), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. R
θ
JC
is specified by design while R
θ
JA
is determined by the user’s board
design.
(2) Device
mounted on FR4 material with 1 inch
2
(6.45 cm
2
) Cu.
Copyright © 2013–2015, Texas Instruments Incorporated
3
CSD87588N
SLPS384D
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5.4 Power
Block Performance
T
A
= 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
V
IN
= 12 V, V
GS
= 5 V
V
OUT
= 1.3 V, I
OUT
= 15 A
ƒ
SW
= 500 kHz
P
LOSS
Power Loss
(1)
2.1
W
L
OUT
= 0.29 µH, T
J
= 25ºC
T
G
to T
GR
= 0 V
B
G
to P
GND
= 0 V
I
QVIN
V
IN
Quiescent Current
10
µA
(1) Measurement
made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V
IN
to P
GND
pins and
using a high current 5 V driver IC.
5.5 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
Q1 FET
TYP
Q2 FET
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-Source Voltage
V
GS
= 0 V, I
DS
= 250
μ
A
30
30
V
μ
A
nA
V
Drain-to-Source Leakage Current
V
GS
= 0 V, V
DS
= 24 V
1
100
1.9
1
100
1.9
4.2
3.5
I
GSS
Gate-to-Source Leakage Current
V
DS
= 0 V, V
GS
= 20
V
GS(th)
Gate-to-Source Threshold Voltage
V
DS
= V
GS
, I
DS
= 250
μ
A
1.1
1.1
V
GS
= 4.5 V, I
DS
= 15 A
Drain-to-Source On Resistance
10.4
8
12.5
9.6
3.5
2.9
93
R
DS(on)
m
Ω
V
GS
= 10 V, I
DS
= 15 A
g
ƒs
Transconductance
V
DS
= 10 V, I
DS
= 15 A
43
S
DYNAMIC CHARACTERISTICS
(1)
C
ISS
C
OSS
C
RSS
R
G
Input Capacitance
Output Capacitance
566
341
10.3
1.2
3.2
0.7
1.4
0.8
7
736
444
13.4
2.4
2310
682
62
3000
887
80.4
2.2
pF
pF
pF
Ω
V
GS
= 0 V, V
DS
= 15 V,
ƒ = 1 MHz
(1)
(1)
Reverse Transfer Capacitance
(1)
Series Gate Resistance
1.1
(1)
Q
g
Gate Charge Total (4.5 V)
4.1
13.7
4.3
17.9
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
OSS
t
d(on)
t
r
Gate Charge – Gate-to-Drain
Gate Charge – Gate-to-Source
Gate Charge at V
th
Output Charge
V
DS
= 15 V,
I
DS
= 15 A
4.3
2.8
V
DD
= 12 V, V
GS
= 0 V
18.6
12.1
36.7
20.1
6.3
Turn On Delay Time
Rise Time
7.3
31.6
10.2
5.0
V
DS
= 15 V, V
GS
= 4.5 V,
I
DS
= 15 A, R
G
= 2
Ω
t
d(off)
t
ƒ
Turn Off Delay Time
Fall Time
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode Forward Voltage
I
DS
= 15 A, V
GS
= 0 V
0.85
12.5
16
0.78
26.7
23
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
V
dd
= 15 V, I
F
= 15 A,
di/dt = 300 A/
μ
s
(1) Specified
by design
4
Copyright © 2013–2015, Texas Instruments Incorporated
CSD87588N
SLPS384D
–
M
ARCH 201
3
–
R
EVISED APRIL 2015
Max R
θ
JA
= 70°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2 oz. (0.071 mm thick)
Cu.
Max R
θ
JA
= 170°C/W
when mounted on
minimum pad area of
2 oz. (0.071 mm thick)
Cu.
5.6 Typical
Power Block Device Characteristics
T
J
= 125°C, unless stated otherwise.The Typical Power Block System Characteristic curves
Figure 3
and
Figure 4
are based
on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper
8
7
6
5
4
3
2
1
0
1.1
1
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.29µH
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.29µH
0.9
0.8
0.7
0.6
0.5
1
3
5
7
9
11 13 15 17 19 21 23 25
Output Current (A)
−50
−25
0
25
50
75
100
125
150
Junction Temperature (ºC)
G001
G001
Figure 1. Power Loss vs Output Current
Figure 2. Normalized Power Loss vs Temperature
30
25
20
15
10
5
30
25
20
15
10
5
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
L
OUT
= 0.29µH
400LFM
200LFM
100LFM
Nat Conv
0
0
0
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
Ambient Temperature (ºC)
Board Temperature (ºC)
G001
G001
Figure 3. Safe Operating Area – PCB Horizontal Mount
Figure 4. Typical Safe Operating Area
Copyright © 2013–2015, Texas Instruments Incorporated
5
CSD87588N
SLPS384D
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ARCH 201
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Typical Power Block Device Characteristics (continued)
T
J
= 125°C, unless stated otherwise.The Typical Power Block System Characteristic curves
Figure 3
and
Figure 4
are based
on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper
1.35
3.0
2.6
2.2
1.7
1.3
0.9
0.4
0.0
−0.4
−0.9
1.4
1.35
1.3
3.5
3.0
2.6
2.2
1.7
1.3
0.9
0.4
0.0
−0.4
V
GS
= 5V
1.3
V
OUT
= 1.3V
L
OUT
= 0.29µH
f
SW
= 500kHz
I
OUT
= 25A
1.25
1.2
1.25
1.2
1.15
1.1
1.15
1.1
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
L
OUT
= 0.29µH
I
OUT
= 25A
1.05
1
1.05
1
0.95
0.9
0.95
0
200 400 600 800
1000 1200 1400 1600 1800
Switching Frequency (kHz)
0
2
4
6
8
10 12 14 16 18 20 22 24
Input Voltage (V)
G001
G001
Figure 5. Normalized Power Loss vs Switching Frequency
Figure 6. Normalized Power Loss vs Input Voltage
2
1.8
1.6
1.4
1.2
1
8.6
6.9
5.1
3.4
1.7
0
1.12
1.1
1.04
V
IN
= 12V
V
GS
= 5V
V
OUT
= 1.3V
f
SW
= 500kHz
0.87
1.08
1.06
1.04
1.02
1
0.69
I
OUT
= 25A
0.52
0.35
0.17
0
V
IN
= 12V
V
GS
= 5V
f
SW
= 500kHz
L
OUT
= 0.29µH
I
OUT
= 25A
0.98
0.96
0.94
−0.17
−0.35
−0.52
0.8
−1.7
0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
Output Voltage (V)
0
100 200 300 400 500 600 700 800 900
1000 1100
Output Inductance (nH)
G001
G001
Figure 7. Normalized Power Loss vs Output Voltage
Figure 8. Normalized Power Loss vs Output Inductance
6
Copyright © 2013–2015, Texas Instruments Incorporated
CSD87588N
SLPS384D
–
M
ARCH 201
3
–
R
EVISED APRIL 2015
5.7 Typical
Power Block MOSFET Characteristics
T
A
= 25°C, unless stated otherwise.
50
45
40
35
30
25
20
15
200
180
160
140
120
100
80
60
V
GS
= 8.0V
V
GS
= 4.5V
V
GS
= 4.0V
V
GS
= 8.0V
V
GS
= 4.5V
V
GS
= 4.0V
10
5
40
20
0
0
0
0
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
1.2
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 9.
Control MOSFET Saturation
Figure 10. Sync MOSFET Saturation
100
10
1000
100
V
DS
= 5V
V
DS
= 5V
1
10
0.1
1
0.01
0.1
0.001
0.0001
0.00001
0.01
0.001
0.0001
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
T
C
= 125°C
T
C
= 25°C
T
C
= −55°C
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
G001
G001
Figure 11. Control MOSFET Transfer
Figure 12. Sync MOSFET Transfer
10
9
8
7
6
5
4
3
2
1
0
10
I
D
= 15A
V
DS
= 15V
I
D
= 15A
V
DS
= 15V
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
Q
g
– Gate Charge
(nC)
Q
g
– Gate Charge
(nC)
G001
G001
Figure 13. Control MOSFET Gate Charge
Figure 14. Sync MOSFET Gate Charge
Copyright © 2013–2015, Texas Instruments Incorporated
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Typical Power Block MOSFET Characteristics (continued)
T
A
= 25°C, unless stated otherwise.
10000
1000
100
10
10000
1000
100
10
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
1
1
0
5
10
15
20
25
30
0
5
10
15
20
25
30
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
G001
G001
Figure 15. Control MOSFET Capacitance
Figure 16. Sync MOSFET Capacitance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
I
D
= 250µA
I
D
= 250µA
0.9
0.8
0.7
0.6
0.9
0.8
−75
−25
25
75
125
175
−75
−25
25
75
125
175
T
C
– Case Temperature (ºC)
T
C
– Case Temperature (ºC)
G001
G001
Figure 17. Control MOSFET V
GS(th)
Figure 18. Sync MOSFET V
GS(th)
30
10
I
D
= 15A
I
D
= 15A
27
24
21
18
15
12
9
9
8
7
6
5
4
3
2
1
0
6
T
C
= 25°C
T
C
= 125ºC
T
C
= 25°C
T
C
= 125ºC
3
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to- Source Voltage (V)
V
GS
– Gate-to- Source Voltage (V)
G001
G001
Figure 19. Control MOSFET R
DS(on)
vs V
GS
Figure 20. Sync MOSFET R
DS(on)
vs V
GS
8
Copyright © 2013–2015, Texas Instruments Incorporated
CSD87588N
SLPS384D
–
M
ARCH 201
3
–
R
EVISED APRIL 2015
Typical Power Block MOSFET Characteristics (continued)
T
A
= 25°C, unless stated otherwise.
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
I
D
= 15A
V
GS
= 8V
I
D
= 15A
V
GS
= 8V
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−75
−25
25
75
125
175
−75
−25
25
75
125
175
T
C
– Case Temperature (ºC)
T
C
– Case Temperature (ºC)
G001
G001
Figure 21. Control MOSFET Normalized R
DS(on)
Figure 22. Sync MOSFET Normalized R
DS(on)
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
T
C
= 25°C
T
C
= 125°C
T
C
= 25°C
T
C
= 125°C
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8 1
V
SD
− Source-to-Drain Voltage (V)
V
SD
− Source-to-Drain Voltage (V)
G001
G001
Figure 23. Control MOSFET Body Diode
Figure 24. Sync MOSFET Body Diode
100
10
1
100
10
1
T
C
= 25°C
T
C
= 125°C
T
C
= 25°C
T
C
= 125°C
0.01
0.1
1
0.01
0.1
1
t
– Time in Avalanche (ms)
t
– Time in Avalanche (ms)
G001
G001
(
AV
)
(
AV
)
Figure 25. Control MOSFET Unclamped Inductive Switching
Figure 26. Sync MOSFET Unclamped Inductive Switching
Copyright © 2013–2015, Texas Instruments Incorporated
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CSD87588N
SLPS384D
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ARCH 201
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EVISED APRIL 2015
6 Application
and Implementation
6.1 Application
Information
The CSD87588N NexFET power block is an optimized design for synchronous buck applications using 5 V gate
drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest
system efficiency. As a result, a new rating method is needed which is tailored toward a more systems-centric
environment. System-level performance curves such as Power Loss, Safe Operating Area, and normalized
graphs allow engineers to predict the product performance in the actual application.
6.1.1 Power
Loss Curves
MOSFET-centric parameters such as R
DS(ON)
and Q
gd
are needed to estimate the loss generated by the devices.
To simplify the design process for engineers, TI has provided measured power loss performance curves.
Figure 1
plots the power loss of the CSD87588N as a function of load current. This curve is measured by
configuring
and running the CSD87588N as it would be in the final application (see
Figure 27
). The measured
power loss is the CSD87588N loss and consists of both input conversion loss and
gate drive loss.
Equation 1
is
used to generate the power loss curve.
(V
IN
× I
IN
) + (V
DD
× I
DD
) – (V
SW_AVG
× I
OUT
) = Power Loss
(1)
The power loss curve in
Figure 1
is measured at the maximum recommended junction temperatures of 125°C
6.1.2 Safe
Operating Curves (SOA)
The SOA curves in the CSD87588N data sheet provide guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss.
Figure 3
to
Figure 4
outline the
temperature and airflow conditions required for a given load current. The area
under the curve dictates
the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches
(W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness.
6.1.3 Normalized
Curves
The normalized curves in the CSD87588N data sheet provides guidance on the Power Loss and SOA
adjustments based on their application-specific needs. These curves show how the power loss and SOA
boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power
loss and the secondary y-axis is the change in system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Input Current (I
IN
)
V
IN
A
BOOT
DRVH
LL
V
DD
A
VDD
V
V
IN
Input Voltage (V
IN
)
Gate Drive
Voltage (V
DD
)
V
TG
ENABLE
PWM
Output Current (I
OUT
)
V
SW
A
V
OUT
PWM
BG
DRVL
P
GND
GND
Averaged Switch
V
Node Voltage
Averaging
Circuit
CSD873588N
Driver IC
(V
SW_AVG
)
Figure 27.
Typical Application
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Application Information (continued)
6.1.4 Calculating
Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see
Design Example
). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of
test conditions, the
following
procedure outlines the steps the user should take to predict product performance for any set of system
conditions.
6.1.4.1 Design
Example
Operating Conditions:
•
•
•
•
•
Output Current = 15 A
Input Voltage = 7 V
Output Voltage = 1 V
Switching Frequency = 800 kHz
Inductor = 0.2 µH
6.1.4.2 Calculating
Power Loss
•
•
•
•
•
•
Final calculated Power Loss = 2.75 W × 1.05 × 0.95 × 1.05 × 1.05
≈
3.02 W
6.1.4.3 Calculating
SOA Adjustments
•
•
•
•
•
Final calculated SOA adjustment = 0.3 + (–0.5) + 0.7 + 0.3
≈
0.8ºC
In the previous design example, the estimated power loss of the CSD87588N would increase to 3.02 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 0.8ºC.
Figure 28
graphically shows how the SOA curve would be adjusted accordingly.
1. Start
by drawing a horizontal line from the application current to the SOA curve.
2. Draw
a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust
the SOA board/ambient temperature by subtracting the temperature adjustment value.
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Application Information (continued)
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 0.8ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 28.
Power Block SOA
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7 Layout
7.1 Layout
Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The
following sections provide a brief description on how to address each parameter.
7.1.1 Electrical
Performance
The CSD87588N has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the
PCB layout design and placement of the input capacitors, inductor, and output capacitors.
•
The placement of the input capacitors relative to VIN and PGND pins of CSD87588N device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see
Figure 29
).
with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the
Power Stage C21, C5, C8, C19, and C18 should follow in order.
•
The switching node of the output inductor should be placed relatively close to the Power Block II CSD87588N
VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction
(1)
7.1.2 Thermal
Performance
The CSD87588N has the ability to utilize the PGND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that wicks down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in
Figure 29
uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
The number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
7.2 Layout
Example
Figure 29.
Recommended PCB Layout (Top Down View)
(1) Keong
W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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8 Device
and Documentation Support
8.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.2 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 CSD87588N
Package Dimensions
Pin Configuration
Position
Designation
Pin 1
TG
V
IN
Pin 2
Pin 3
P
GND
BG
Pin 4
Pin 5
V
SW
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9.2 Land
Pattern Recommendation
1.250 REF PKG
0.858
2
1
3
5
0.000
0.238
0.538
0.238
0.538
4
0.858
1.250 REF PKG
PACKAGE
OUTLINE
9.3 Stencil
Recommendation (100 µm)
Text For Spacing
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9.4 Stencil
Recommendation (125 µm)
Text
For
Spacing
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
9.5 Pin
Drawing
87588N
TI YMS
LLLL E
Text For Spacing
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9.6 CSD87588N
Embossed Carrier Tape Dimensions
(1) Pin
1 is oriented in the top-left quadrant of the tape enclosure (closest to the carrier tape sprocket holes).
spacer
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PACKAGE OPTION ADDENDUM
25-Feb-2015
PACKAGING INFORMATION
Orderable Device
CSD87588N
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PTAB
PTAB
MPA
5
5
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 150
87588N
87588N
CSD87588NT
ACTIVE
MPA
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
25-Feb-2015
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
24-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CSD87588N
PTAB
PTAB
MPA
MPA
5
5
2500
250
330.0
180.0
12.4
12.4
2.8
2.8
5.3
5.3
0.55
0.55
8.0
8.0
12.0
12.0
Q1
Q1
CSD87588NT
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
24-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD87588N
PTAB
PTAB
MPA
MPA
5
5
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
CSD87588NT
Pack Materials-Page 2
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