Texas-Instruments-JFE150DCKT
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JFE150
超低噪音、低栅极电流、音频、
N
通
道
JFET
设置
，
并为
50
μ
A
至
20mA
的电流提供出色的噪声性
能。当偏置电流
为
5mA
时
，
该器件会产
生
0.8nV/
√
Hz
的输入参考噪声
，
从而以极高的输入阻抗
(> 1T
Ω
)
提
供超低噪声性能。
JFE150
还具有连接到独立钳位节点
的集成二极管
，
无需添加高泄漏、非线性外部二极管即
可提供保护。
1
特性
• 超低噪声
：
– 电压噪声
：
•
1kHz
时
为
0.8nV/
√
Hz
，
I
DS
= 5mA
•
1kHz
时
为
0.9nV/
√
Hz
，
I
DS
= 2mA
– 电流噪声
：
1 kHz
时
为
1.8fA/
√
Hz
• 低栅极电流
：
10pA
（
最大值
）
• 低输入电容
：
V
DS
= 5V
时
为
24pF
• 高栅漏电压和栅源击穿电压
：
-40 V
• 高跨导
：
68mS
JFE150
可承受
40V
的高漏源电压
，
以及低至 –
40V
的栅源电压和栅漏电压。该器件额定工作温度范围为
–
40°C
至
+ 125°C
，
并采用
5
引脚
SOT-23
和
SC-70
封装。
器件信息
• 封装
：
小
型
SC70
和
SOT-23
（
预发布
）
SOT-23 (5) –
预发布
SC-70 (5)
封装尺寸
（
标称值
）
2.90mm × 1.60mm
2.00mm × 1.25mm
器件型号
JFE150
2
应用
(1)
如需了解所有可用封装
，
请参阅数据表末尾的封装选项附录。
器件概述
参数
值
V
GSS
V
DSS
C
ISS
T
J
-40 V
±40 V
24pF
栅源电压
漏源电压
输入电容
结温
3
说明
JFE150
是使用德州仪器
(TI)
的现代高性能模拟双极工
艺构建的
Burr-Brown
™
分立式
JFET
。
JFE150
具有以
前较旧的分立式
JFET
技术所不具备的性能。
JFE150
提供出色的噪声功率效率和灵活性
，
静态电流可由用户
–
40°C
至
+125°C
I
DSS
36 mA
漏源饱和电流
D
VCH
G
VCL
S
功能框图
超低输入电压噪声
本文档旨在为方便起见
，
提供有
关
TI
产品中文版本的信息
，
以确认产品的概要。有关适用的官方英文版本的最新信息
，
请访问
Table of Contents
4 Revision History
注
：
以前版本的页码可能与当前版本的页码不同
Changes from Revision * (June 2021) to Revision A (November 2021)
Page
•
Changed Figure 6-3,
Drain-to-Source Current vs Drain-to-Source Voltage,
to show correct V
GS
values……….
6
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2
5 Pin Configuration and Functions
VCH
VCL
G
1
2
3
5
D
4
S
Not to scale
图
5-1. DBV (5-Pin SOT-23, Preview) and DCK (5-Pin SC70) Packages, Top View
表
5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
D
NO.
5
Output
Input
Drain
G
3
Gate
S
4
Output
Power
Power
Source
VCH
VCL
1
Positive diode clamp voltage
Negative diode clamp voltage
2
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6 Specifications
6.1 Absolute Maximum Ratings
MIN
–
40
–
40
MAX
UNIT
V
DS
Drain-to-source voltage
40
0.9
40
V
V
V
V
GS
, V
GD
V
VCH
Gate-to-source, gate-to-drain voltage
Voltage between VCH to D, G, or S
Voltage between VCL to D, G, or S
V
VCL
–
40
DC
20
200
50
I
VCL
, I
VCH
Clamp diode current
mA
I
DS
Drain-to-source current
Gate-to-source, gate-to-drain current
Ambient temperature
mA
mA
°C
–
50
–
20
–
55
–
55
–
55
I
GS,
I
GD
T
A
20
150
150
175
T
J
Junction temperature
°C
T
stg
Storage temperature
°C
(1) Operation
outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Maximum
diode current pulse specified for 50 ms at 1% duty cycle.
6.2 ESD Ratings
VALUE
±2500
±500
UNIT
V
(ESD)
Electrostatic discharge
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.02
0
NOM
MAX
I
DSS
UNIT
I
DS
V
GS
T
A
Drain-to-source current
Gate-to-source voltage
Specified temperature
mA
V
–
1.2
125
°C
–
40
6.4 Thermal Information
JFE150
DCK (SC70)
5 PINS
197.1
UNIT
R
θ
JA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
θ
JC(top)
R
θ
JB
93.7
44.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.7
ψ
JT
44.6
ψ
JB
R
θ
JC(bot)
N/A
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report.
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6.5 Electrical Characteristics
at T
A
= 25°C, I
DS
= 2 mA, and V
DS
= 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
I
DS
= 100 µA
I
DS
= 2 mA
I
DS
= 5 mA
3
2
I
DS
= 100 µA , V
DS
= 5 V
I
DS
= 2 mA, V
DS
= 5 V
I
DS
= 5 mA, V
DS
= 5 V
1.6
0.9
1.8
0.8
0.19
0.09
0.13
1.8
e
n
Input-referred voltage noise density
nV/
√
Hz
f = 0.1 Hz to 10 Hz,
V
DS
= 5 V
Input-referred voltage noise
Input current noise
µV
PP
e
i
f = 1 kHz, V
DS
= 5 V
fA/
√
Hz
INPUT CURRENT
0.2
0.2
±10
V
DS
= 2
V
,
V
GS
=
–
0.7
V
,
V
VCH
= 5
V
,
V
VCL
=
–
5 V
I
G
Input gate current
pA
±2000
T
A
=
–
40°C to +85°C
T
A
=
–
40°C to +125°C
V
DS
= 0
V
,
V
GS
=
–
30 V
±10000
INPUT VOLTAGE
V
GSS
V
GSC
Gate-to-source breakdown voltage
V
DS
= 0
V
,
|
I
G
| < 100 µA
V
DS
= 10
V
,
I
DS
= 0.1 µA
I
DS
= 100 µA
V
V
−
40
−
0.9
Gate-to-source cutoff voltage
−
1.5
–
1.3
–
1.1
−
1.2
–
0.7
–
0.5
V
GS
Gate-to-source voltage
V
I
DS
= 2 mA
INPUT IMPEDANCE
R
IN
Gate input resistance
1
30
24
7
V
GS
=
–
5 V to 0 V
,
V
DS
= 0 V
V
DS
= 0 V
T
Ω
C
ISS
Input capacitance
V
DS
= 5 V
pF
C
RSS
Reverse transfer capacitance
V
DS
= 0 V
OUTPUT
24
22
35
46
57
I
DSS
gm
Drain-to-source saturation current
Transconductance
V
DS
= 10
V
,
V
GS
= 0 V
mA
mS
T
A
=
–
40°C to +125°C
I
DS
= 100 µA
3
18
68
I
DS
= 2 mA
G
FS
Full conduction transconductance
Drain-to-source breakdown voltage
Output capacitance
V
DS
= 10
V
,
V
GS
= 0 V
|I
DS
| < 100 µA, V
GS
=
–
2 V
V
DS
= 5 V
55
40
80
mS
V
V
DSS
C
OSS
8
pF
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6.6 Typical Characteristics
at T
A
= 25°C, I
DS
= 2 mA, common-source configuration, and V
DS
= 5 V (unless otherwise noted)
图
6-1. Drain-to-Source Current vs Gate-to-Source Voltage
图
6-2. Drain-to-Source Current vs Drain-to-Source Voltage
图
6-3. Drain-to-Source Current vs Drain-to-Source Voltage
图
6-4. Common Source Transconductance vs Drain-to-Source
Current
图
6-6. Gate Current vs Gate-to-Source Voltage
图
6-5. Gate Current vs Drain-to-Source Voltage
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6.6 Typical Characteristics (continued)
at T
A
= 25°C, I
DS
= 2 mA, common-source configuration, and V
DS
= 5 V (unless otherwise noted)
V
DS
= 5 V
图
6-7. Gate-to-Source Voltage vs Temperature
图
6-8. I
DSS
vs Drain-to-Source Voltage
f = 1kHz
图
6-9. Input-Referred Noise Density vs Frequency
图
6-10. Noise Density Contributors vs Input Gate Resistance
f = 1 kHz
图
6-11. Input-Referred Noise Spectral Density
vs Drain
‑
to
‑
Source Current
图
6-12. Input, Output, and Reverse Transfer Capacitance vs
Drain-to-Source Voltage
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7 Parameter Measurement Information
7.1 AC Measurement Configurations
The circuit configuration used for noise measurements is seen in
图
7-1
. The nominal I
DS
current is configured in
the schematic by calibrating V
–
. After I
DS
is fixed, the V
DS
voltage is set by calibrating V+. For input-referred
noise data, the gain of the circuit is calibrated from V
IN
to V
OUT
and used for the input-referred gain calculation.
V+
100
ꢀ
10 k
ꢀ
R
D
10 k
ꢀ
49.9
ꢀ
œ
V
OUT
+
J
F
E
1
50
OPA210
1
ꢁ
F
R
G
0
ꢀ
100 k
ꢀ
+
V
IN
R
S
œ
3 mF
10 k
ꢀ
V
œ
图
7-1. AC Measurement Reference Schematic
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8 Detailed Description
8.1 Overview
The JFE150 is an ultra-low noise JFET designed to create low-noise gain stages for very high output impedance
sensors or microphones. Advanced processing technology gives the JFE150 extremely low-noise performance,
a high gm/C
ISS
ratio, and ultra-low gate-current performance. Input protection diodes are integrated to clamp
high-voltage spurious input signals without the need for additional input diodes that can add leakage current or
distortion-creating non-linear capacitance. The JFE150 provides a next-generation device to implement low-
noise amplifiers for piezoelectric sensors, transducers, large-area condenser microphones, and hydrophones in
small-package options.
8.2 Functional Block Diagram
D
VCH
G
VCL
S
8.3 Feature Description
8.3.1 Ultra-Low Noise
Junction-gate field-effect transistors (JFE
T
s
) are commonly used as an input stage in high-input-impedance, low-
noise designs in audio, SONAR, vibration analysis, and other technologies. The JFE150 is a new generation
JFET device that offers very low noise performance at the lowest possible current consumption in high-input-
impedance amplifier designs. The JFE150 is manufactured on a high-performance analog process technology,
giving tighter process parameter control than a standard JFE
T
.
Designs that feature operational amplifiers (op amps) as the primary gain stage are common, but these designs
are not able to achieve the lowest possible noise as a result of the inherent challenges and tradeoffs required
from a full operational amplifier design. Noise in JFET designs can be evaluated in two separate regions: low-
frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that
require signal gain at frequencies less that 100 Hz. The JFE150 achieves extremely low 1/f noise in this range.
Thermal noise is noise in the region greater than 1 kHz and depends on the gain, or gm, of the circuit. The gm is
a function of the drain-to-source bias current; therefore, thermal noise is also a function of drain-to-source bias
current.
图
6-9
shows both 1/f and thermal noise with multiple bias conditions measured using the circuit shown
Noise is typically modeled as a voltage source (voltage noise) and current source (current noise) on the input.
The 1/f and thermal noise can be represented as voltage noise. Current noise is dominated by current flow into
the gate, and is called
shot noise
. The JFE150 features extremely low gate current, and therefore, extremely low
current noise.
图
6-10
shows how source impedance on the input is the dominant noise source. In nearly all
cases, noise created as a result of current noise is negligible.
8.3.2 Low Gate Current
The JFE150 features a maximum gate current of 10 pA at room temperature, making the device an excellent
choice for maximizing the gain and dynamic range from extremely high impedance sensors. Additionally, any
noise contributions as a result of gate current are minimized because of the negligible shot noise at low current
levels. As with all JFET devices, when the drain-to-source voltage increases, the gate current also increases.
Keep the drain-to-source voltage to less than 5 V for the lowest gate input current operation.
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8.3.3 Input Protection
The JFE150 features input protection diodes that are used for surge clamping and ESD events. The diodes are
rated to withstand high current surges for short times, steering current from the gate (G) pin to the VCH and VCL
pins. The diodes also feature very low leakage, removing the need for external protection devices that may have
high leakage currents or nonlinear capacitance that degrade the distortion performance.
8.4 Device Functional Modes
The JFE150 functionality is identical to standard N-channel depletion JFET devices. The gate-to-source (V
GS
voltage, drain-to-source voltage (V
DS
) and drain-to-source current (I
DS
) determine the region of operation.
)
•
For V
GS
< V
GSC
: JFE150 conduction channel is closed; I
DS
is only determined by junction leakage current.
•
For V
GS
> V
GSC
: Two modes of operation can exist depending on V
DS
. When V
DS
is less than the linear
(saturation) region threshold (see
图
8-1
), the device operates in the linear region, meaning that the device
behaves as a resistor connected from drain-to-source with minimal variation from any changes in V
GS
. When
V
DS
is greater than the linear (saturation) region threshold, I
DS
has a strong dependance on V
GS
, where the
relationship is described by the parameter gm.
Linear Region
Saturation Region
图
8-1. V
DS
vs I
DS
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9 Application and Implementation
备注
以下应用部分中的信息不属
于
TI
器件规格的范围
，
TI
不担保其准确性和完整性。
TI
的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计
，
以确保系统功能。
9.1 Application Information
9.1.1 Input Protection Diodes
The JFE150 features diodes that are used to help clamp voltage surges that can occur on the input sensor to the
gate. The diodes are connected between the gate and two separate pins, VCL and VCH. The clamping
mechanism works by
steering
current from the gate into the VCL or VCH nodes when the voltage at the gate is
less than VCL or greater than VCH.
图
9-1
shows an example of a microphone input circuit where a dc blocking
capacitor operates with a large dc voltage. When the microphone input is dropped or shorted, the dc blocking
capacitor discharges into the VCL or VCH nodes, thus helping eliminate large signal transient voltages on the
gate. There are also clamping diodes from the drain and source to VCL and VCH, respectively. The clamping
diodes can withstand high surge currents up to 200 mA for 50 ms; however, limit dc current to less than 20 mA.
48 V
VCH
D
6
.
8 k
Ω
C
D
C
10
…
F
R
G
G
J
F
E
1
50
i
G
R
B
VCL
S
R
L
图
9-1. JFE150 Clamping Diode Example
图
9-1
shows an example of configuring the diode clamp to protect the JFET against overvoltage in a phantom-
powered microphone circuit. Phantom power typically delivers 48 V through a 6.8-k
Ω
pullup resistor to a
microphone or dynamic load. If the microphone is disconnected, dc blocking capacitor C
DC
can be biased up to
48
V
.
I
f the input to the capacitor is then shorted to ground (shown by the switch in
图
9-1
), the gate voltage can
exceed the absolute maximum rating for V
GS
. In this case, the blocking diode is used, along with current limiting
resistors R
G
and R
L
, to clamp the gate voltage to a safe level. Be aware that the thermal noise of R
G
couples
directly into the gate input; therefore, make sure to minimize the resistance of R
G
.
The clamping diodes are not required for operation. The V
GS
voltage can withstand
–
40
V
,
s
o clamping is not
required if the V
GS
voltage is kept greater than this limit. If the diodes are not needed, leave the VCL and VCH
nodes floating.
Most previous-generation JFET devices featured only three pins (gate, source, and drain). For these devices,
the gate pin is in the same physical location as the VCL pin on the JFE150.
T
o
t
est the JFE150 in a three-pin
socket, short pin 2 of the JFE150 (VCL) to pin 3 (G). When the devices are connected with pin 2 shorted to pin 3,
the diode from VCL is shorted out and cannot provide any clamping protection. The input capacitance (C
ISS
) also
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9.1.2 Capacitive Transducer Input Stage
Piezoelectric transducers are used for many different applications that require low-noise, high-gain performance.
These transducers exhibit high output impedance (> 10 M
Ω
), and therefore require very high impedance loading
for subsequent input stages. The JFE150 has ultra-low input gate current (maximum I
G
= ±10 pA) and low input
capacitance (C
ISS
= 24 pF), which makes the device an excellent choice for transducers with an effective
capacitance of greater than 240 p
F
.
F
or smaller, lower-capacitance transducers, the C
ISS
may impact the gain of
the front end by attenuating the input signal, thereby reducing the noise performance.
9.1.3 Common-Source Amplifier
The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers, the basic circuit is
V
+
R
D
V
OUT
J
F
E
1
50
R
G
+
V
IN
R
S
œ
图
9-2. Common-Source Amplifier
V
gm
*
R
D
1 +
gm
*
R
OUT
=
−
(1)
V
IN
S
Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased as
a result of increasing gm (see
图
6-4
). As a result, the input-referred noise decreases as bias current is
performance. The JFE150, however, delivers significantly lower noise performance than most operational
amplifiers at the same current consumption. The bias current (I
DS
) is set by the value of the source resistor, R
S
,
图
9-3. Drain-to-Source Current vs R
S
, V
DS
= 5 V
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The bias current varies according to the resistor and threshold voltage tolerances. Additionally, thermal noise
associated with R
S
couples directly into the gain of the circuit, degrading the overall noise performance.
T
o
improve the circuit in
图
9-4
, use a current-source biasing scheme. Current-source biasing removes the JFET
threshold variation from the biasing scheme, and allows for lower-value filtering capacitance (C
S
) for equivalent
filtering due to the high output impedance of current sources.
V
+
R
D
V
OUT
J
F
E
1
50
R
G
+
C
S
V
IN
œ
I
BIAS
V
œ
图
9-4. Common-Source Amplifier With Current-Source Biasing
9.1.4 Composite Amplifiers
The JFE150 can be configured to provide a low-noise, high-input impedance front-end stage for a typical op
amp. Open-loop transistor gain stages shown previously suffer from wide gain variations that are dependent on
the forward transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET
front-end + operational amplifier) achieves excellent results by allowing for a fixed gain determined by external
resistors, and improving the noise and bandwidth of the operational amplifier. The JFE150 gain stage provides a
boost to the open-loop performance of the system, extending the bandwidth beyond what the operational
amplifier alone can provide, and gives a high-input impedance, ultra-low noise input stage to interface with high
source impedance microphones.
图
9-5
shows a generic schematic representation of a current-feedback composite amplifier. The component
C
F
V
D
D
R
D
C
D
œ
OPA
J
F
E
1
50
V
OUT
V
BIASO
+
C
B
R
G
+
R
B
V
IN
R
S2
œ
R
S
C
S
图
9-5. Low Noise, High Input Impedance Composite Amplifier
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表
9-1. Composite Amplifier Component List and Function
COMPONENT
DESCRIPTION
RELATED EQUATION
DC blocking capacitor for input source. Use a dc blocking capacitor if
the dc voltage of the input source is not the same as the gate bias
voltage.
1
f
=
(2)
C
B
–3
dBDC
2*
π
*
R
R
*
C
B
1
B
2
B
1
Bias resistor. Use biasing resistors to set the dc voltage at the gate.
High-value resistors can be used without an impact to noise if the
source impedance and bypass capacitor have sufficiently low
impedance.
R
B
Gate resistor. Can be used to help limit current flow into gate in
overvoltage cases.
R
G
R
D
R
S
C
D
Drain resistor. Sets gain of JFET stage in common source biasing,
along with gm and R
S
.
thermal noise directly impacts noise performance.
DC blocking capacitor. Blocks nominal drain voltage so the amplifier
operates at a midsupply bias point.
Feedback capacitor. Along with R
F
, this capacitor sets the
–
3
‑
dB
high-pass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the
–
3
‑
dB frequency. If
the GBW is not high enough, then the GBW sets the
–
3-dB
frequency.
1
f
=
(3)
C
F
–3
dBHP
2*
π
*
R
*
C
F
F
Feedback resistor. Along with C
F
, this resistor sets the
–
3
‑
dB high-
pass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the
–
3
‑
dB frequency. If
the GBW is not high enough, then the GBW sets the
–
3-dB
frequency.
R
F
V
R
F2
Current feedback gain-setting resistor 1. Along with R
S2
, sets gain
closed-loop.
OUT
R
F2
R
S2
C
S
=
(4)
(5)
V
R
IN
S2
Current feedback gain-setting resistor 2. Along with R
S2
, sets gain
closed-loop. Resistor thermal noise directly impacts noise
performance.
1
Current feedback ac-coupling capacitor. This capacitor, along with R
2
,
sets the low-pass
–
3-dB frequency.
f
=
–3
dBLP
2*
π
*
R
*
C
S2
S
9.2 Typical Application
The JFE150 can be configured to provide a low-noise, high-input-impedance front-end stage for a typical op
amp. Single-transistor gain stages shown previously suffer from wide gain variations dependent on the forward
transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET front-end +
operational amplifier) achieves excellent results.
C
F
10 pF
12 V
R
D
10 k
ꢁ
C
D
10
ꢀ
F
œ
J
F
E
1
50
R
G
10
ꢁ
V
O
U
T
C
B
10
ꢀ
F
6 V
+
OP
A
2
02
+
R
B
1 M
ꢁ
R
S2
10
ꢁ
V
IN
œ
R
S
300
ꢁ
C
S
470
ꢀ
F
图
9-6. Low-Noise, High-Input-Impedance Composite Amplifier
Copyright © 2022
T
e
xas Instruments Incorporated
14
9.2.1 Design Requirements
PARAMETER
DESIGN GOAL
Gain
60 dB
Frequency response
Noise
60 Hz to 20 kHz
< 1.5 nV/
√
Hz
< 100 pA
Input current
Output swing
±5 V
9.2.2 Detailed Design Procedure
This design provides 60 dB of gain with extremely high input impedance at a very low frequency response. The
order of design priorities are as follows:
•
The JFE150 bias current is set by selecting the desired bias current and noise tradeoff (see
图
6-11
). The
input-referred noise is dominated by the JFE150 bias current and gain.
T
o
s
et the bias current point, adjust
•
After the bias current is selected, set the JFET stage gain as high as possible without pushing the device into
the linear region of operation. This is achieved by using the largest drain resistor (R
D
) possible while
maintaining a minimum of 2 V across the drain to source nodes. Be aware that the amplifier forces the drain
node to match the noninverting amplifier input in normal closed-loop operation. Both ac and dc voltages must
be considered, but generally, only the dc operating point on the drain is considered because the ac voltage
swing is minimal.
•
Set the closed gain according to R
F2
and R
S2
, as seen in
方程
式
4
. Thermal noise from R
S2
directly couples
into the circuit; therefore, small values for this resistor are required.
•
C
S
is required to block dc voltages from altering the bias point set by source resistor R
S
. C
S
also forms the
9.2.3 Application Curves
图
9-7. Voltage Gain
图
9-8. Input-Referred Noise Density
Copyright © 2022
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e
xas Instruments Incorporated
15
10 Power Supply Recommendations
The JFE150 is a JFET transistor with clamping diodes. There are no specific power-supply connections;
however, take care not to exceed any absolute maximum voltages on any of the pins if system supply voltages
greater than or equal to 40 V are used.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
Reduce parasitic coupling by running the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
Place the external components as close to the device as possible.
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
•
Keep high impedance input signals away from noisy traces.
•
Make sure supply voltages are adequately filtered.
•
Minimize distance between source-connected and drain-connected components to the JFE150.
•
Consider a driven, low-impedance guard ring around the critical gate traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
Clean the PCB following board assembly for best performance.
•
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
V
DD
R
D
V
DD
V
SS
VCH
VCL
G
D
S
V
SS
R
S
V
IN
C
S
图
11-1. JFE150 Layout Example, Common Source Configuration
Copyright © 2022
T
e
xas Instruments Incorporated
16
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice
®
for TI
PSpice
®
for TI
is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA
™
is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI
™
simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro
models, in addition to a range of both passive and active models. TINA-TI software provides all the conventional
dc, transient, and frequency domain analyses of SPICE, as well as additional design capabilities.
Available as a
free download
from the WEBENCH
®
Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software (from DesignSoft
™
) or TINA-TI software be installed.
12.1.1.3 TI Precision Designs
TI Precision Designs are analog solutions created by TI
’
s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
12.1.1.4 WEBENCH® Filter Designer
WEBENCH® Filter Designer
is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI’s vendor partners.
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
Copyright © 2022
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17
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
T
e
xas Instruments,
OPAx202 Precision, Low-Noise, Heavy Capacitive Drive, 36-V Operational Amplifiers
12.3
接收文档更新通知
改摘要。有关更改的详细信息
，
请查看任何已修订文档中包含的修订历史记录。
12.4
支持资源
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成
TI
技术规范
，
并且不一定反映
TI
的观点
；
请参阅
12.5 Trademarks
Burr-Brown
™
, TINA-TI
™
, and TI E2E
™
are trademarks of
T
e
xas Instruments.
TINA
™
and DesignSoft
™
are trademarks of DesignSoft, Inc.
WEBENCH
®
is a registered trademark of
T
e
xas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD.
T
e
xas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7
术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022
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18
PACKAGE OPTION ADDENDUM
30-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
JFE150DCKR
JFE150DCKT
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
3000 RoHS
& Green
250 RoHS
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1IF
1IF
SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
JFE150DCKR
JFE150DCKT
SC70
SC70
DCK
DCK
5
5
3000
250
178.0
178.0
9.0
9.0
2.4
2.4
2.5
2.5
1.2
1.2
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
21-Oct-2021
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
JFE150DCKR
JFE150DCKT
SC70
SC70
DCK
DCK
5
5
3000
250
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
重要声明和免责声明
TI“
按原样
”
提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用
TI
产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：
(1)
针对您的应用选择合适的
TI
产品，
(2)
设计、验
证并测试您的应用，
(3)
确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。
TI
授权您仅可将这些资源用于研发本资源所述的
TI
产品的应用。严禁对这些资源进行其他复制或展示。
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TI
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TI
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本、损失和债务，
TI
对此概不负责。
TI
反对并拒绝您可能提出的任何其他或不同的条款。
IMPORTANT NOTICE
邮寄地址：
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(TI)
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