Texas-Instruments-LMV324AIPWR
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LMV3xxA Low-Voltage Rail-to-Rail Output Operational A
m
p
l
ifiers
The robust design of the LMV3xxA family simplifies
1 Features
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter,
and no-phase reversal in overdrive conditions.
1
•
•
•
•
•
•
•
•
•
•
Low input offset voltage: ±1 mV
Rail-to-rail output
Unity-gain bandwidth: 1 MHz
Low broadband noise: 30 nV/
√
Hz
Low input bias current: 10 pA
Low quiescent current: 70 µA/Ch
Unity-gain stable
The LMV3xxA family is available in industry-standard
packages such as SOIC, MSOP, SOT-23, and
TSSOP packages.
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
3.91 mm × 4.90 mm
3.00 mm × 4.40 mm
1.60 mm × 2.90 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
Internal RFI and EMI filter
SOT-23 (5)
LMV321A
Operational at supply voltages as low as 2.5 V
SC70 (5)
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
SOIC (8)
TSSOP (8)
SOT-23 (8)
VSSOP (8)
SOIC (14)
TSSOP (14)
LMV358A
LMV324A
•
Extended temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Smoke detectors
Motion detectors
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Wearable devices
Large and small appliances
EPOS
Single-Pole, Low-Pass Filter
R
G
R
F
Barcode scanners
Sensor signal conditioning
Power modules
R
1
V
OUT
V
IN
Personal electronics
Active filters
C
1
1
2
p
R
1
C
1
f
=
–
3 dB
HVAC: heating, ventilating, and air conditioning
Motor control: AC induction
Low-side current sensing
V
OUT
V
IN
R
F
1
1 + sR
1
C
1
=
1 +
(
(
R
G
3 Description
The LMV3xxA family includes single – (LMV321A),
dual – (LMV358A), and quad-channel (LMV324A) low-
voltage (2.5 V to 5.5 V) operational amplifiers (op
amps) with rail-to-rail output swing capabilities. These
op amps provide a cost-effective solution for space-
constrained applications such as large appliances,
smoke detectors, and personal electronics where low-
voltage operation and high capacitive-load drive are
required. The capacitive-load drive of the LMV3xxA
family is 500 pF, and the resistive open-loop output
impedance makes stabilization easier with much
higher capacitive loads. These op amps are designed
specifically for low-voltage operation (2.5 V to 5.5 V)
with performance specifications similar to the LMV3xx
devices.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
8
9
7
12 Mechanical,
Packaging, and Orderable
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2019) to Revision F
Page
•
Added SOT-23 (U) package information to
Pin Configuration and Functions
section …………………………………………………..
4
Changes from Revision D (November 2018) to Revision E
Page
•
•
•
Changes from Revision C (August 2018) to Revision D
Page
•
•
•
•
•
Deleted DBV (SOT-23) and DCK (SC70) package preview note from the LM321A
Thermal Information
table ………………
7
Deleted D (SOIC) and PW (TSSOP) package preview note from the LM324A
Thermal Information
table ……………………..
7
Changes from Revision B (June 2018) to Revision C
Page
•
•
2
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Changes from Revision A (May 2018) to Revision B
Page
•
•
•
•
•
•
•
Changes from Original (December 2017) to Revision A
Page
•
•
Copyright © 2017–2020, Texas Instruments Incorporated
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5 Pin
Configuration and Functions
LMV321A DBV Package
5-Pin SOT-23
LMV321A DCK, LMV321AU DBV Package
5-Pin SC70, SOT-23
Top View
Top View
OUT
V
–
1
2
3
5
4
V+
+IN
V
–
1
2
3
5
4
V+
+IN
–
IN
–
IN
OUT
Pin Functions: LMV321A
PIN
I/O
DESCRIPTION
NAME
–IN
DBV
DCK, DBV (U)
4
3
1
2
5
3
1
4
2
5
I
Inverting input
Noninverting input
Output
+IN
I
OUT
V–
O
—
—
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
LMV358A D, DDF, DGK, PW Packages
8-Pin SOIC, VSSOP, TSSOP
Top View
OUT A
–
IN A
+IN A
V
–
1
2
3
4
8
7
6
5
V+
OUT B
–
IN B
+IN B
Pin Functions: LMV358A
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
3
6
5
1
7
4
8
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
I
I
Noninverting input, channel B
Output, channel A
O
O
—
—
Output, channel B
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
4
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LMV324A D, PW Packages
14-Pin SOIC, TSSOP
Top View
OUT A
1
2
3
4
5
6
7
14 OUT
D
13
–
IN D
A
D
–
IN A
+IN A
V+
12 +IN
D
11 V
–
+IN B
–
IN B
OUT B
10 +IN
C
9
8
–
IN C
B
C
OUT C
Pin Functions: LMV324A
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
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6 Specifications
6.1 Absolute
Maximum Ratings
over operating temperature range (unless otherwise noted)
(1)
MIN
0
MAX
UNIT
V
Supply voltage, ([V+] – [V–])
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
Common-mode
Differential
(V–) – 0.5
V
Voltage
(2)
Current
(2)
Signal input pins
V
–10
–55
–65
mA
Output short-circuit
(3)
Operating, T
A
Continuous
150
°C
°C
°C
Operating junction temperature, T
J
Storage temperature, T
stg
150
150
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions
. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input
pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit
to ground, one amplifier per package.
6.2 ESD
Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
(ESD)
Electrostatic discharge
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended
Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
V
S
T
A
Supply voltage
2.5
Specified temperature
–40
125
°C
6
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6.4 Thermal
Information: LMV321A
LMV321A
THERMAL METRIC
(1)
DBV (SOT-23)
5 PINS
232.8
DCK (SC70)
5 PINS
239.6
148.5
82.3
UNIT
R
θ
JA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
θ
JC(top)
R
θ
JB
153.8
100.9
ψ
JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
77.2
54.5
ψ
JB
100.4
81.8
R
θ
JC(bot)
N/A
N/A
(1) For
more information about traditional and new thermal metrics, see
Semiconductor and IC Package Thermal Metrics
.
6.5 Thermal
Information: LMV358A
LMV358A
THERMAL METRIC
(1)
D (SOIC)
8 PINS
147.4
94.3
DGK (VSSOP)
8 PINS
201.2
PW (TSSOP)
8 PINS
205.8
DDF (SOT-23)
8 PINS
183.7
UNIT
R
θ
JA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
R
θ
JC(top)
Junction-to-case (top) thermal resistance
85.7
106.7
112.5
R
θ
JB
ψ
JT
Junction-to-board thermal resistance
89.5
122.9
133.9
98.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
47.3
21.2
34.4
18.8
ψ
JB
89
121.4
132.6
97.6
(1) For
more information about traditional and new thermal metrics, see
Semiconductor and IC Package Thermal Metrics
.
6.6 Thermal
Information: LMV324A
LMV324A
THERMAL METRIC
(1)
D (SOIC)
14 PINS
102.1
56.8
PW (TSSOP)
8 PINS
148.3
UNIT
R
θ
JA
R
θ
JC(top)
R
θ
JB
ψ
JT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
68.1
58.5
92.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20.5
16.9
ψ
JB
58.1
91.8
(1) For
more information about traditional and new thermal metrics, see
Semiconductor and IC Package Thermal Metrics
.
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6.7 Electrical
Characteristics
For V
S
= (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to ±2.75 V), T
A
= 25°C, R
L
= 10 k
Ω
connected to V
S
/ 2, and V
CM
= V
OUT
= V
S
/ 2
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Vs = 5 V
±1
±4
±5
V
OS
Input offset voltage
mV
Vs = 5 V, T
A
= –40°C to 125°C
T
A
= –40°C to 125°C
dV
OS
/dT
PSRR
V
OS
vs temperature
±1
µV/°C
dB
Power-supply rejection ratio
V
S
= 2.5 to 5.5 V, V
CM
= (V–)
78
100
INPUT VOLTAGE RANGE
Common-mode
voltage range
V
CM
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) – 1
V
V
S
= 2.5 V, (V–) – 0.1 V < V
CM
< (V+) – 1.4 V
T
A
= –40°C to 125°C
86
95
77
68
V
S
= 5.5 V, (V–) – 0.1 V < V
CM
< (V+) – 1.4 V
T
A
= –40°C to 125°C
Common-mode
CMRR
dB
rejection ratio
V
S
= 5.5 V, (V–) – 0.1 V < V
CM
< (V+) + 0.1 V
T
A
= –40°C to 125°C
63
V
S
= 2.5 V, (V–) – 0.1 V < V
CM
< (V+) + 0.1 V
T
A
= –40°C to 125°C
INPUT BIAS CURRENT
I
B
Input bias current
Input offset current
Vs = 5 V
±10
±3
pA
pA
I
OS
NOISE
Input voltage noise
(peak-to-peak)
E
n
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
5.1
µV
PP
ƒ = 1 kHz, Vs = 5 V
ƒ = 10 kHz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
33
30
25
e
n
i
n
Input voltage noise density
Input current noise density
nV/
√
Hz
fA/
√
Hz
INPUT CAPACITANCE
C
ID
C
IC
Differential
1.5
5
pF
pF
Common-mode
OPEN-LOOP GAIN
V
S
= 5.5 V, (V–) + 0.05 V < V
O
< (V+) – 0.05 V, R
L
= 10 k
Ω
V
S
= 2.5 V, (V–) + 0.04 V < V
O
< (V+) – 0.04 V, R
L
= 10 k
Ω
V
S
= 2.5 V, (V–) + 0.1 V < V
O
< (V+) – 0.1 V, R
L
= 2 k
Ω
V
S
= 5.5 V, (V–) + 0.15 V < V
O
< (V+) – 0.15 V, R
L
= 2 k
Ω
100
115
98
A
OL
Open-loop voltage gain
dB
112
128
FREQUENCY RESPONSE
GBW
φ
m
Gain-bandwidth product
Vs = 5 V
1
76
1.7
3
MHz
°
Phase margin
Slew rate
V
S
= 5.5 V, G = 1
SR
Vs = 5 V
V/µs
To 0.1%, V
S
= 5 V, 2-V step , G = +1, C
L
= 100 pF
To 0.01%, V
S
= 5 V, 2-V step , G = +1, C
L
= 100 pF
V
S
= 5 V, V
IN
× gain > V
S
t
S
Settling time
µs
µs
4
t
OR
Overload recovery time
0.9
Total harmonic distortion
+ noise
V
S
= 5.5 V, V
CM
= 2.5 V, V
O
= 1 V
RMS
, G = +1, f = 1 kHz,
80-kHz measurement BW
THD+N
OUTPUT
0.005%
V
S
= 5.5 V, R
L
= 10 k
Ω
V
S
= 5.5 V, R
L
= 2 k
Ω
Vs = 5.5 V
20
40
50
75
Voltage output swing
from supply rails
V
O
mV
I
SC
Z
O
Short-circuit current
±40
1200
mA
Open-loop output impedance
Vs = 5 V, f = 1 MHz
Ω
POWER SUPPLY
V
S
Specified voltage range
2.5 (±1.25)
5.5 (±2.75)
125
V
I
O
= 0 mA, V
S
= 5.5 V
70
50
I
Q
Quiescent current per amplifier
Power-on time
µA
µs
I
O
= 0 mA, V
S
= 5.5 V, T
A
= –40°C to 125°C
V
S
= 0 V to 5 V, to 90% I
Q
level
150
8
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6.8 Typical
Characteristics
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
6
4
3.5
3
I
B
–
I
B
+
I
OS
I
B
–
I
B
+
I
OS
2.5
2
2
1.5
1
0
-2
-4
-6
-8
-10
0.5
0
-0.5
-1
-1.5
-2
-2.5
-40
-20
0
20
40
60
80
100 120 140
-3
-2
-1
Common-Mode Voltage (V)
0
1
2
3
Temperature (
è
C)
D006
D007
Figure 1. I
B
and I
OS
vs Temperature
Figure 2. I
B
and I
OS
vs Common-Mode Voltage
100
120
160
140
120
100
80
80
60
40
20
0
100
80
60
40
20
0
60
40
20
V
S
= 5.5 V
V
S
= 2.5 V
Gain
Phase
0
-20
-40
-20
0
20
40
60
80
100 120 140
1k
10k
100k
Frequency (Hz)
1M
Temperature (
è
C)
D008
D009
C
L
= 10 pF
Figure 3. Open-Loop Gain vs Temperature
Figure 4. Open-Loop Gain and Phase vs Frequency
80
70
60
50
40
30
20
10
0
160
140
120
100
80
Gain =
–
1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
60
40
20
-10
-20
0
-3
-2
-1 0
Output Voltage (V)
1
2
3
100
1k
10k 100k
Frequency (Hz)
1M
D010
D011
C
L
= 10 pF
Figure 5. Open-Loop Gain vs Output Voltage
Figure 6. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
3
2.5
2
120
100
80
60
40
20
0
PSRR+
PSRR
–
1.5
1
125°C
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-2.5
-3
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
100
1k
10k
Frequency (Hz)
100k
1M
D012
D013
Figure 7. Output Voltage vs Output Current (Claw)
Figure 8. PSRR vs Frequency
120
100
80
60
40
20
0
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (
è
C)
D014
D015
V
S
= 1.8 V to 5.5 V
Figure 9. DC PSRR vs Temperature
Figure 10. CMRR vs Frequency
2.5 V
Time (1 s/div)
D017
V
CM
= (V–) – 0.1 V to (V+) – 1.4 V
Figure 11. DC CMRR vs Temperature
Figure 12. 0.1 Hz to 10 Hz Integrated Voltage Noise
10
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Typical Characteristics (continued)
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
-50
120
100
-60
80
-70
60
-80
40
-90
20
RL = 2K
RL = 10K
0
10
-100
100
100
1k
Frequency (Hz)
10k
100k
1k
Frequency (Hz)
10k
D018
D019
V
S
= 5.5 V, V
CM
= 2.5 V, G = 1, BW = 80 kHz, V
OUT
= 0.5 V
RMS
Figure 13. Input Voltage Noise Spectral Density
Figure 14. THD + N vs Frequency
0
-20
70
G = +1, R
L
= 2 k
W
G = +1, R
L
= 10 k
W
G =
–
1, R
L
= 2 k
W
G =
–
1, R
L
= 10 k
W
60
50
40
30
20
10
0
-40
-60
-80
-100
0.001
0.01
0.1
Amplitude (V
RMS
1
2
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
)
D020
D021
V
S
= 5.5 V, V
CM
= 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz
Figure 15. THD + N vs Amplitude
Figure 16. Quiescent Current vs Supply Voltage
70
2000
1800
1600
1400
1200
1000
800
600
400
200
0
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100 120 140
1k
10k
100k
Frequency (Hz)
1M
10M
Temperature (
è
C)
D022
D023
Figure 17. Quiescent Current vs Temperature
Figure 18. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
Overshoot (+)
Overshoot (–)
0
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D024
D025
G = 1, V
IN
= 100 mVpp
G = –1, V
IN
= 100 mVpp
Figure 19. Small Signal Overshoot vs Capacitive Load
Figure 20. Small Signal Overshoot vs Capacitive Load
90
V
OUT
V
IN
80
70
60
50
40
30
20
10
0
Time (100
m
s/div)
0
200
400 600
Capacitance Load (pF)
800
1000
D027
D026
G = 1, V
IN
= 6.5 V
PP
Figure 22. No Phase Reversal
Figure 21. Phase Margin vs Capacitive Load
V
OUT
V
IN
V
OUT
V
IN
Time (20
m
s/div)
Time (10
m
s/div)
D028
D029
G = –10, V
IN
= 600 mV
PP
G = 1, V
IN
= 100 mV
PP
, C
L
= 10 pF
Figure 23. Overload Recovery
Figure 24. Small-Signal Step Response
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Typical Characteristics (continued)
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
V
OUT
V
IN
Time (10
m
s/div)
Time (1 μs/div)
D030
D031
G = 1, V
IN
= 4 V
PP
, C
L
= 10 pF
G = 1, C
L
= 100 pF, 2-V step
Figure 25. Large-Signal Step Response
Figure 26. Large-Signal Settling Time (Negative)
80
60
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
Time (1
m
s/div)
-40
-20
0
20
40
60
80
100
120
Temperature (
è
C)
D032
D033
G = 1, C
L
= 100 pF, 2-V step
Figure 27. Large-Signal Settling Time (Positive)
Figure 28. Short-Circuit Current vs Temperature
6
5
4
3
2
1
0
140
120
100
80
V
S
= 5.5 V
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
D035
D034
Figure 30. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
Figure 29. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
at T
A
= 25°C, V+ = 2.75 V, V– = –2.75 V, R
L
= 10 k
Ω
connected to V
S
/ 2, V
CM
= V
S
/ 2, and V
OUT
= V
S
/ 2 (unless otherwise
noted)
0
-20
-40
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
D036
Figure 31. Channel Separation
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7 Detailed
Description
7.1 Overview
The LMV3xxA is a family of low-power, rail-to-rail output op amps. These devices operate from 2.5 V to 5.5 V,
are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-
mode voltage range includes the negative rail and allows the LMV3xxA family to be used in many single-supply
applications. Rail-to-rail output swing significantly increases dynamic range, especially in low-supply applications,
and makes them suitable for driving sampling analog-to-digital converters (ADCs).
7.2 Functional
Block Diagram
V+
Reference
Current
V
IN+
V
IN
–
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
V
–
(Ground)
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7.3 Feature
Description
7.3.1 Operating
Voltage
The LMV3xxA family of op amps are for operation from 2.5 V to 5.5 V. In addition, many specifications such as
input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in the
Typical Characteristics
section.
7.3.2 Input
Common Mode Range
The input common-mode voltage range of the LMV3xxA family extends 100 mV beyond the negative supply rail
and within 1 V below the positive rail for the full supply voltage range of 2.5 V to 5.5 V. This performance is
achieved with a P-channel differential pair, as shown in the
Functional Block Diagram
. Additionally, a
complementary N-channel differential pair has been included in
parallel to eliminate issues with
phase reversal
that are common with previous generations of op amps. However, the N-channel pair is not optimized for
operation. TI recommends limiting any voltages applied at the inputs to less than V
CC
– 1 V to ensure that the op
7.3.3 Rail-to-Rail
Output
Designed as a low-power, low-voltage operational amplifier, the LMV3xxA family delivers a robust output drive
capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 k
Ω
, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
7.3.4 Overload
Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the LMV3xxA family is approximately 850 ns.
7.4 Device
Functional Modes
The LMV3xxA family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
16
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8 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application
Information
The LMV3xxA family of low-power, rail-to-rail output operational amplifiers is specifically designed for portable
applications. The devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of
general-purpose applications. The class AB output stage is capable of driving less than or equal to 10
‑
k
Ω
loads
connected to any point between V+ and V–. The input common-mode voltage range includes the negative rail,
and allows the LMV3xxA devices to be used in many single-supply applications.
8.2 Typical
Application
8.2.1 LMV3xxA
Low-Side, Current Sensing Application
Figure 32
shows the LMV3xxA configured in a low-side current sensing application.
V
BUS
I
LOAD
Z
LOAD
5V
+
LMV358A
V
OUT
Þ
+
R
SHUNT
V
SHUNT
R
F
0.1
Ω
57.6
kΩ
Þ
R
G
1.2
kΩ
Figure 32.
LMV3xxA in a Low-Side, Current-Sensing Application
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Typical Application (continued)
8.2.1.1 Design
Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
8.2.1.2 Detailed
Design Procedure
V
OUT
=
I
LOAD
ì
R
SHUNT
ì
Gain
(1)
The load current (I
LOAD
) produces a voltage drop across the shunt resistor (R
SHUNT
). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
V
SHUNT
_
MAX
100mV
1A
R
SHUNT
=
=
=
100m
W
I
LOA
D
_
MAX
(2)
amplified by the LMV3xxA
to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
V
OUT
_
MAX
–
V
OUT
_
MIN
(
)
Gain
=
V
I
N
_
MAX
–
V
I
N
_
MIN
(3)
Using
Equation 3
, the required gain is calculated to be 49 V/V, which is set with resistors R
F
and R
G
.
Equation 4
R
(
)
F
Gain
=
1
+
R
G
(4)
measured transfer function of the circuit shown in
Figure 32
. Notice that the gain is
only a function
of the
feedback and gain resistors. This gain is adjusted
by varying the
ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
8.2.1.3 Application
Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
I
LOAD
(A)
C219
Figure 33.
Low-Side, Current-Sense Transfer Function
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Typical Application (continued)
8.2.2 Single-Supply
Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through the
photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in
Figure 34
is
an example of a single-supply photodiode amplifier circuit using the LMV358A.
+3.3 V
R
1
11.5
kΩ
10 pF
C
F
V
REF
R
2
357
Ω
R
F
309
kΩ
+3.3 V
œ
LMV358A
V
OUT
+
V
REF
C
PD
I
IN
0-10 µA
R
L
10 k
ꢀ
47 pF
Figure 34.
Single-Supply Photodiode Amplifier Circuit
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Typical Application (continued)
8.2.2.1 Design
Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
8.2.2.2 Detailed
Design Procedure
The transfer function between the output voltage (V
OUT
), the input current, (I
IN
) and the reference voltage (V
REF
)
V
OUT
=
I
IN
ì
R
F
+
V
REF
(5)
Where:
≈
∆
«
’
÷
R
1
ì
R
2
R
1
+
R
2
◊
V
REF
=
V
ì
+
(6)
Set V
REF
to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
V
REF
0.1 V
=
=
0.0303
V
+
3.3 V
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 k
Ω
and R2 to 357
Ω
.
The required feedback resistance can be calculated based on the input current and desired output voltage.
V
OUT
–
V
REF
3.2 V
–
0.1 V
10
m
A
kV
R
F
=
=
=
310
ö
309 k
W
I
A
IN
(8)
Calculate the value for the feedback capacitor based on R
F
and the desired –3-dB bandwidth, (f
–3dB
) using
1
1
C
F
=
=
=
10.3 pF
ö
10 pF
2
ì
p
ì
R
F
ì
f
–
3dB
2
ì
p
ì
309 k
W
ì
50 kHz
(9)
The minimum op amp bandwidth required for this application is based on the value of R
F
, C
F
, and the
capacitance on the INx– pin of the LMV358A which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as
Equation 10
shows.
C
=
C
PD
+
C
CM
+
C
D
=
47 p
F
+
5 pF
+
1
p
F
=
53 pF
IN
(10)
C
IN
+
C
F
f
=
BGW
í
í
324 kHz
2
2
ì
p
ì
R
F
ì
C
F
(11)
The 1-MHz bandwidth of the LMV3xxA meets the minimum bandwidth requirement and remains stable in this
application configuration.
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Typical Application (continued)
8.2.2.3 Application
Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in
Figure 35
. The
3
2.5
2
120
100
80
1.5
1
60
0.5
0
40
10
100
1k 10k
Frequency (Hz)
100k
1M
0
2E-6
4E-6 6E-6
Input Current (A)
8E-6
1E-5
D001
D002
Figure 35. Photodiode Amplifier Circuit AC Gain Results
Figure 36. Photodiode Amplifier Circuit DC Results
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9 Power
Supply Recommendations
The LMV3xxA family is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The
Typical Characteristics
section presents parameters that may exhibit significant
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the
Absolute Maximum Ratings
table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the
Layout
Guidelines
section.
9.1 Input
and ESD Protection
The LMV3xxA family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA.
Figure 37
shows how a series input resistor can be added to the driven input to limit the input current.
The
added resistor
contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
I
OVERLOAD
10-mA maximum
V
OUT
Device
V
IN
5 k
W
Figure 37.
Input Current Protection
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10 Layout
10.1 Layout
Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to
the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing
a low-impedance path to ground.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the
ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is
much better as opposed to running the traces in parallel with the noisy trace.
•
•
•
and R
G
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout
Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
R
G
R
G
R
F
R
F
Place components
close to device and to
each other to reduce
pa
r
a
sitic error
s
.
OUT 1
Use low-ESR,
ceramic bypass
capacitor .
Place as
close to the device
as possible .
V
S+
GND
OUT1
V+
R
F
R
G
OUT 2
GND
I
N
1
œ
I
N
1
+
V
œ
OUT2
I
N
2
œ
I
N
2
+
R
F
VIN 1
GND
R
G
VIN 2
Keep input traces short
and
r
u
n the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor .
Place as
close to the device
as possible .
V
S
œ
Ground (GND) plane on another layer
as possible .
Figure 39.
Layout Example
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11 Device
and Documentation Support
11.1 Documentation
Support
11.1.1 Related
Documentation
For related documentation, see the following:
•
11.2 Related
Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
LMV321A
LMV358A
LMV324A
11.3 Receiving
Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support
Resources
TI E2E™ support forums
are an engineer’s go-to source for fast, verified answers and design help — straight
from the experts. Search
existing answers or ask your own question to get the quick design help you need.
Linked content is provided “AS IS” by the respective contributors. They do not constitute TI specifications and do
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic
Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
24
Copyright © 2017–2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
7-Jan-2020
PACKAGING INFORMATION
Orderable Device
LMV321AIDBVR
LMV321AIDCKR
LMV321AUIDBVR
LMV324AIDR
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT-23
SC70
DBV
5
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
1OIF
1C2
ACTIVE
PREVIEW
ACTIVE
DCK
DBV
D
3000
3000
2500
2000
3000
2500
250
Green (RoHS
& no Sb/Br)
CU SN
SOT-23
SOIC
5
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU SN
1WOF
14
14
8
Green (RoHS
& no Sb/Br)
LMV324
LMV324A
358A
LMV324AIPWR
LMV358AIDDFR
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDR
ACTIVE
TSSOP
PW
DDF
DGK
DGK
D
Green (RoHS
& no Sb/Br)
ACTIVE SOT-23-THIN
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAUAG
CU NIPDAUAG
CU SN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
8
Green (RoHS
& no Sb/Br)
1MAX
8
Green (RoHS
& no Sb/Br)
1MAX
8
2500
2000
Green (RoHS
& no Sb/Br)
MV358A
LMV358
LMV358AIPWR
TSSOP
PW
8
Green (RoHS
& no Sb/Br)
CU SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
7-Jan-2020
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
13-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
LMV321AIDBVR
LMV321AIDCKR
LMV324AIDR
SOT-23
SC70
DBV
DCK
D
5
5
3000
3000
2500
2000
3000
180.0
178.0
330.0
330.0
180.0
8.4
9.0
3.2
2.4
6.4
6.9
3.2
3.2
2.5
5.2
5.6
3.2
1.4
1.2
2.1
1.6
1.4
4.0
4.0
8.0
8.0
4.0
8.0
8.0
Q3
Q3
Q1
Q1
Q3
SOIC
14
14
8
15.4
12.4
8.4
12.0
12.0
8.0
LMV324AIPWR
LMV358AIDDFR
TSSOP
PW
DDF
SOT-
23-THIN
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
2500
250
330.0
330.0
330.0
330.0
12.4
12.4
15.4
12.4
5.3
5.3
6.4
7.0
3.4
3.4
5.2
3.6
1.4
1.4
2.1
1.6
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
2500
2000
LMV358AIPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
13-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV321AIDBVR
LMV321AIDCKR
LMV324AIDR
SOT-23
SC70
DBV
DCK
D
5
5
3000
3000
2500
2000
3000
2500
250
210.0
190.0
336.6
366.0
210.0
366.0
366.0
336.6
366.0
185.0
190.0
336.6
364.0
185.0
364.0
364.0
336.6
364.0
35.0
30.0
41.3
50.0
35.0
50.0
50.0
41.3
50.0
SOIC
14
14
8
LMV324AIPWR
LMV358AIDDFR
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDR
TSSOP
SOT-23-THIN
VSSOP
VSSOP
SOIC
PW
DDF
DGK
DGK
D
8
8
8
2500
2000
LMV358AIPWR
TSSOP
PW
8
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 – 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 – 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 – 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
PACKAGE OUTLINE
D0008A
SOIC – 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1]
C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0
-15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0
-15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 –
8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
EXAMPLE BOARD LAYOUT
D0008A
SOIC – 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061
)
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 )
TYP
[0.05]
5
4
6X (.050
)
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
D0008A
SOIC – 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061
)
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 )
TYP
[0.05]
5
4
6X (.050
)
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
PACKAGE OUTLINE
PW0008A
TSSOP – 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 –
8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP – 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP – 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
PACKAGE OUTLINE
DDF0008A
SOT-23 – 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 –
8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 – 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 – 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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