Texas-Instruments-TPD4F003DQDR
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TPDxF003 Four-, Six-, and Eight-Channel EMI Filters
W
i
th Integrated ESD Protection
1 Features
3 Description
The TPDxF003 family is a series of highly integrated
devices designed to provide Electromagnetic
Interference (EMI) filtering in all systems subjected to
electromagnetic interference. These filters also
provide a Transient Voltage Suppressor (TVS) diode
circuit for Electrostatic Discharge (ESD) protection
which prevents damage to the application when
subjected to ESD stress far exceeding IEC 61000-4-2
(Level 4).
1
•
Four-, Six-, and Eight-Channel EMI Filtering for
Data Ports
•
•
•
–3 dB Bandwidth of 200 MHz
Greater than 25 dB attenuation at 1 GHz
IEC 61000-4-2 Level 4 ESD Protection
–
–
±12-kV Contact Discharge
±20-kV Air Gap Discharge
•
Pi-Style (C-R-C) Filter Configuration
(R = 100
Ω
, C
TOTAL
= 17 pF)
The TPDxF003 family is specified for –40°C to 85°C
operation. These filters are also packaged in space-
saving 0.4-mm pitch DQD packages.
•
•
Low 10-nA Leakage Current
Easy Flow-Through Routing
PART NUMBER
TPD4F003
PACKAGE
WSON (8)
WSON (12)
WSON (16)
BODY SIZE (NOM)
1.70 mm x 1.35 mm
2.50 mm x 1.35 mm
3.30 mm x 1.35 mm
2 Applications
•
•
•
•
•
Display Interfaces
Cell Phones
TPD6F003
TPD8F003
Tablets
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SVGA Video Connections
Memory Interfaces
Equivalent Schematic
100
Ω
Ch_Out
Ch_In
8.5 pF
8.5 pF
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
8
9
7
12 Mechanical,
Packaging, and Orderable
4 Revision
History
Changes from Revision D (January 2010) to Revision E
Page
•
Added
Handling Rating
table,
Feature Description
section,
Device Functional Modes
,
Application and
Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device and Documentation
2
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5 Pin
Configuration and Functions
DQD PACKAGE
(TOP VIEW)
TPD4F003
TPD6F003
TPD8F003
Ch1_In
Ch2_In
Ch3_In
Ch4_In
Ch1_Out
Ch2_Out
Ch3_Out
Ch4_Out
Ch1_In
Ch2_In
Ch3_In
Ch4_In
Ch5_In
Ch6_In
Ch1_Out
Ch2_Out
Ch3_Out
Ch4_Out
Ch5_Out
Ch6_Out
Ch1_In
Ch2_In
Ch3_In
Ch4_In
Ch5_In
Ch6_In
Ch7_In
Ch8_In
Ch1_Out
Ch2_Out
Ch3_Out
Ch4_Out
Ch5_Out
Ch6_Out
Ch7_Out
Ch8_Out
1
2
3
4
8
7
6
5
1
2
3
4
5
6
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
8
1.7 mm x 1.35 mm x 0.75 mm
(0.4-mm pitch)
7
2.5 mm x 1.35 mm x 0.75 mm
(0.4-mm pitch)
3.3 mm x 1.35 mm x 0.75 mm
(0.4-mm pitch)
Pin Functions – TPD4F003
PIN
I/O
DESCRIPTION
NAME
No.
ChX_In
ChX_Out
GND
1, 2, 3, 4
5, 6, 7, 8
GND
IO
IO
G
ESD-protected channel, connected to corresponding ChX_Out
ESD-protected channel, connected to corresponding ChX_In
Ground
Pin Functions – TPD6F003
PIN
I/O
Description
Name
No.
ChX_In
1, 2, 3, 4, 5, 6
IO
IO
G
ESD-protected channel, connected to corresponding ChX_Out
ESD-protected channel, connected to corresponding ChX_In
Ground
7, 8, 9, 10, 11,
12
ChX_Out
GND
GND
Pin Functions – TPD8F003
PIN
I/O
Description
Name
No.
1, 2, 3, 4, 5, 6,
7, 8
ChX_In
IO
ESD-protected channel, connected to corresponding ChX_Out
9, 10, 11, 12,
13, 14, 15, 16
ChX_Out
GND
IO
G
ESD-protected channel, connected to corresponding ChX_In
Ground
GND
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6 Specifications
6.1 Absolute
Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
6
UNIT
V
V
IO
T
J
IO to GND
Junction temperature
150
°C
(1) Stresses
beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
6.2 Handling
Ratings
MIN
MAX
150
UNIT
T
stg
Storage temperature range
–65
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins
(1)
±15
kV
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins
(2)
±1500
V
(ESD)
Electrostatic discharge
IEC 61000-4-2 ESD Rating – Contact
IEC 61000-4-2 ESD Rating – Air
±12
±20
kV
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
IO
T
A
0
V
–40
85
°C
6.4 Thermal
Information
TPD4F003
TPD6F003
DQD
TPD8F003
THERMAL METRIC
(1)
UNIT
8 PINS
115.6
108.5
66.4
12 PINS
89.2
16 PINS
80.8
88.3
45.8
9.2
R
θ
JA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
R
θ
JC(top)
R
θ
JB
100.1
50.5
°C/W
ψ
JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
9.4
ψ
JB
65.9
50.0
45.4
31.8
R
θ
JC(bot)
33.2
31.0
(1) For
more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953
.
6.5 Electrical
Characteristics
T
A
= –40°C to 85°C (unless otherwise noted)
PARAMETER
DC breakdown voltage
Resistance
TEST CONDITIONS
MIN
6
TYP
(1)
MAX UNIT
V
BR
R
I
IO
= 10
μ
A
V
85
100
8.5
10
115
Ω
pF
C
Capacitance (C1 or C2)
Channel leakage current
Cut-off frequency
V
IO
= 2.5 V
V
IO
= 3.3 V
I
IO
f
C
nA
Z
SOURCE
= 50
Ω
, Z
LOAD
= 50
Ω
200
MHz
(1) Typical
values are at T
A
= 25°C.
4
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6.6 Typical
Characteristics
6.6.1 IEC
Clamping Waveforms
(clamp voltage measured both at Ch_Out and Ch_In)
140
120
100
80
140
120
100
80
Ch_In
Ch_Out
Ch_In
Ch_Out
60
60
40
40
20
20
0
0
-20
-40
-20
-40
0
25
50
75
100
125
150
175
200
0
25
50
75
100
Time (ns)
125
150
175
200
Time (ns)
Figure 2. With 12 kV Contact ESD Stress at Ch_Out
Figure 1. With 8 kV Contact ESD Stress at Ch_Out
40
40
20
0
20
0
C
h
_In
Ch_Out
Ch_In
Ch_Out
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
25
50
75
100
Time (ns)
125
150
175
200
0
25
50
75
100
Time (ns)
125
150
175
200
Figure 3. With -8 kV Contact ESD Stress at Ch_Out
Figure 4. With -12 kV Contact ESD Stress at Ch_Out
0
-5
0.001
0.0008
0.0006
0.0004
0.0002
0
TPD8F003
TPD6F003
TPD4F003
-10
-15
-20
-25
-30
-35
-40
-45
-50
TPD8F003
3dB drop/Bias of 0.0V
-3dB = 198MHz
Peak/Freq/Db
= 2.57/45 GHz/dB
TPD6F003
3dB drop/Bias of 0.0V
-3dB = 197MHz
Peak/Freq/Db
= 2.30/47 GHz/dB
TPD4F003
3dB drop/Bias of 0.0V
-3dB = 197MHz
Peak/Freq/Db
= 2.25/45 GHz/dB
-0.0002
-0.0004
-0.0006
-0.0008
-0.001
1.00E+06
1.00E+07
1.00E+08
1
.
0
0E+09
1
.
0
0E+10
Fr
e
quency (Hz)
-4
-2
0
2
4
6
8
V
o
l
t
a
ge (V)
Figure 6. DC Voltage-Current Sweep Across Input/Output
Pins
Figure 5. Frequency Response
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6.6.2 Channel-to-Channel
Crosstalk
0
0
-5
-5
Adjacent Signal Pair
Farthest Signal Pair
A
d
jacent Signal Pair
Farthest Signal Pair
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1.00E+10
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1.00E+10
Frequency (Hz)
Frequency (Hz)
Figure 7. TPD4F003
Figure 8. TPD6F003
0
-5
Adjacent Signal pair
Farthest Signal Pair
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1.00E+10
Frequency (Hz)
Figure 9. TPD8F003
6
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7 Detailed
Description
7.1 Overview
The TPDxF003 family is a series of highly integrated devices designed to provide EMI filtering in all systems
subjected to electromagnetic interference. These filters also provide a Transient Voltage Suppressor (TVS) diode
circuit for ESD protection which prevents damage to the application when subjected to ESD stress far exceeding
IEC 61000-4-2 (Level 4).
7.2 Functional
Block Diagram
100
Ω
Ch_Out
Ch_In
8.5 pF
8.5 pF
GND
7.3 Feature
Description
The TPDxF003 family is a line of ESD and EMI filtering devices designed to reduce EMI emissions and provide
system level ESD protection. Each device can dissipate ESD strikes above the maximum level specified by IEC
61000-4-2 international standard. Additionally, the EMI filtering structure reduces EMI emissions by providing
high frequency roll-off.
7.3.1 Four-,
Six-, and Eight-Channel EMI Filtering for Data Ports
These devices provide EMI filtering for four, six, or eight channels of data lines.
7.3.2 –3
dB Bandwidth of 200 MHz
These devices have a through –3dB bandwidth of 200 MHz.
7.3.3 Greater
Than 25 dB Attenuation at 1 GHz
Signal attenuation is above 25dB at 1 GHz, which provides significant reduction in spurious emissions.
7.3.4 Robust
ESD Protection Exceeds IEC 61000-4-2
The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact ESD is rated at ±12 kV and
Air-gap ESD is rated at ±20 kV.
7.3.5 Pi-Style
(C-R-C) Filter Configuration
This family of devices has a pi-style filtering configuration composed of a series resistor and two capacitors in
parallel with the I/O pins. The typical resistor value is 100
Ω
and the typical capacitor values are 8.5 pF each.
7.3.6 Low
10-nA Leakage Current
The I/O pins feature an ultra-low leakage current of 10-nA (typical) with a bias of 3.3 V.
7.3.7 Easy
Flow-Through Routing
The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through
routing which requires minimal changes to existing layout for addition of these devices.
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7.4 Device
Functional Modes
The TPDxF003 family of devices are passive integrated circuits that passively filter EMI and trigger when
voltages are above V
BR
or below the lower diode voltage (–0.6 V). During ESD events, voltages as high as ±20
kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall
below the trigger levels, the device reverts to passive.
8
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8 Applications
and Implementation
8.1 Application
Information
The TPDxF003 family are diode type TVS’ integrated with series resistors for filtering emitted EMI. As signal
passes through the device, higher frequency components are filtered out. This device also provides a path to
ground during ESD events and isolates the protected IC. As the current from ESD passes through the TVS, only
a small voltage drop is present across the diode. This is the voltage presented to the protected IC. In particular,
these filters are ideal for EMI filtering and protecting data lines from ESD at the display, keypad, and memory
interfaces.
8.2 Typical
Application
TPD6F003
R0
1
2
3
4
5
6
12
11
10
9
R1
R2
R3
R4
R5
8
7
TPD6F003
GND
1
2
3
4
5
6
12
11
10
9
G0
G1
G2
G3
G4
G5
8
7
TPD6F003
GND
1
2
3
4
5
6
12
11
10
9
B0
B1
B2
B3
B4
B5
8
7
GND
Figure 10.
Display Panel Schematic
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Typical Application (continued)
8.2.1 Design
Requirements
For this design example, three TPD6F003 devices are used in an 18-bit display panel application. This will
provide a complete ESD and EMI protection solution for the display connector.
Given the display panel application, the following parameters are known.
DESIGN PARAMETER
Signal range on all pins except GND
Operating Frequency
VALUE
0 V to 5 V
100 MHz
8.2.2 Detailed
Design Procedure
To begin the design process, some design parameters must be decided; the designer need to know the
following:
•
•
Signal range on all the protected lines
Operating frequency
8.2.2.1 Signal
Range on All Protected Lines
The TPD6F003 has 8 identical protection channels for signal lines. All I/O pins will support a signal range from 0
to 5.5 V.
8.2.2.2 Operating
Frequency
The TPD6F003 has a 200 MHz –3dB bandwidth, which supports the operating frequency for this display.
8.2.3 Application
Curve
0
±
5
±
10
±
15
±
20
Channel 1
±
25
Channel 2
±
30
Channel 3
±
35
Channel 4
±
40
Channel 5
±
45
Channel 6
±
50
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
Frequency (Hz)
C001
Figure 11.
Frequency Response
10
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9 Power
Supply Recommendations
This family of devices are passive EMI and ESD devices so there is no need to power them. Care should be
taken to not violate the recommended V
IO
specification (5.5 V) to ensure the device functions properly.
10 Layout
10.1 Layout
Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout
Example
This application is typical of an 18-bit RGB display panel layout.
VIA to GND Plane
GND
GND
GND
Figure 12.
TPD6F003 Layout
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11 Device
and Documentation Support
11.1 Related
Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TPD4F003
TPD6F003
TPD8F003
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Copyright © 2008–2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
30-Oct-2018
PACKAGING INFORMATION
Orderable Device
TPD4F003DQDR
TPD6F003DQDR
TPD8F003DQDR
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
WSON
WSON
WSON
DQD
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
5RS
47S
ACTIVE
ACTIVE
DQD
DQD
12
16
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 85
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
-40 to 85
(5US, 5UU)
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
30-Oct-2018
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
15-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
TPD4F003DQDR
TPD6F003DQDR
TPD8F003DQDR
WSON
WSON
WSON
DQD
DQD
DQD
8
3000
3000
3000
180.0
180.0
330.0
8.4
8.4
1.65
1.68
1.65
2.0
2.79
3.6
0.95
0.91
0.95
4.0
4.0
4.0
8.0
8.0
Q1
Q1
Q1
12
16
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
15-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4F003DQDR
TPD6F003DQDR
TPD8F003DQDR
WSON
WSON
WSON
DQD
DQD
DQD
8
3000
3000
3000
183.0
183.0
358.0
183.0
183.0
335.0
20.0
20.0
35.0
12
16
Pack Materials-Page 2
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