Texas-Instruments-TPIC5421LNE
| Part # | Texas-Instruments-TPIC5421LNE |
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
•
Low r
. . . 0.4
Ω
Typ
•
Voltage Output . . . 60 V
DW PACKAGE
(TOP VIEW)
DS(on)
•
Input Protection Circuitry . . . 18 V
•
Pulsed Current . . . 3 A Per Channel
•
Extended ESD Capability . . . 4000 V
•
Direct Logic-Level Interface
GND
SOURCE2/GND
GATE2
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
SOURCE4/GND
GATE4
NC
NC
DRAIN4
SOURCE3
DRAIN3
GATE3
NC
DRAIN2
15
SOURCE1
description
14
13
12
11
DRAIN1
GATE1
NC
The TPIC5421L is a monolithic gate-protected
logic-level power DMOS array that consists of four
electrically isolated N-channel enhancement-
mode DMOS transistors, two of which are
configured with common source. Each transistor
features integrated high-current zener diodes
NC
NC
NE PACKAGE
(TOP VIEW)
(Z
and Z
) to prevent gate damage in the
CXa
CXb
SOURCE1
DRAIN1
GATE1
DRAIN2
SOURCE2/GND
GATE2
1
2
3
4
5
6
7
8
16
15
14
event that an overstress condition occurs. These
zener diodes also provide up to 4000 V of ESD
protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-k
Ω
resistor.
13
GND
12
GND
GND
GND
11
10
9
GATE3
GATE4
The TPIC5421L is offered in a 20-pin wide-body
surface-mount (DW) package and a 16-pin
thermally-enhanced dual-in-line (NE) package
and is characterized for operation over the case
temperature of
−
4
0
°
C to 125
°
C.
DRAIN3
SOURCE3
SOURCE4/GND
DRAIN4
NC − No internal connection
schematic
14
7
8
DRAIN1
GATE1
DRAIN3
GATE3
Q1
Q3
Z1
D1
D2
Z3
13
Z
C1b
Z
C3b
Z
6
Z
C1a
15
C3a
SOURCE3
DRAIN4
SOURCE1
16
5
DRAIN2
Q2
Q4
19
3
GATE4
GATE2
Z2
Z4
Z
Z
C2b
C4b
Z
C2a
Z
C4a
1, 2, 20
GND, SOURCE2, SOURCE4
NOTE A:
For correct operation, no terminal may be taken below GND.
Pin numbers shown are for the DW package.
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Copyright
1995,
T
e
xas Instruments Incorporated
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1
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•
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POST OFFICE BOX 1443
•
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60 V
DS
Source-to-GND voltage (Q1, Q3)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 V
Drain-to-GND voltage (Q1, Q3)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 V
Drain-to-GND voltage (Q2, Q4)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60 V
Gate-to-source voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−9 V to 18 V
GS
Continuous drain current, each output, T
= 25
°
C: NE package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 A
C
DW package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 A
Continuous source-to-drain diode current, T
= 25
°
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 A
C
Pulsed drain current, each output, I
, T
= 25
°
C (see Note 1 and Figure 15)
. . . . . . . . . . . . . . . . . . . . .
3 A
max
C
Continuous gate-to-source zener-diode current, T
= 25
°
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
C
Pulsed gate-to-source zener-diode current, T
= 25
°
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
500 mA
C
Single-pulse avalanche energy, E
, T
= 25
°
C (see Figures 4 and 16)
. . . . . . . . . . . . . . . . . . . . . . .
180 mJ
AS
C
Continuous total power dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
See Dissipation Rating
T
a
ble
Operating virtual junction temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40
°
C to
150
°
C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40
°
C to
125
°
C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65
°
C to
150
°
C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260
°
C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1:
Pulse duration = 10 ms, duty cycle = 2%
DISSIPATION RATING TABLE
≤
25
°
C DERATING
FACTOR
T
C
T =
125
°
C
C
POWER RATING
PACKAGE
POWER RATING
ABOVE T
= 25
°
C
C
DW
NE
1125 mW
9.0 mW/
°
C
225 mW
2075 mW
16.6 mW/
°
C
415 mW
2
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•
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•
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
electrical characteristics, T
= 25
°
C (unless otherwise noted)
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
Drain-to-source breakdown voltage
I
I
= 250
µ
A,
V
V
= 0
= V
60
V
(BR)DSX
D
GS
= 1 mA,
,
D
DS
GS
Gate-to-source threshold voltage
1.5
1.85
2.2
V
GS(th)
See Figure 5
V
V
Gate-to-source breakdown voltage
Source-to-gate breakdown voltage
I
I
= 250
µ
A
= 250
µ
A
18
9
V
V
(BR)GS
GS
(BR)SG
SG
Reverse drain-to-GND breakdown voltage (across
D1, D2)
V
Drain-to-GND current = 250
µ
A
100
V
V
(BR)
I
D
= 1 A,
= 5
V
,
V
GS
V
Drain-to-source on-state voltage
0.4 0.475
DS(on)
See Notes 2 and 3
I
= 1 A,
= 0 (Z1, Z2, Z3, Z4),
S
V
V
Forward on-state voltage, source-to-drain
V
0.9
1.1
V
F(SD)
GS
See Notes 2 and 3 and Figure 12
I
= 1 A (D1, D2),
D
Forward on-state voltage, GND-to-drain
Zero-gate-voltage drain current
4.6
V
F
See Notes 2 and 3
T
T
= 25
°
C
0.05
0.5
20
1
10
V
V
= 48
V
,
= 0
C
DS
GS
I
µ
A
DSS
= 125
°
C
C
I
I
Forward-gate current, drain short circuited to source
Reverse-gate current, drain short circuited to source
V
= 15
V
,
= 5
V
,
V
V
= 0
= 0
200
100
1
nA
nA
GSSF
GS
SG
DS
V
10
GSSR
DS
T
= 25
°
C
0.05
0.5
C
C
I
Leakage current, drain-to-GND
V
= 48 V
DGND
µ
A
lkg
T
= 125
°
C
10
V
= 5
V
,
GS
= 1 A,
T
T
= 25
°
C
0.4 0.475
C
I
D
r
Static drain-to-source on-state resistance
Forward transconductance
Ω
DS(on)
See Notes 2 and 3
and Figures 6 and 7
= 125
°
C
0.65
0.68
C
V
= 15
V
,
I =
0.5 A,
D
DS
See Notes 2 and 3 and Figure 9
g
1.25
1.4
S
fs
C
C
Short-circuit input capacitance, common source
Short-circuit output capacitance, common source
220
120
275
150
iss
V
= 25
V
,
V
= 0,
oss
DS
f = 1 MHz,
GS
See Figure 11
pF
Short-circuit reverse-transfer capacitance,
common source
C
100
125
rss
NOTES: 2.
T
e
chnique should limit T
− T
to 10
°
C maximum.
J
C
3. These
parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T
= 25
°
C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
55
MAX
UNIT
Z1 and Z3
Z2 and Z4
D1 and D2
Z1 and Z3
Z2 and Z4
D1 and D2
150
200
0.06
0.3
t
rr
Reverse-recovery time
ns
I
V
= 0.5 A,
= 0,
V
= 48
V
,
S
DS
di/dt = 100 A/
µ
s,
GS
See Figures 1 and 14
Q
T
o
tal diode charge
µ
C
RR
0.7
3
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•
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•
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
resistive-load switching characteristics, T
= 25
°
C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
50
UNIT
t
t
t
t
Turn-on delay time
d(on)
d(off)
r2
Turn-off delay time
Rise time
20
40
V
t
= 25
V
,
R
= 25
Ω
,
t
r1
= 10 ns,
DD
= 10 ns,
L
ns
See Figure 2
21
42
f1
Fall time
9
18
f2
Q
Q
Q
T
o
tal gate charge
3.9
0.55
2.5
5
g
V
= 48
V
,
I
D
= 0.5 A,
V
GS
= 5
V
,
DS
See Figure 3
Threshold gate-to-source charge
Gate-to-drain charge
Internal drain inductance
Internal source inductance
Internal gate resistance
0.8
3.6
nC
gs(th)
gd
L
L
5
5
D
nH
S
R
0.25
Ω
g
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
90
MAX
UNIT
DW package
R
R
R
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance
Junction-to-pin thermal resistance
See Notes 4 and 6
See Notes 4 and 6
See Notes 5 and 6
θ
JA
θ
JB
θ
JP
NE package
DW package
DW package
NE package
60
53
°
C/W
30
25
NOTES: 4.
Package mounted on an FR4 printed-circuit board with no heatsink.
5. Package
mounted in intimate contact with infinite heatsink.
6. All
outputs with equal power
4
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•
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•
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
1.5
V
V
= 48 V
= 0
DS
GS
1
0.5
‡
Z1 and Z3
Reverse di/dt = 100 A/
µ
s
0
− 0.5
− 1
†
25% of I
RM
Shaded Area
= Q
RR
− 1.5
− 2
†
I
RM(REC)
t
rr(SD)
− 2.5
0
25
50
75 100
125 150 175 200 225 250
Time − ns
†
‡
I
= maximum recovery current
RM(REC)
The above waveform is representative of Z2, Z4, D1, and D2 in shape only.
Figure 1. Reverse-Recovery-Current Waveforms of Source-to-Drain Diode
V
DD
= 25 V
t
t
r1
f1
5 V
R
L
V
DS
V
GS
0 V
Pulse Generator
V
GS
t
d(off)
t
d(on)
DUT
t
r2
t
f2
C
= 30 pF
R
50
Ω
L
gen
V
DD
(see Note A)
50
Ω
V
DS
V
DS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A:
C includes
probe and jig capacitance.
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
5
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•
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
Q
g
Same Type
12-V
Battery
as DUT
0.2
µ
F
50 k
Ω
5 V
0.3
µ
F
Q
Q
gs(th)
gd
V
DD
V
GS
V
DS
DUT
Gate Voltage
Time
I
G
= 100
µ
A
0 V
I
Current-
I Current-
D
Sampling Resistor
WAVEFORM
G
Sampling Resistor
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
V
DD
= 25 V
t
(see Note B)
5 V
av
t
w
23 mH
V
GS
V
DS
Pulse Generator
(see Note A)
0 V
I
D
I
AS
V
GS
(see Note B)
I
D
DUT
50
Ω
0 V
R
gen
V
= 60 V Min
50
Ω
(BR)DSX
V
DS
0 V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The
pulse generator has the following characteristics: t
≤
10 ns, t
≤
10 ns, Z
= 50
Ω
.
r
f
O
B. Input
pulse duration (t
) is increased until peak current I
= 3 A.
w
AS
I
V
t
av
AS
(BR)DSX
2
Energy test level is defined as E
+
+
180 mJ,
AS
where t
= avalanche time
av
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
6
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•
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•
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ꢃꢊ ꢈꢏ
ꢓ ꢏꢈ
ꢁꢒ ꢔ ꢏꢌꢐ
ꢍꢕ ꢒ
ꢖꢐꢑ ꢌꢌ ꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
vs
CASE TEMPERATURE
JUNCTION TEMPERATURE
2.5
2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DS
= V
GS
I =
1 A
D
V
= 4.5 V
GS
I
= 1 mA
D
1.5
1
V
GS
= 5 V
I
= 100
µ
A
D
0.5
0
− 40 − 20
0
20 40 60 80
100 120
140 160
− 40 − 20
0
20 40 60 80
100 120
140 160
T
J
− Junction Temperature −
°
C
T
C
− Case Temperature −
°
C
Figure 5
Figure 6
DRAIN CURRENT
vs
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
1
0.9
0.8
0.7
3
2
1
n
V
= 0.2 V
GS
T
J
= 25
°
C
T
J
= 25
°
C
0.6
0.5
V
= 4.5 V
GS
0.4
0.3
V
= 5 V
GS
0.2
V
GS
= 3 V
0.1
0.1
0
1
10
0
2
4
6
8
10 12 14 16 18 20
I
D
− Drain Current − A
V
DS
− Drain-to-Source Voltage − V
Figure 7
Figure 8
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ꢀ ꢁꢂ ꢃ
ꢄ ꢅ ꢆꢇ ꢈ
ꢉ ꢊꢋ ꢌꢂ
ꢍ ꢎꢏ
ꢐ ꢎꢑꢀꢏ
ꢊꢁ ꢌꢒ
ꢀꢏ ꢃ
ꢀꢏ ꢍꢐ
ꢈꢒ ꢎ ꢂꢃꢊ
ꢈ ꢏꢓꢏꢈ
ꢁꢒꢔ ꢏꢌ
ꢐꢍ ꢕꢒ
ꢖꢐꢑꢌ ꢌꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DISTRIBUTION OF
GATE-TO-SOURCE VOLTAGE
FORWARD TRANSCONDUCTANCE
30
25
20
15
10
5
3
2
Total Number of
Units = 2888
V
= 25 V
= 0.5 A
= 25
°
C
DS
I
D
T
J
T
=
−
4
0
°
C
J
1
0
T
= 150
°
C
J
T
= 125
°
C
J
T
J
= 25
°
C
T
J
= 75
°
C
0
0
1
2
3
4
5
V
GS
− Gate-to-Source Voltage − V
g
fs
− Forward Transconductance − S
Figure 9
Figure 10
CAPACITANCE
vs
SOURCE-TO-DRAIN DIODE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN VOLTAGE
500
450
400
350
300
250
200
150
100
50
5
4
3
V
= 0
f = 1 MHz
= 0
GS
V
GS
= 25
°
C
T
J
2
1
0.6
0.4
C
C
iss
T
J
= 125
°
C
= 150
°
C
T
=
−
4
0
°
C
J
oss
0.2
T
J
T
J
= 25
°
C
C
rss
T
J
= 75
°
C
0.1
0
10
20
30
40
0.1
10
1
V
DS
− Drain-to-Source Voltage − V
V
SD
− Source-to-Drain Voltage − V
Figure 11
Figure 12
8
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ꢀ ꢁ
ꢂꢃ ꢄꢅ
ꢆꢇ ꢈ
ꢉꢊꢋꢌ ꢂꢍꢎ
ꢏꢐ ꢎ
ꢑꢀ ꢏꢊꢁꢌ
ꢒꢀ ꢏ
ꢃꢀ ꢏꢍꢐ
ꢈꢒ ꢎ ꢂ
ꢃꢊ ꢈꢏ
ꢓ ꢏꢈ
ꢁꢒ ꢔ ꢏꢌꢐ
ꢍꢕ ꢒ
ꢖꢐꢑ ꢌꢌ ꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
7
6
5
4
3
70
60
50
40
30
20
10
0
I
T
= 0.5 A
= 25
°
C
D
J
See Figure 3
V
= 20 V
= 30 V
DD
V
DD
2
1
0
V
DD
= 48 V
V
DD
= 10 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Q
− Gate Charge − nC
g
Figure 13
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
200
175
150
125
V
V
= 48 V
= 0
= 0.5 A
DS
GS
I
T
S
J
= 25
°
C
See Figure 1
100
Z2 and Z4
75
50
25
Z1 and Z3
0
100
200
300
400
500
600
700
Reverse di/dt − A/
µ
s
Figure 14
9
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ꢀ ꢁꢂ ꢃ
ꢄ ꢅ ꢆꢇ ꢈ
ꢉ ꢊꢋ ꢌꢂ
ꢍ ꢎꢏ
ꢐ ꢎꢑꢀꢏ
ꢊꢁ ꢌꢒ
ꢀꢏ ꢃ
ꢀꢏ ꢍꢐ
ꢈꢒ ꢎ ꢂꢃꢊ
ꢈ ꢏꢓꢏꢈ
ꢁꢒꢔ ꢏꢌ
ꢐꢍ ꢕꢒ
ꢖꢐꢑꢌ ꢌꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
T
C
= 25
°
C
†
1
µ
s
†
10 ms
†
1 ms
†
500
µ
s
1
DW Pkg
NE Pkg
DC Conditions
1
0.1
0.1
10
100
V
− Drain-to-Source Voltage − V
DS
Less than 2% duty cycle
†
Figure 15
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
See Figure 4
T
C
= 25
°
C
T
C
= 125
°
C
1
0.01
0.1
1
10
100
t
− Time Duration of Avalanche − ms
av
Figure 16
10
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ꢀ ꢁ
ꢂꢃ ꢄꢅ
ꢆꢇ ꢈ
ꢉꢊꢋꢌ ꢂꢍꢎ
ꢏꢐ ꢎ
ꢑꢀ ꢏꢊꢁꢌ
ꢒꢀ ꢏ
ꢃꢀ ꢏꢍꢐ
ꢈꢒ ꢎ ꢂ
ꢃꢊ ꢈꢏ
ꢓ ꢏꢈ
ꢁꢒ ꢔ ꢏꢌꢐ
ꢍꢕ ꢒ
ꢖꢐꢑ ꢌꢌ ꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
†
NE PACKAGE
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
DC Conditions
d = 0.5
1
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
t
c
t
w
I
D
0
0.0001
0.0001
0.001
0.01
0.1
1
10
t
− Pulse Duration − s
w
†
Device mounted on FR4 printed-circuit board with no heatsink.
NOTES A:
(t) = r(t) R
Z
θ
JA
θ
JA
t
= pulse duration
= cycle time
w
t
c
d = duty cycle = t
/t
w c
Figure 17
11
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ꢀ ꢁꢂ ꢃ
ꢄ ꢅ ꢆꢇ ꢈ
ꢉ ꢊꢋ ꢌꢂ
ꢍ ꢎꢏ
ꢐ ꢎꢑꢀꢏ
ꢊꢁ ꢌꢒ
ꢀꢏ ꢃ
ꢀꢏ ꢍꢐ
ꢈꢒ ꢎ ꢂꢃꢊ
ꢈ ꢏꢓꢏꢈ
ꢁꢒꢔ ꢏꢌ
ꢐꢍ ꢕꢒ
ꢖꢐꢑꢌ ꢌꢑꢗ
ꢘ
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
†
DW PACKAGE
JUNCTIO
N
–
T
O
–
BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
DC Conditions
d = 0.5
d = 0.2
d = 0.1
d = 0.05
10
d = 0.02
d = 0.01
1
Single Pulse
t
c
t
w
I
D
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
t
− Pulse Duration − s
w
†
2
Device mounted on a 24 in
, 4-layer
FR4 printed-circuit board with no heatsink.
NOTES A:
(t) = r(t) R
Z
θ
JB
θ
JB
t
= pulse duration
= cycle time
w
t
c
d = duty cycle = t
/t
w c
Figure 18
12
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PACKAGE OPTION ADDENDUM
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Package
Pins Package
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Qty
Type
SOIC
PDIP
Drawing
TPIC5421LDW
TPIC5421LNE
OBSOLETE
OBSOLETE
DW
20
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
NE
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan
–
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
–
please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. — The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
M
E
CHANICAL DATA
MPDI003 – OCTOBER 1994
NE (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
20 PIN SHOWN
0.070 (1,78) MAX
11
20
PINS **
16
20
DIM
0.914 (23,22)
MIN
A
C
0.780 (19,80)
0.975 (24,77)
0.930 (23,62)
MAX
MIN
B
C
1.000 (25,40)
MAX
1
10
MIN
0.240 (6,10)
0.260 (6,61)
0.280 (7,11)
MAX 0.260
(6,60)
0.020 (0,51) MIN
0.200 (5,08) MAX
A
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25)
M
0.310 (7,87)
B
0.020 (0,51) MIN
0.290 (7,37)
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0
°
–
1
5
°
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25)
M
0.010 (0,25) NOM
404005
4
/B
0
4/95
NOTES: A. All
linear dimensions are in inches (millimeters).
B. This
drawing is subject to change without notice.
C. Falls
within JEDEC MS-001 (16 pin only)
1
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PACKAGE OUTLINE
DW0020A
SOIC – 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 –
8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
EXAMPLE BOARD LAYOUT
DW0020A
SOIC – 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
DW0020A
SOIC – 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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