Texas-Instruments-TRF6903PTR

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

D

Single-Chip RF Transceiver for 315-MHz,  

433-MHz, 868-MHz, and 915-MHz Industrial,  

Scientific, and Medical (ISM) Bands  

D

D

Clock Recovery With Integrated Data Bit  

Synchronizer and Baud Rate Selection  

Linear Receive Strength Signal Indicator  

(RSSI)  

D

D

D

D

D

D

D

2.2-V to 3.6-V Operation  

Low Power Consumption  

FSK/OOK Operation  

D

Flexible 3-Wire Serial Interface  

D

Minimal Number of External Components  

Required  

Integer-N Synthesizer With Fully Integrated  

Voltage Controlled Oscillator (VCO)  

D

D

D

D

48-Pin Low-Profile Plastic Quad Flat  

Package (PQFP)  

On-Chip Reference Oscillator and  

Phase-Locked Loop (PLL)  

Programmable XTAL Trimming  

Lock Detect Indicator  

Power Amplifier With 8-dBm Typical Output  

Power  

Programmable Training Sequence  

Recognition  

Programmable Brownout Detector  

D

Pin Compatible to the TRF6901  

10.7 MHz Ceramic  

or Discrete IF Filter  

Ceramic  

Discriminator  

33  

RX_DATA  

27  

DCLK  

41  

RSSI_OUT  

1

23  

LNA_IN1  

LNA_IN2  

RX_FLAG  

2

18  

TRF6903  

CLOCK  

45  

20  

DATA  

DET_OUT  

19  

STROBE  

26  

STDBY  

4

PA_OUT  

21  

MODE  

22  

LOCK_DETECT  

32  

TX_DATA  

13 15  

30  

31  

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  

during storage or handling to prevent electrostatic damage to the gates.  

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  

T

e

xas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  

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Copyright



2005,

T

e

xas Instruments Incorporated  

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1

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PQFP PACKAGE  

(TOP VIEW)  

48 47 46 45 44 43 42 41 40 39 38 37  

LNA_IN1  

LNA_IN2  

LPF_OUT  

CER_DIS  

SLC_CAP  

RX_DATA  

TX_DATA  

XTAL_SW  

XTAL  

36  

35  

34  

33  

32  

31  

30  

29  

28  

27  

26  

25  

1

2

LNA_VCC  

PA_OUT  

3

4

PA_GND1  

PA_VCC  

5

6

PA_GND2  

VCO_GND1  

VCO_VCC  

VCO_VCC2  

VCO_BYPASS  

VCO_GND2  

7

8

XTAL_VCC  

DGND  

9

10  

11  

12  

DCLK  

STDBY  

NC  

13 14 15 16 17 18 19 20 21 22 23 24  

description  

The TRF6903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK  

transceiver to establish a frequency-programmable, half-duplex, bidirectional RF link. The multichannel  

transceiver is intended for digital (FSK, OOK) modulated applications in the North American and European  

315-MHz, 433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip transceiver operates down to 2.2 V  

and is designed for low power consumption. The synthesizer has a typical channel spacing of better than  

200 kHz and features a fully-integrated VCO. Only the PLL loop filter is external to the device.  

Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two  

preprogrammed settings (for example,

 

receive (RX)/transmit (TX); TX_frequency_0/TX_frequency_1;  

RX_frequency_0/RX_frequency_1;

…

) without reprogramming the device.  

ISM band standards  

Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined  

for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency  

band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible.  

The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz), and is  

suitable for short range RF links.  

2

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

transmitter  

The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power  

amplifier. The dividers, prescaler, and reference oscillator require only the addition of an external crystal and  

a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz.  

Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is  

necessary in most applications.  

Four attenuation settings for the power amplifier are offered. This feature allows the user to fine tune the  

amplifier for optimal output power.  

receiver  

The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of a low  

noise amplifier, mixer, limiter, FM/FSK demodulator with an external LC tank circuit or ceramic resonator, LPF  

amplifier, and a data slicer with clock recovery and an integrated data bit synchronizer. The received strength  

signal indicator (RSSI) can also be used for fast carrier sense on/off keying, or amplitude shift keying,  

(OOK/ASK) demodulator.  

baseband interface  

The TRF6903 can easily be interfaced to a baseband processor such as the

T

e

xas Instruments MSP430  

ultralow-power microcontroller (see Figure 1). The TRF6903 serial control registers are programmed by the  

MSP430 and the MSP430 performs baseband operations in the software.  

A synchronized data clock, programmable for most common data rates, is provided by the TRF6903. This  

feature reduces the need for extensive oversampling and data decision in the microcontroller during receive.  

During transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF6903  

at predefined data rates.  

Microcontroller  

Antenna  

Section  

RF Section  

RSSI_OUT  

RSSI Out (Analog Signal)  

Transmit Data  

TX_DATA  

RX_DATA  

Receive Data  

RF In  

LNA_IN1, 2  

PA_OUT  

Data Clock  

DCLK  

Learn/Hold Select  

RF Out  

LEARN/HOLD  

Mode Select  

Standby  

MODE  

STDBY  

TRF6903  

Transceiver  

+

MSP430  

Family

µ

C  

Brownout Detector Out  

DET_OUT  

Discretes  

Serial Control Data  

Serial Control Clock  

Serial Control Strobe  

DATA  

CLOCK  

STROBE  

Lock Detect Out  

LOCK_DETECT  

RX_FLAG  

Receive Data Flag  

Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

functional block diagram  

Ceramic  

Discriminator  

10.7-MHz Ceramic  

or Discrete IF FIlter  

47  

44, 43  

Limiter  

35  

37  

36 39  

34  

LPF Amplifier  

Mixer  

LNA_IN1, LNA_IN2  

RF  

IN  

LNA  

1, 2  

Data Slicer  

Quadrature  

33  

27  

Demodulator  

Bit Synchronizer  

and  

Data Clock  

RX_DATA  

DCLK  

OOK  

Switch  

41  

23  

RSSI  

RSSI_OUT  

RX_FLAG  

Band-gap  

8

18  

20  

19  

26  

21  

/A-  

Counter  

CLOCK  

/Div. CTRL  

Serial  

6

DATA  

STROBE  

Interface  

45  

STDBY  

MODE  

Brownout  

Detector  

/N Prescaler  

32/33  

DET_OUT  

/B-  

Counter  

22  

Lock  

Detect  

LOCK_DETECT  

Output  

Divider  

1, 2, 3  

4

PFD  

CPs  

PA_OUT  

PA  

/Ref  

2…255  

32  

TX_DATA  

XTAL  

Switch  

VCO  

30  

31  

VCO_TUNE 13  

15 CP_OUT  

Loop Filter  

Terminal Functions  

TERMINAL  

I/O  

DESCRIPTION  

NAME  

NO.  

35  

18  

14  

15  

16  

20  

CER_DIS  

CLOCK  

CP_GND  

CP_OUT  

CP_VCC  

DATA  

Connect to external ceramic discriminator  

Serial interface clock signal input  

Charge pump ground  

I

O

I

Charge pump output  

Charge pump supply voltage  

Serial interface data signal input  

4

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

Terminal Functions (Continued)  

TERMINAL  

I/O  

O

DESCRIPTION  

NAME  

DCLK  

NO.  

27  

38  

40  

45  

28  

17  

42  

44  

43  

39  

1

Data clock output  

DEM_GND  

DEM_VCC  

DET_OUT  

DGND  

Demodulator ground  

Demodulator supply voltage  

Brownout detector output; active high  

Digital ground  

O

DVDD  

Digital power supply  

GND  

Substrate ground  

IF_IN1  

I

I

I

I

I

Limiter amplifier noninverting input  

Limiter amplifier inverting input  

IF_IN2  

LEARN/HOLD  

LNA_IN1  

LNA_IN2  

LNA_VCC  

LOCK_DETECT  

LPF_IN  

Data slicer switch. Controls data slicer reference level  

LNA noninverting input  

LNA inverting input  

2

3

LNA power supply  

22  

37  

36  

46  

47  

48  

21  

24, 25  

5

O

I

PLL lock detect signal, active high  

Low-pass filter amplifier input  

Low-pass filter amplifier output  

Mixer ground  

LPF_OUT  

MIX_GND  

MIX_OUT  

MIX_VCC  

MODE  

O

O

I

Mixer output  

Mixer supply voltage  

Mode select input  

NC  

No connect  

PA_GND1  

PA_GND2  

PA_OUT  

PA_VCC  

RSSI_OUT  

RX_DATA  

RX_FLAG  

SLC_CAP  

STDBY  

Power amplifier ground  

Power amplifier ground  

Power amplifier output  

7

4

O

6

Power amplifier supply voltage  

RSSI output signal  

41  

33  

23  

34  

26  

19  

32  

O

O

O

I/O  

I

Demodulated digital (FSK or OOK) RX data  

Receive data flag  

External capacitor for data slicer  

Standby input signal; active low  

Serial interface strobe signal  

Buffered TX data input  

STROBE  

TX_DATA  

I

I

VCO_BYPASS  

VCO_GND1  

VCO_GND2  

VCO_TUNE  

VCO_VCC  

VCO_VCC2  

XTAL  

11  

8

I

VCO bypass; connect to ground through a 100-pF capacitor  

VCO ground  

12  

13  

9

VCO ground  

I

Tuning voltage for the integrated VCO  

VCO supply voltage  

10  

30  

31  

29  

VCO core supply voltage  

I/O  

I

Connection to an external crystal reference  

Connecting to external capacitor, which sets the frequency deviation of the transmitted signal  

Oscillator supply voltage  

XTAL_SW  

XTAL_VCC  

5

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)  

Supply voltage range

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

−0.6 to 4.5 Vdc  

Input voltage, logic signals

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

−0.6 to 4.5 Vdc  

Storage temperature range, T  

ESD protection, human body model (HBM)

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

2 kV  

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

− 65

°

C to 150

°

C  

stg  

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  

recommended operating conditions  

PARAMETER  

Analog supply voltage  

TEST CONDITIONS  

MIN  

2.2  

TYP  

MAX  

3.6  

3.6  

85  

UNIT  

V

Digital supply voltage  

2.2  

V

Operating free-air temperature  

−

4

0  

°

C  

dc electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C  

A

CC  

supply current  

PARAMETER  

TEST CONDITIONS  

STDBY low  

MIN  

TYP  

0.6  

12  

11  

MAX  

4

UNIT  

Standby current  

µ

A  

315-MHz band  

433-MHz band  

868-MHz band  

915-MHz band  

315-MHz band  

433-MHz band  

868-MHz band  

915-MHz band  

315-MHz band  

433-MHz band  

868-MHz band  

15  

14  

12  

12  

26  

25  

23  

23  

26  

25  

23  

RX current, receive chain inactive. Bit synchronizer and data clock  

inactive. PLL, VCO, dividers, and reference active  

mA  

mA  

mA  

10  

10  

20  

19  

18  

18  

20  

19  

18  

RX current, receive chain active. PLL, VCO, dividers, and reference  

active. Bit synchronizer and data clock inactive  

RX current, receive chain active. PLL, VCO, dividers, and reference  

active. Bit synchronizer and data clock active  

915-MHz band  

18  

23  

6

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

dc electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C (continued)  

A

CC  

supply current (continued)  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

12  

MAX  

15  

UNIT  

315-MHz band  

433-MHz band  

868-MHz band  

915-MHz band  

11  

14  

TX current, PA disabled. PLL, VCO, dividers, and reference active  

mA  

10  

12  

10  

12  

0-dB attenuation  

10-dB attenuation  

20-dB attenuation  

0-dB attenuation  

10-dB attenuation  

315-MHz band  

315-MHz band  

315-MHz band  

433-MHz band  

433-MHz band  

433-MHz band  

868-MHz band  

868-MHz band  

868-MHz band  

915-MHz band  

915-MHz band  

915-MHz band  

37  

30  

29  

36  

29  

28  

35  

28  

27  

35  

28  

27  

43  

42  

40  

40  

20-dB attenuation  

0-dB attenuation  

10-dB attenuation  

20-dB attenuation  

0-dB attenuation  

10-dB attenuation  

20-dB attenuation  

‡

TX current

 

, PA enabled. PLL, VCO, dividers,  

mA  

reference, and data clock active  

‡

The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the  

highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other  

attenuation settings alters the typical current consumption from the typical values noted.  

digital interface  

PARAMETER  

High-level input voltage  

TEST CONDITIONS  

MIN  

−0.4  

TYP MAX  

UNIT  

V

V

V

V

V

V

V

V

DD  

0.4  

IH  

DD  

Low-level input voltage  

High-level output voltage  

Low-level output voltage  

Digital input leakage current  

0

V

IL  

I

I

= 0.5 mA  

= 0.5 mA  

−0.4  

DD  

V

OH  

OL  

OH  

0.4  

V

OL  

<0.01  

µ

A  

ac electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C  

A

CC  

receiver (LNA, mixer, limiter, demod, LPF amplifier, data slicer, VCO, and PLL)  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

MAX  

UNIT  

RX wake-up time  

BER, FSK  

1

ms  

315 MHz, 433 MHz,  

868 MHz, 915 MHz,  

IF = 10.7 MHz, BW = 280 kHz  

FSK deviation:

 

32 kHz  

Bit rate: 19.2 kbit/s Manchester  

−3  

10  

10  

†

−

1

03 < P  

RFIN  

(dBm) <

−

3

0  

315 MHz, 433 MHz,  

868 MHz, 915 MHz,  

IF = 10.7 MHz, BW = 280 kHz  

ON-OFF ratio: 50 dB  

−3  

BER, OOK  

‡

Bit rate: 9.6 kbit/s Manchester  

−

1

03 < P

 

(dBm) <

−

3

0  

RFIN  

†

‡

19.2 kbit/s Manchester is equivalent to 38.4 kbit/s NRZ.  

9.6 kbit/s Manchester is equivalent to 19.2 kbit/s NRZ.  

7

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ꢁ

SWRS022D − MARCH 2004 − REVISED JUNE 2005  

ac electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C  

A

CC  

LNA/mixer, 304−316 MHz  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

315  

21  

MAX  

UNIT  

dB  

Frequency range  

304  

316  

Conversion gain  

dB  

SSB noise figure  

Includes external matching network  

6.5  

dB  

Input 1-dB compression point  

Input IP3  

−31  

−21  

dBm  

dBm  

LNA/mixer, 430−450 MHz  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

433  

21  

MAX  

UNIT  

MHz  

dB  

Frequency range  

430  

450  

Conversion gain  

SSB noise figure  

Includes external matching network  

6.5  

dB  

Input 1-dB compression point  

Input IP3  

−31  

−21  

dBm  

dBm  

LNA/mixer, 868−870 MHz  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

869  

19  

MAX  

UNIT  

MHz  

dB  

Frequency range  

868  

870  

Conversion gain  

SSB noise figure  

Includes external matching network  

6.5  

dB  

Input 1-dB compression point  

Input IP3  

−31  

−20  

dBm  

dBm  

LNA/mixer, 902−928 MHz  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

915  

18  

MAX  

UNIT  

MHz  

dB  

Frequency range  

902  

928  

Conversion gain  

SSB noise figure  

Includes external matching network  

6.5  

dB  

Input 1-dB compression point  

Input IP3  

−31  

−19  

dBm  

dBm  

IF/limiter amplifier  

PARAMETER  

Frequency  

TEST CONDITIONS  

MIN  

TYP  

10.7  

86  

MAX  

UNIT  

MHz  

dB  

Voltage gain  

Noise figure  

IF frequency = 10.7 MHz  

4

dB  

VCO/output divider  

PARAMETER  

TEST CONDITIONS  

Low-side injection, A<1:0> = 11  

High-side injection, A<1:0> = 10  

High-side injection, A<1:0> = 01  

Low-side injection, A<1:0> = 01  

Frequency offset = 50 kHz  

MIN  

304  

430  

868  

902  

TYP  

MAX  

316  

450  

870  

928  

UNIT  

MHz  

MHz  

MHz  

MHz  

Frequency range: 315-MHz band  

Frequency range: 433-MHz band  

Frequency range: 868-MHz band  

Frequency range: 915-MHz band  

315  

433  

869  

915  

−

7

7  

−

9

0  

Closed loop phase noise  

Tuning voltage  

dBc/Hz  

V

Frequency offset = 200 kHz  

VCC at  

terminal 10  

0.1  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

ac electrical characteristics, V  

RSSI  

= 2.7

V

, T

 

=

2

5

°

C (continued)  

A

CC  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

70  

2

MAX  

UNIT  

dB  

Dynamic range  

Rise time  

Slope  

R

R

= 100 k

Ω,

C =

 

10 pF  

4

µ

s  

L

L

L

20  

mV/dB  

RSSI output current  

= 100 k

Ω,

C =

 

10 pF  

30  

µ

A  

L

impedances and loads  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

MAX  

UNIT  

LNA_IN  

See Figure 4  

1400  

{

MIX_OUT  

Ω

Ω

{

IF_IN  

Differential  

2600  

See  

Figure 10  

PA_OUT  

†

Does not include external matching network.  

transmitter (XTAL, PLL, VCO, and PA), 315-MHz band  

PARAMETER  

TEST CONDITIONS  

A<1:0> = 11  

0-dB attenuation  

MIN  

TYP  

315  

8

MAX  

UNIT  

TX frequency range  

304  

316  

MHz  

10-dB attenuation  

20-dB attenuation  

Disabled, B<3> =

 

0  

−2  

†

−12  

−

8

0  

−80  

−25  

−30  

ꢀ

32  

75  

Output power  

dBm  

‡

Off  

Second harmonic  

Third harmonic  

dBc  

dBc  

kHz  

dB  

§

Frequency deviation  

FSK  

Power ON-OFF ratio  

OOK, 0-dB mode  

FSK  

64  

Maximum data rate (NRZ)  

kbit/s  

OOK  

32  

†

‡

§

Matched to 50

Ω

using external matching network.  

Not selectable with PA attenuation bits A

<

7:6

>

, B

<

7:6

>

, or with B<3>. Measured while the TRF6903 device is in RX mode.  

Dependent upon external circuitry.  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

ac electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C (continued)  

A

CC  

transmitter (XTAL, PLL, VCO, and PA), 433-MHz band  

PARAMETER  

TEST CONDITIONS  

A<1:0> = 10  

0-dB attenuation  

MIN  

TYP  

433  

8

MAX  

UNIT  

TX frequency range  

430  

450  

MHz  

10-dB attenuation  

20-dB attenuation  

Disabled, B<3> =

 

0  

−2  

†

−12  

−

8

0  

−80  

−25  

−30  

ꢀ

32  

75  

Output power  

dBm  

‡

Off  

Second harmonic  

Third harmonic  

dBc  

dBc  

kHz  

dB  

§

Frequency deviation  

FSK  

Power ON-OFF ratio  

OOK, 0-dB mode  

FSK  

64  

Maximum data rate (NRZ)  

kbit/s  

OOK  

32  

†

‡

§

Matched to 50

Ω

using external matching network.  

Not selectable with PA attenuation bits A

<

7:6

>

, B

<

7:6

>

, or with B<3>. Measured while the TRF6903 device is in RX mode.  

Dependent upon external circuitry.  

transmitter (XTAL, PLL, VCO, and PA), 868-MHz band  

PARAMETER  

TEST CONDITIONS  

A<1:0> = 11  

0-dB attenuation  

MIN  

TYP  

869  

8

MAX  

UNIT  

TX frequency range  

868  

870  

MHz  

10-dB attenuation  

20-dB attenuation  

Disabled, B<3> =

 

0  

−2  

†

−12  

−

8

0  

−80  

−25  

−30  

ꢀ

32  

75  

Output power  

dBm  

‡

Off  

Second harmonic  

Third harmonic  

dBc  

dBc  

kHz  

dB  

§

Frequency deviation  

FSK  

Power ON-OFF ratio  

OOK, 0-dB mode  

FSK  

64  

Maximum data rate (NRZ)  

kbit/s  

OOK  

32  

†

‡

§

Matched to 50

Ω

using external matching network.  

Not selectable with PA attenuation bits A

<

7:6

>

, B

<

7:6

>

, or with B<3>. Measured while the TRF6903 device is in RX mode.  

Dependent upon external circuitry.  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

ac electrical characteristics, V  

= 2.7

V

, T

 

=

2

5

°

C (continued)  

A

CC  

transmitter (XTAL, PLL, VCO, and PA), 915-MHz band  

PARAMETER  

TEST CONDITIONS  

A<1:0> = 11  

0-dB attenuation  

MIN  

TYP  

915  

8

MAX  

UNIT  

TX frequency range  

902  

928  

MHz  

10-dB attenuation  

20-dB attenuation  

Disabled, B<3> =

 

0  

−2  

†

−12  

−

8

0  

−80  

−25  

−30  

32  

Output power  

dBm  

‡

Off  

Second harmonic  

Third harmonic  

dBc  

dBc  

kHz  

dB  

§

Frequency deviation  

FSK  

Power ON-OFF ratio  

OOK, 0-dB mode  

FSK  

75  

64  

Maximum data rate (NRZ)  

kbit/s  

OOK  

32  

†

‡

§

Matched to 50

Ω

using external matching network.  

Not selectable with PA attenuation bits A

<

7:6

>

, B

<

7:6

>

, or with B<3>. Measured while the TRF6903 device is in RX mode.  

Dependent upon external circuitry.  

XTAL  

PARAMETER  

TEST CONDITIONS  

MIN  

TYP  

TYP  

MAX  

UNIT  

Frequency range  

9.5  

20  

MHz  

brownout detector  

PARAMETER  

TEST CONDITIONS  

MIN  

MAX  

UNIT  

V

Voltage threshold, V  

Voltage steps (

∆

V)  

Number of steps  

Output level  

Set by B<2:1>  

2.2  

2.8  

det  

200  

4

mV  

Connected to typical input port of microcontroller  

CMOS  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

timing data for serial interface  

PARAMETER  

Clock frequency  

MIN  

TYP  

MAX  

UNIT  

MHz  

ns  

f

t

t

t

t

t

t

t

20  

(CLOCK)  

w(CLKHI)  

w(CLKLO)  

su(D)  

Clock high-time pulse width, clock high  

Clock low-time pulse width, clock low  

20  

20  

0

ns  

Setup time, data valid before CLOCK

↑  

Hold time, data valid after CLOCK

↑  

ns  

10  

20  

20  

20  

ns  

h(D)  

Delay time of CLOCK low before STROBE high  

STROBE high-time pulse width, STROBE high  

STROBE low-time pulse width, STROBE low  

ns  

d(CLKLO)  

w(STROBEHI)  

w(STROBELO)  

ns  

ns  

Data  

Change  

Data  

Valid  

−V  

H

MSB  

MSB  

LSB  

DATA  

−V  

L

Start of  

t

t

t

w(CLKHI)  

Next Word  

su(D)  

h(D)  

t

d(CLKLO)  

t

−V  

CLOCK  

H

−V  

L

w(STROBEHI)  

t

w(CLKLO)  

t

w(STROBELOW)  

t

r

t

STROBE  

f

−V  

H

Clock Disabled  

−V  

L

Shift in Data  

Clock Enabled  

Note: Most significant bit (MSB) clocked in first to the synthesizer.  

Store Data  

Strobe Enabled  

Figure 2. Timing Data for Serial Interface  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

timing data for DCLK, TX_DATA, RX_FLAG, and RX_DATA  

PARAMETER  

MIN  

TYP  

MAX  

UNIT  

t

t

t

t

t

t

Delay time, rising edge of DCLK to transition of RX_DATA  

3

ns  

d(DG)  

{

Setup time, RX_DATA valid before DCLK

↑  

Hold time, RX_DATA valid after DCLK

↑  

Delay time, rising edge of RX_FLAG before DCLK

↑  

Setup time, TX_DATA valid before DCLK

↑  

Hold time, TX_DATA valid after DCLK

↑  

0.4/f  

su(r)  

c

{

0.4/f  

h(r)  

c

2

ns  

ns  

ns  

d(FK)  

su(TX)  

100  

100  

h(TX)  

†

After clock recovered  

Receive Deglitch Mode  

RX_DATA  

Output  

t

d(DG)  

DCLK  

Output  

1

T

DGK  

=

f

DG  

t

Receive Clock Recovery Mode or Self Train Mode  

su(r)  

RX_DATA  

Output  

t

h(r)  

DCLK  

Output  

T

CRK  

t

d(FK)  

RX_FLAG  

Output  

(Valid Only in  

Self Train Mode)  

t

= T  

CRK  

RXF  

0.87  

1.13  

≤

T  

CRK  

≤

f

f

c

c

NOTE: RX_DATA

 

is latched at the falling edge of DCLK.  

Transmit  

t

t

h(TX)  

su(TX)  

TX_DATA  

Input  

DCLK  

Output  

1

T

SK  

=

f

c

NOTE: TX_DATA

 

is latched at the rising edge of DCLK.  

Figure 3. Timing Data for DCLK, TX_DATA, RX_FLAG, and RX_DATA  

It can be seen from the timing diagram that in the clock recovery or self train mode, the data transitions  

(high-to-low or low-to-high) on the RXDATA pin are timed to coincide with the falling edge of DCLK. Any  

microcontroller using the TRF6903 can then latch RXDATA on the rising edge of DCLK. For more details, see  

the

data clock

section.  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

timing data for DCLK, TX_DATA, RX_FLAG, and RX_DATA (continued)  

In high data rate systems (> 38K bps), designers need to be aware of the latency between the rising edge of  

DCLK and the time the RXDATA logic value is sampled by the microcontroller. This latency needs to be less  

than half the RXDATA pulse width to prevent bit errors.  

If transmit capture mode is selected (by setting bit 13 in word E), the data transitions (high-to-low or low-to-high)  

on the TXDATA pin are timed to coincide with the falling edge of DCLK. Any microcontroller using the TRF6903  

can then latch TXDATA on the rising edge of DCLK. For more details, see the

data clock

section.  

low-noise amplifier (LNA)/RF mixer  

The LNA has differential inputs. The off-chip input matching network has the dual task of matching a 50-

Ω  

connector (or antenna, switch, filter, etc.) to the differential inputs and providing a 180-degree phase shift  

between the inputs at terminals 1 and 2. The differential input impedance of the LNA is approximately 500

Ω  

in parallel with 0.7 p

F

.

T

he predicted noise figure of the LNA and input matching circuit is 2.5 dB. The cascaded  

noise figure for the LNA/mixer is listed in the specifications.  

The mixer offers good linearity (high IP3). An external matching network is required to transform the output  

impedance of the mixer (1.4 k

Ω

) to the input impedance of the IF filter (typically 330

Ω

).  

↑

1  

U

CH1 S11  

1

0.5  

2

5

CAL  

OFS  

0

0.2  

0.5  

1

2

5

10  

CPL  

−5  

FIL  

1k  

−0.5  

−2  

−1  

START 300

 

MHz  

STOP 1000

 

MHz  

Figure 4. Typical LNA Input Impedance (S11) at Device Terminals LNA_IN1,2  

IF amplifier/limiter  

The IF amplifier has differential inputs to its first stage. The limiting amplifier provides 68 dB of gain. An external  

impedance matching network is required between the IF filter output at terminal 47 and the IF amplifier inputs  

at terminals 43 and 44.  

RSSI  

The received signal strength indicator (RSSI) voltage at terminal 41 is proportional to the log of the  

down-converted RF signal at the IF limiting amplifier input. The RSSI circuit is temperature compensated. It is  

useful for detecting interfering signals, transceiver handshaking, and RF channel selection. In some  

applications, the RSSI circuitry alone can be used as a demodulator for amplitude-shift keying (ASK) or on-off  

keying (OOK) modulation with an output at the RSSI_OUT terminal. In OOK mode, the received signal is also  

fed from the RSSI circuitry to the input of the post-detection LPF amplifier. In this mode, received data is output  

at the RX_DATA terminal according to the RXM field.  

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demodulator  

The quadrature demodulator decodes digital frequency shift keying (FSK) modulation. An external ceramic  

discriminator or an equivalent discrete circuit is required at terminal 35. The demodulator is optimized for use  

with a ceramic discriminator. Thus, the use of a packaged ceramic discriminator is recommended for best  

performance. Internal resistors can be programmed with D<14:12> to tune the demodulator center frequency.  

The recommended default setting for the demodulator tuning bits is D<14:12> = 110. The resonant frequency  

of the discrete-component discriminator can be calculated from the inductor and capacitor values used in the  

circuit. A parallel resistor may be added to reduce the quality factor (Q) of the tank circuit, depending on the  

application.  

When OOK modulation is selected, the received signal from the RSSI circuitry is connected directly to the  

post-detection LPF amplifier, therefore bypassing the quadrature demodulator.  

1

ƒ

res  

+

Ǹ

2

p

LC  

External Tank  

35  

L

R

C

Figure 5. Optional External Discrete Demodulator Tank  

post-detection amplifier/low-pass filter  

The post-detection amplifier operates as a low-pass transimpedance amplifier. The external low-pass filter  

circuit must be optimized for the data rate. The 3-dB corner frequency of the low-pass filter should be greater  

than twice the data rate. Various low-pass filter designs use two to five components and may be first- or  

second-order designs. Simple 2-element filter component values and 3-dB bandwidths are contained in

T

a

ble 1.  

1

f

+

3dB  

2

p

R2(C2

)

 

C1)  

R2  

C2  

External Low-Pass Filter  

37  

36  

C1  

2 pF  

Internal Low-Pass Amplifier  

Figure 6. Post-Detection Amplifier/Low-Pass Filter  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

post-detection amplifier/low-pass filter (continued)  

Table 1. Various Post-Detection Amplifier/Low-Pass Filter  

3-dB Bandwidth and Corresponding Component Values for FSK Operation  

f

(kHz)  

10  

220  

68  

20  

220  

33  

30  

220  

22  

60  

220  

10  

3dB  

R2 (k

Ω

)  

C2 (pF)  

NOTE: For

 

OOK operation, it is recommended that R2 be set to 27 k

Ω

and C2 is not placed.  

data slicer and bit synchronizer  

The data slicer is a comparator circuit for received digital (FSK and OOK) data. The data slicer output voltage  

depends on the difference between the received signal and a reference voltage (at the sample-and-hold (S&H)  

capacitor) used as a decision threshold. During the learn mode, the S&H capacitor connected to terminal 34  

is charged up to the average dc voltage of a training sequence of alternating ones and zeroes; this establishes  

the reference voltage to be used as a decision level before a sequence of actual data is received in the hold  

mode. During long data transmissions, more training sequences may be necessary to recharge the S&H  

capacitor.  

If the modulation scheme is dc-free (Manchester coding) or constant-dc, the TRF6903 may be operated  

continuously in the learn mode and no training sequence is necessary before the transmission of a data string.  

However, the S&H capacitor voltage may be incorrect during power up or after long periods of inactivity (no data  

transmission); a learning sequence before each data transmission is recommended.  

The comparator is a CMOS circuit that does not load the S&H capacitor. Leaving the transmission gate  

(LEARN/HOLD switch) open (in hold mode) during periods of inactivity, such as during standby, may be useful  

in maintaining the capacitor reference voltage. However, the reference voltage gradually discharges over time  

due to leakage current.  

The time constant for charging the S&H capacitor is determined by its capacitance and an internal 51-k

Ω  

resistor. A slow data rate requires a larger S&H capacitor (longer time constant). The value of the S&H capacitor,  

Csh, can be calculated with the following equation:  

Number of training Bits  

5

 

 

51k

 

 

Data Rate (Hz)  

S & H Cap

+

 

; Farad  

Where the data rate in Hz is the fundamental frequency (in Hz) of the base band waveform.  

Low-Pass Amplifier  

LPF Out  

33  

Bit Synchronizer  

and  

Data Clock  

27  

23  

Comparator  

51 k

Ω  

39  

34  

{

Csh  

LEARN/HOLD  

{

External Sample-and-Hold Capacitor  

Figure 7. Data Slicer and Bit Synchronizer  

The received data and data clock output modes are determined by field RXM according to

T

a

ble 3. When RXM,  

E<15:14> is set to 00, the raw data from the data slicer is output at terminal 33, RX_DATA. No synchronization  

or data recovery is performed and the receiver can be used in an asynchronous mode. When RXM, E<15:14>,  

is set to 01, received data is first passed through a deglitching filter. These modes are useful for the reception  

of data whose baud rate is nonstandard.  

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data slicer and bit synchronizer (continued)  

When RXM is set to enable recovered data, RXM E<15:14> = 10 or 11, the integrated bit synchronizer  

determines the preprogrammed data rate as determined by the crystal frequency and the values of D1, D2, and  

D3, and performs data recovery. Glitch-free, recovered data is then output at terminal 33, RX_DATA, and the  

corresponding data clock is output at

 

terminal 27, DCLK.  

The preprogrammed bit rate can be calculated based on the following equation:  

F

crystal frequency (kHz)  

x

Bit rate (kbps)

+

 

+

+

 

f (kHz)  

c

D1

 

 

D2

 

 

D3  

D1

 

 

D2

 

 

D3  

where  

D1 = 1, 5, 6, or 8  

D2 = 1, 2, 4, 8, 16, 32, 64, or 128  

D3 = 15 or 16  

data clock  

When enabled, RXM = 10 or 11, the data clock circuitry provides as an output at terminal 27, DCLK, a data clock  

based on a programmable bit rate. The bit rate is programmable via variables D1, D2, and D3 and is always  

relative to the master clock (XTAL) frequency, F

 

.

T

a

ble 2 shows common bit rates (kbps) vs selected crystal  

x

frequencies (MHz) and the respective settings of D1, D2, and D3.  

Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3  

D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ)  

BIT RATE  

(kbps)  

9.8304  

12.288  

14.7456  

15.72864  

8x128x15  

8x64x15  

8x32x15  

8x16x15  

8x8x15  

16.384  

19.6608  

0.6  

0.9  

8x128x16  

8x128x16  

1

6x128x16  

5x128x16  

6x64x16  

5x64x16  

6x32x16  

5x32x16  

6x16x16  

5x16x16  

6x8x16  

8x128x16  

1.024  

1.2  

5x128x15  

8x64x16  

6x128x16  

8x64x16  

8x128x16  

1.8  

2

8x64x16  

8x32x16  

8x16x16  

8x8x16  

8x4x16  

8x2x16  

2.048  

2.4  

5x64x15  

8x32x16  

5x128x15  

8x64x16  

6x64x16  

8x32x16  

3.6  

4

4.096  

4.8  

5x32x15  

8x16x16  

5x64x15  

8x32x16  

6x32x16  

8x16x16  

7.2  

8

8.192  

9.6  

5x16x15  

8x8x16  

5x32x15  

8x16x16  

6x16x16  

8x8x16  

14.4  

16  

16.384  

19.2  

28.8  

32  

5x8x15  

8x4x16  

5x16x15  

8x8x16  

5x8x16  

6x8x16  

8x4x16  

6x4x16  

32.768  

38.4  

57.6  

64  

5x4x15  

8x2x16  

8x4x15  

5x8x15  

8x4x16  

5x4x16  

6×4 x16  

8x2x16  

6x2x16  

65.536  

5x2x15  

8x2x15  

5x4x15  

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data clock (continued)  

Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of  

D1, D2, and D3 (continued)  

D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ)  

BIT RATE  

(kbps)  

9.8304  

12.288  

14.7456  

6x2x16  

8x1x16  

15.72864  

16.384  

19.6608  

76.8  

115.2  

128  

8x1x16  

5x2x16  

8x2x16  

6x1x16  

8x1x16  

There are several receive modes, from raw slicer output to clock recovery and training sequence recognition.  

The receive logic is controlled by the RXM, TWO, and TCOUNT fields. The RXM, E<15:14>, field determines  

the receive mode as indicated in

T

a

ble 3. These modes are described in more detail below.  

Table 3. Clock Recovery and Receive Data Modes Selected by RXM  

RXM  

RECEIVE MODE  

RX_DATA  

DCLK  

RX_FLAG  

00  

Raw data  

Data direct from data

 

Inactive; held low  

slicer  

Inactive; held low  

01  

10  

Deglitch  

Deglitched data  

Active; clock  

synchronous to  

deglitched data  

Inactive; held low  

Inactive; held low  

Clock recovery  

Deglitched data;  

synchronous to  

bit-rate clock at  

DCLK  

Active; synchronous  

bit-rate clock  

11  

Self train  

Deglitched data;  

synchronous to  

bit-rate clock at  

DCLK  

Active; synchronous  

bit-rate clock  

Active; set high at  

first received bit that  

is not part of a  

predetermined  

training sequence  

In

Raw Data

mode, the data slicer output is fed directly to the RX_DATA terminal, and the DCLK and RX_FLAG  

terminals are held low.  

In

Deglitch

mode, the data slicer output is passed through the internal deglitch filter. This filter samples the slicer  

output at a rate f

 

, where  

DG  

F

x

D1

 

 

D2  

f

+

DG  

The filter output is high if five or more of the last seven samples were high, and low if two or less of the last seven  

samples were high. Otherwise, the filter holds its previous value. The deglitched data is applied to the RX_DATA  

terminal, and the over-sampled deglitch filter clock is passed on to the DCLK terminal. Data will appear on the  

RX_DATA terminal a few gate delays after the rising edge of DCLK. The RX_FLAG terminal is held low.  

In

Clock Recovery

mode, the edges of the deglitched data are used to synchronize a bit-rate clock to the data.  

As long as the consecutive number of ones or zeros in the data stream, N

 

, meets the condition:  

CB  

250000  

D

were

∆

is the error between the transmit bit rate and the receiver bit-rate clock in ppm.  

N

t

B

CB  

B

The output data is synchronous with the bit-rate clock. The deglitched data is routed to the RX_DATA terminal  

and the synchronized bit-rate clock appears at DCLK. The RX_FLAG terminal is held low. The data transition  

is timed to coincide with the falling edge of DCLK, so that the external microcontroller using the TRF6903 can  

latch RX_DATA on the rising edge of DCLK with plenty of setup and hold margin. If no data edges have been  

observed since the last reset, then DCLK is held low until an edge is seen.  

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data clock (continued)  

I

n

Self Train

mode, the TRF6903 receiver not only performs clock recovery, but also looks for the end of a training  

sequence. The TWO, E<12>, field determines the pattern of the training sequence. If TWO is low, the training  

sequence is assumed to be alternating ones and zeros; if TWO is high, the training sequence is assumed to  

be alternating pairs of ones and zeros. RX_DATA and DCLK output are the same as in

Clock Recovery

mode.  

However, if a minimum number of training bits have been observed, then the RX_FLAG terminal is asserted  

high for one clock period (after which it returns low) at the first bit that is not part of the training sequence. The  

timing of RX_FLAG is a few gate delays after the rising edge of DCLK. The minimum number of training bits  

is four times the unsigned binary value of TCOUN

T

,

E

<11:7>, plus two if TWO = 0 or plus three if TWO = 1,  

according to the equation:  

TB  

= (4 x TCOUNT) + TWO + 2  

min  

The clock recovery and training sequence recognition circuits are all designed to reset/clear internally with no  

user action required.  

When active, DCLK is synchronized to the received data. The rising edge of the data clock is intended to be  

located at the middle of the received recovered data bit, thus enhancing the synchronization ability of the  

microcontroller and reducing the need for extensive signal processing in the microcontroller.  

main divider  

The main divider is composed of a 5-bit A-counter and a 9-bit B-counter and a prescaler. The A-counter controls  

the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33  

until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count,  

whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33  

prescaler by:  

N

= 33

x

A + 32

x

(B – A)  

TOTAL  

where 0

≤

A

≤

31 and 31

≤

B

≤

511 or,

 

N  

= A + 32B  

TOTAL  

Thus, the N-divider has a range of 992

≤

N  

≤

16383  

TOTAL  

PLL  

The phase-locked loop is the radio frequency synthesizer for the TRF6903. It is used to generate the transmit  

signal and as the local oscillator for the receive mixer. The signal (F

 

) from a reference crystal oscillator (XO)  

X

is divided by an integer factor R down to F

 

. The minimum frequency resolution, and thus, the minimum channel  

R

spacing, is F

 

.  

R

F

= F

 

÷

R where 1

≤

R

≤

256  

X

R

The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an  

integer factor N to get a frequency at the phase detector input.  

F

= F  

÷

N  

VCO  

PD  

The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error  

signal from two charge pumps. The error signal corrects the VCO output to the desired frequency.  

As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nF

 

).  

R

In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal  

to the channel spacing, thus, channel spacing = F

 

= F

 

÷

R. When the PLL is locked, the LOCK_DETECT  

R

X

terminal is high.  

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PLL (continued)  

With the addition of an output divider for multiband operation, the actual output frequency, F

 

, is given by:  

out  

F

F

VCO  

P

A

)

 

32B  

X

N

P

N

P

F

+

+

 

+

 

F  

 

+

 

 

F  

out  

where F

 

= F  

R

R

R

P

under locked conditions. The actual minimum channel spacing is:  

R

PD  

F

F

B

 

R  

R

X

+

P

P

where P = 1, 2, 3 and is set by A<1:0>.  

oscillator circuit and reference divider  

The reference divider reduces the frequency of the external crystal (F

 

) by an 8-bit programmable integer  

X

divisor, R, to an internal reference frequency (F

 

) used for the phase-locked loop. See Figure 8. The choice of  

R

internal reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter  

design. The crystal frequency can be tuned using the F word to control internal trimming capacitors, which are  

placed in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an  

additional capacitor is placed in parallel (through terminal 31) with the external capacitor that is connected in  

series with the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 32)  

is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation.  

Hence, the 2-FSK frequency, set by the level of TX_DATA and the external capacitor, can be represented as  

follows:  

ƒ

+

 

TX_DATA Low (XTAL switch closed) and

ƒ  

+

 

TX_DATA High (XTAL switch open)  

out2  

out1  

Note that the frequencies

ƒ  

and

ƒ  

are centered about the frequency

ƒ  

= (

ƒ  

+

ƒ  

)/2. When  

out1  

out2  

center  

out1  

out2  

transmitting FSK,

ƒ  

is considered to be the effective carrier frequency and any receiver local oscillator (LO)  

center  

should be set to the same

ƒ  

frequency the

 

receiver’s IF frequency (

ƒ

) for proper reception and  

center  

IF  

demodulation.  

For the case of high-side injection, the receiver LO would be set to

ƒ

=

ƒ  

+

ƒ

. Using high-side injection,  

IF  

LO  

center  

the received data at terminal 33, RX_DATA, would be inverted from the transmitted data applied at terminal 32,  

TX_DATA. Conversely, for low-side injection, the receiver LO would be set to

ƒ

=

ƒ  

−

ƒ

. Using low-side  

LO  

center  

IF  

injection, the received data would be the same as the transmitted data. The data polarity invert bit PI, A<4>,  

can be used to invert the data at terminal 33, RX_DATA, when high-side injection is being used.  

In addition, when the TRF6903 is placed in receive mode, it is recommended that the D<19> bit be kept high  

to keep the XTAL switch closed. In this manner, the actual LO frequency injected into the mixer is

ƒ  

If D<19> is set low, the the receiver LO would be offset, resulting in poor receiver sensitivity.  

=

ƒ  

.

out1  

LO  

31  

V

CC  

÷

R  

Crystal  

Oscillator  

Circuit  

F

F

30  

R

Reference  

Divider  

2…255  

Phase-  

Frequency  

Detector  

External  

Loop  

Filter  

15  

13  

F

x

PD  

External Crystal  

VCO  

Charge Pumps  

÷

N  

External  

Cap for  

FSK  

Main Divider  

A, B Counters  

32/33  

Output  

Divider  

Fvco  

P = 1, 2, 3  

992

≤

N

≤

16383  

F

out  

Figure 8. TRF6903 PLL and Output Divider  

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phase detector and charge pumps  

The phase detector is a phase-frequency design. The phase-frequency detector gain is given by:  

K =

 

I /2

π  

P

(CP)  

where, I  

is the peak charge pump current. The peak charge pump current is programmable with A<3:2> in  

(CP)  

three steps: 250

µ

A, 500

µ

A, and 1000

µ

A.  

loop filter  

The loop filter must be carefully chosen for proper operation of the TRF6903. The loop filter as shown in Figure 9  

is typically a second- or third-order passive design and in FSK operation should have a bandwidth wide enough  

to allow the PLL to relock quickly as the external crystal frequency is pulled off-center during modulation. The  

loop filter should also be wider than the data modulation rate. These requirements should be balanced with  

making the loop narrow enough in consideration of the reference frequency. In OOK the VCO frequency is not  

changed during data modulation, so the filter bandwidth may be narrower than the modulation bandwidth. Filters  

can be calculated using standard formulas in reference literature. Some third-order filter examples are shown  

in

T

a

ble 4.  

1

1

)

 

sC2R2  

s C1

)

 

C2

)

 

sC1C2R2  

C3R3  

1

F(s)

+

 

 

(

)

s

)

 

C3R3  

R3  

lcp  

15  

Vtune  

13  

VCO_TUNE  

VCO_VCC  

CP_OUT  

C1  

C2  

R2  

C3  

External-Loop Filter  

Figure 9. Third-Order Loop Filter and Transfer Function  

Table 4. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz,  

0.5-mA Charge Pump Current  

Manchester coding  

NRZ coding  

1.024  

2.048  

1.024  

47  

2.048  

4.096  

2.048  

12  

4.096  

8.192  

4.096  

2.7  

8.192  

16.384  

8.192  

0.68  

27  

16.384  

32.768  

16.384  

0.18  

6.8  

19.2  

38.4  

19.2  

0.12  

5.1  

32.768  

65.536  

32.768  

0.043  

1.8  

65.536  

131.072  

65.536  

0.01  

Bit rate − kbps  

Data rate − kHz  

Fundamental freq of BB  

C1, nF  

C2, nF  

1800  

27  

430  

100  

1.5  

0.47  

Loop filter component  

(selected to nearest  

standard value)  

C3, nF  

R2, k

Ω  

R3, k

Ω  

6.8  

0.39  

3

0.1  

0.075  

6.8  

0.027  

12  

0.0068  

24  

0.39  

0.75  

1.28  

0.75  

1.5  

1.5  

5.7  

3

5.7  

12  

15  

22  

47  

−3−dB bandwidth, kHz (approximate)  

2.56  

5.12  

10.24  

20.48  

24  

40.96  

81.92  

VCO  

The voltage-controlled oscillator (VCO) produces an RF output signal with a frequency that is dependent upon  

the dc-tuning voltage at terminal 13. The tank circuit is passive and has integrated varactor diodes and  

inductors. The open-loop VCO gain is approximately 100 MHz/V.  

A <1:0> is used to set the output divider ratio for operation within the 315-MHz, 433-MHz, 868-MHz, or 915-MHz  

bands.  

When the STDBY terminal is high, the reference, PLL, VCO, and dividers are powered up. When STDBY is low,  

these blocks are powered down.  

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power amplifier  

The power amplifier has three programmable attenuation states as determined by A<7:6> and B<7:6>: full  

power (0-dB attenuation), 10-dB attenuation, and 20-dB attenuation. This adjustment feature allows the user  

to fine-tune the device for optimal output power. The power amplifier can be enabled/disabled during transmit  

by bit B<3>, PARXED. During receive, the transmit power amplifier is powered down but the VCO and PLL are  

still operating. During ASK or OOK operation, the TX_DATA signal turns the power amplifier on and off according  

to the transmit data incident at terminal 32.  

↑

1  

U

CH1 S22  

1

0.5  

2

5

CAL  

OFS  

0

0.2  

0.5  

1

2

5

10  

CPL  

−5  

FIL  

1k  

−0.5  

−2  

−1  

START 300

 

MHz  

STOP 1000

 

MHz  

Figure 10. Typical PA Output Impedance (S22) at Device Terminal PA_OUT  

brownout detector  

The brownout detector provides an output voltage to indicate a low supply voltage. This may be used to signal  

the need to change transmit power to conserve battery life, or for system power down. The brownout detector  

threshold is set with the B word. Four different thresholds are available.  

serial control interface  

The TRF6903 is controlled through a serial interface; there are five 24-bit control words (A, B, C, D, E) which  

set the device state. The A and B words are almost identical, and provide configuration settings for two modes,  

designated 0 and 1, which are commonly used to configure the transmit and receive states. The transmit and  

receive states can then be rapidly selected using MODE (terminal 21). The C word sets the reference dividers,  

the power amplifier bias, and contains various reset bits. The E word contains the bit-rate select, data clock  

control bits, and the power amplifier bias control registers. The D word is used to trim the external crystal  

frequency and tune the demodulator.  

The register address is the composite of bits 23, 22, 1, and 0 of the 24 bits written to the serial interface. For  

some words, certain bits of the address are don’t cares and are noted as XX. This flexible addressing scheme  

allows backward compatibility with the TRF6901, and because of this flexibility, the data length of each register  

varies from 15 bits to 22 bits.  

Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals.  

DATA values are clocked into the 24-bit serial interface shift register on the rising edge of CLOCK. The 24-bit  

value is decoded and written into the appropriate data register on the rising edge of STROBE.  

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PRINCIPLES OF OPERATION  

register description  

ꢀ ꢁ

 

ꢀ ꢀ

 

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ꢀ ꢃ  

ꢂ ꢄ  

ꢂ ꢅ  

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ꢂ

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ꢅ

ꢆ

ꢇ

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ꢁ

ꢀ

ꢂ

ꢃ

ꢊ

ꢋ

ꢌ

ꢍ

ꢎ

ꢍ

ꢍ

ꢌ

ꢏ

ꢐ

ꢐ

ꢎ

ꢍ

ꢍ

ꢌ

ꢏ

ꢐ

ꢐ

ꢑ ꢒ

 

ꢓꢔ ꢎꢕꢖ

 

ꢓꢗꢓ ꢍ

 

ꢏ ꢌ

 

ꢘꢋ ꢏ ꢙꢙꢓ

 

ꢚꢓ ꢏ

 

ꢔ ꢛ  

ꢜꢑ ꢋ

 

ꢍꢏ ꢃ

 

ꢝ  

ꢠꢡ ꢢ  

ꢣ ꢡꢃ  

ꢎ

ꢞ

ꢃ

ꢃ

ꢃ

ꢂ

ꢑ ꢒꢓ

 

ꢔ ꢞ

 

ꢕꢖꢓ ꢗꢓ ꢍꢏ

 

ꢌ ꢘ

 

ꢋꢏꢙꢙ ꢓ

 

ꢚꢓꢏ ꢔꢛ

 

ꢜꢑ ꢋꢍ

 

ꢏ ꢃꢝ  

ꢑ ꢒꢓ

 

ꢔ ꢞ

 

ꢕꢖꢓ ꢗꢓ ꢍꢏ

 

ꢌ ꢘ

 

ꢋꢏꢙꢙ ꢓ

 

ꢚꢓꢏ ꢔꢛ

 

ꢜꢑ ꢋꢍ

 

ꢏ ꢂꢝ  

ꢟ ꢎ ꢃ  

ꢟ ꢎ ꢂ  

ꢟ

ꢤ

ꢘ

ꢟ

ꢎ

ꢚ

ꢚ

ꢥ

ꢞꢦ ꢖ  

ꢑ ꢒ

 

ꢓꢔ ꢎꢕꢖ

 

ꢓꢗꢓ ꢍ

 

ꢏ ꢌ

 

ꢘꢋ ꢏ ꢙꢙꢓ

 

ꢚꢓ ꢏ

 

ꢔ ꢛ  

ꢜꢑ ꢋ

 

ꢍꢏ ꢂ

 

ꢝ  

ꢠꢡ ꢢ

 

ꢧ ꢨꢩ

 

ꢢ  

ꢣ ꢡꢂ

 

ꢪ ꢪ ꢩ  

ꢖꢏ ꢛ

 

ꢏ ꢚꢛ

 

ꢋꢌ ꢖꢏ

 

ꢛ ꢥ  

ꢠ ꢬꢌ

 

ꢏ ꢐꢬꢋ ꢭ

 

ꢍ ꢫꢔ

 

ꢒ ꢮ ꢭꢏ  

ꢟ

ꢎ

ꢣ

ꢡ

ꢫ

ꢖ

ꢘ

ꢫ

ꢂ

ꢂ

ꢃ

ꢃ

ꢣꢏ ꢙ

 

ꢏꢌ ꢏꢔ

 

ꢚ ꢏ

 

ꢖꢓ ꢗꢓ ꢍ

 

ꢏ ꢌ

 

ꢘꢋ ꢏ ꢙꢙꢓ

 

ꢚꢓ ꢏ

 

ꢔ ꢛ  

ꢞꢣ ꢞ

 

ꢞꢣꢘ  

ꢣ

ꢏ

ꢐ

ꢏ

ꢌ

ꢗ

ꢏ

ꢍ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢃ

ꢃ

ꢃ

ꢂ

ꢞ

ꢣ

ꢎ

ꢣ

ꢡ

ꢑ

ꢠꢡ ꢑ

 

ꢠꢊ ꢪ  

ꢖ ꢏꢳ

 

ꢱꢠꢲꢔ ꢏ  

ꢠꢘ ꢪ

 

ꢯꢦ ꢠ  

ꢌ

ꢃ

ꢃ

ꢟꢧ ꢖ  

ꢌꢏ ꢐꢏ ꢛ  

ꢂ

ꢂ

ꢌ

ꢌ

ꢣ

ꢡ

ꢨ

ꢡꢠꢎꢰ ꢱ ꢠꢲ ꢔ ꢏ  

ꢪ

ꢪ

ꢩ

ꢡ

ꢨ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢌ

ꢃ

ꢖ

NOTE: r

 

= reserved. All reserved bits should be set low (0) during normal operation.  

NOTE: All

 

bits indicated as 1 should be set high (1) during normal operation.  

NOTE: All

 

bits indicated as 0 should be set low (0) during normal operation.  

ADDRESS  

LOCATION  

NO. OF  

BITS  

DESCRIPTION  

DEFAULT VALUE  

00xx  

00xx  

00xx  

00xx  

00xx  

00xx  

00xx  

01xx  

01xx  

01xx  

01xx  

01xx  

01xx  

2

1

:

1

7  

1

6

:8  

7:6  

5

5

9

2

1

1

2

2

5

9

2

1

1

1

Main A divider coefficient (Mode 0)  

00000  

Main B divider coefficient (Mode 0)  

Controls the PA attenuation (Mode 0)  

Enables transmit/receive path (Mode 0)  

Receive data polarity invert bit  

001110000  

10  

0

4

0

3:2  

1:0  

2

1

:

1

7  

1

6

:8  

7:6  

5

Controls charge pump peak current  

Output divider coefficient; band select  

Main A divider coefficient (Mode 1)  

Main B divider coefficient (Mode 1)  

Controls the PA attenuation (Mode 1)  

Enables transmit/receive path (Mode 1)  

00  

10  

00000  

001110000  

10  

0

4

Controls modulation scheme (FSK or OOK)  

0

3

Enables or disables the power amplifier while in transmit mode  

or the receive chain while in receive mode  

0

01xx  

01xx  

1000  

1001  

1001  

1001  

1001  

1001  

1001  

1001  

11×0  

11×0  

11×0  

11×0  

2:1  

0

2

1

8

2

3

1

2

1

1

5

1

3

1

3

Sets threshold for the brownout detector  

Enables brownout detector  

00  

0

2

1

:

1

4  

2

1

:

2

0  

1

9

:

1

7  

16  

Reference divider coefficient  

01000000  

Bit-rate divider D1  

11  

010  

0

Bit-rate divider D2  

Bit-rate divider D3  

1

5

:

1

4  

13  

Receive mode select  

00  

Transmit capture mode select  

RX training sequence pattern select  

Determines the minimum number of training bits  

Controls the position of the XTAL switch during FSK reception  

Tunes the XTAL frequency by using an internal capacitor bank  

PFD reset  

0

12  

0

11 : 7  

19  

00100  

0

1

8

:

1

6  

15  

000  

1

1

4

:

1

2  

Tunes the resonant frequency of the external demodulation  

tank circuit  

000  

11×0  

11  

1

Controls the position of the XTAL switch during OOK operation  

0

NOTE: x

 

= don’t care  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

At power on/startup, all of the TRF6903 register contents are as per the default values.  

Address 00XX (A-Word):  

Word A is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 0), A<21:17>,  

is the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient  

(mode 0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A  

<16:8> are

 

unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE  

terminal is low. TX/RX0, A<5>, is the TX/RX switch when the MODE terminal is low. PI, A<4>, is the data  

polarity invert bit. When high, this bit causes the data slicer output to be inverted. CP Acc., A<3:2>, sets the  

charge pump current. BND, A<1:0>, sets the output divider, which in turn determines the band of operation.  

T

e

rminal 21 (MODE) selects bits A

<

2

1

:5>

i

f low, or B

<

2

1

:5>

i

f high.  

Main divider A

<

2

1

:

1

7

>

: 5-bit value for divider ratio of the A counter  

Main divider A

<

1

6

:8

>

: 9-bit value for divider ratio of the B counter  

PA attenuation A

<

7:6

>

: 2 bits for setting the PA attenuation  

A

<

7:6>  

PA ATTENUATION  

0 dB  

00  

01  

10  

11  

10 dB  

20 dB  

Not defined  

A

<

5

>

: 1-bit TX/RX mode select  

A

<

5>  

TX/RX MODE  

RX mode  

0

1

TX mode  

A

<

4

>

: 1-bit data polarity invert bit  

A<

4

>  

RX DATA POLARITY  

Noninverted  

0

1

Inverted  

A

<

3

:

2

>

: 2 bits for setting the charge pump current  

A<

3

:2>  

00  

CP CURRENT  

0.5 mA  

01  

1 mA  

10  

0.25 mA  

11  

Not defined  

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ꢈꢖ ꢌ ꢁ  

SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

A

<

1

:0>: 2-bit value to set the output divider and thus select the band of operation.  

A<1:

0

>  

OUTPUT DIVIDER  

RATIO, P  

BAND OF  

OPERATION  

00  

01  

3

2

315 MHz  

433 MHz  

10  

11  

1

1

868 MHz or 915 MHz  

868 MHz or 915 MHz  

Address 01XX (B-Word):  

Word B is a 22-bit data register comprising eight fields. The main A-divider coefficient (mode 1), B<21:17>,  

is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient  

(mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and  

B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE  

terminal is high. TX/RX1, B<5>, is the TX/RX switch when the MODE terminal is high. FSK/OOK, B<4>, sets  

the modulation scheme for both TX and RX. Bit B<3> enables/disables the power amplifier while in transmit  

mode and enables/disables the receive chain while in receive mode. The detector threshold, B<2:1>, is the  

2-bit setting for the threshold voltage of the brownout detector. Det. Enable, B<0>, is the brownout detector  

enable flag.  

T

e

rminal 21 (MODE) selects bits A

<

2

1

:5>

i

f low, or B

<

2

1

:5>

i

f high.  

Main divider B

<

2

1

:

1

7

>

: 5-bit value for divider ratio of the A-counter  

Main divider B

<

1

6

:8

>

: 9-bit value for divider ratio of the B-counter  

PA attenuation B

<

7:6

>

: 2 bits for setting the PA attenuation  

B

<

7:6>  

PA ATTENUATION  

0 dB  

00  

01  

10  

11  

10 dB  

20 dB  

Not defined  

B

<

5

>

: 1-bit TX/RX mode select  

B

<

5>  

TX/RX MODE  

RX mode  

0

1

TX mode  

B

<

4>

1

-bit modulation select  

B

<

4>  

TX/RX MODULATION  

0

1

OOK  

FSK  

NOTE: During

 

OOK reception, the OOK switch is closed. During FSK reception, the OOK switch is open.  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

B

<

3

>

: 1-bit PA or receive chain enable/disable  

B

<

3>  

PA OR RECEIVE CHAIN  

ENABLE/DISABLE  

0

1

Disabled  

Enabled  

B

<

2:1

>

: 2-bit value to set the threshold voltage for the brownout detector  

B

<

2:1>  

THRESHOLD VOLTAGE  

00  

01  

10  

11  

2.2 V  

2.4 V  

2.6 V  

2.8 V  

B

<

0

>

: 1 bit to enable brownout detector  

B

<

0>  

BROWNOUT DETECTOR  

0

1

Off  

On  

Address 1000 (C-Word):  

Word C is a 20-bit data register comprising four fields. The reference divider

 

coefficient, C<21:14>, is the  

8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> =  

00000010) through 255 (C <21:14> = 11111111).  

Bits C<13> through C<2> are reserved and should be set to 0.  

Address 1001 (E-Word):  

Word E is a 20-bit data register comprising eight fields. The bit rate or bit frequency, used by the clock  

recovery receive modes and the transmit synchronous mode is controlled by the BRA, E<21:20>, BRB,  

E<19:17>, and BRC, E<16>, fields. These three fields control a sequence of dividers, D1 through D3, that  

divide the reference (crystal) frequency, F

 

.  

X

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

E<21:20>: 2 bits to set D1 divider setting  

E<21:20>  

D1  

1

00  

01  

10  

11  

5

6

8

E<19:17>: 3 bits to set D2 divider setting  

E<19:17>  

000  

D2  

1

001  

2

010  

4

011  

8

100  

101  

110  

111  

16  

32  

64  

128  

E<16>: 1 bit to set D3 divider setting  

E<16>  

D3  

0

1

16  

15  

RXM, E<15:14> controls the signals that appear at the RX_DATA and DCLK terminals. The definition of  

RXM is contained in

T

a

ble 3.  

TXM, E<13>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit  

function asynchronously. If TXM is high, the bit-rate clock is output at DCLK and the transmit data at the  

TX_DATA terminal is latched on the rising edge of DCLK, where DCLK is the bit-rate clock.  

TWO, E<12>, sets the receive training sequence pattern. If TWO is high, the expected training sequence is  

assumed to be alternating pairs of ones and zeroes. If TWO is low, the expected training sequence is  

assumed to be alternating ones and zeroes.  

TCOUN

T

, E>11:7>, determines the minimum number of training bits. The minimum number of training bits is  

four times the unsigned binary value of TCOUN

T

,

p

lus two if TWO = 0 or plus three if TWO = 1.  

Bits E<6> through E<2> are reserved and should be set to 0.  

Address 11X0 (D-Word):  

Word D is a 21-bit data register comprising three fields. XTAL_Tune, D<18:16>, is used to fine tune the  

crystal frequency by using an internal capacitor bank. PFD reset, D<15>, selects the source of the PFD  

reset signal. Dem_Tune, D<14:12>, is a 3-bit value used to tune the demodulator time constant. Bit D<11>  

controls the position of the XTAL switch during OOK operation.  

D

<

1

9

>

: 1-bit value to control the position of the XTAL switch during FSK reception, when B<4>=1 and  

either A<5> or B<5> = 0. It is recommended to set this bit to 1 (XTAL switch closed). If D<19> is set to 0  

(XTAL switch open), the LO frequency injected into the mixer is f  

= f

 

+ designed peak-peak  

outs  

LO  

deviation. This results in the down-converted IF signal shifting higher (high-side injection) or lower  

(low-side injection) from the IF center frequency (10.7 MHz) by an amount equal to the designed  

peak-peak frequency deviation.  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

D<1

9

>  

XTAL SWITCH DURING FSK  

RECEPTION  

TERMINAL 31  

0

1

Unconnected (open)  

High-Z  

Connected (closed)  

Shorted to ground internally  

D

<

1

8

:

1

6

>

: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank.  

D

<

1

8:1

6

>  

000  

TYPICAL LOAD CAPACITANCE  

13.23 pF  

22.57 pF  

17.9 pF  

001  

010  

011  

27.24 pF  

15.56 pF  

24.9 pF  

100  

101  

110  

20.23 pF  

29.57 pF  

111  

D

<

1

5

>

: 1-bit value to select the reset signal for the PFD  

D<1

5

>  

RESET SIGNAL  

Derived from XTAL  

Derived from prescaler  

0

1

NOTE: The

 

default setting for D<15> is 1.  

D

<

1

4

:

1

2

>

: 3-bit value to tune the resonant frequency of the external demodulator tank circuit. It can be  

used to optimize the receiver performance. The recommended default setting is 110.  

D

<

1

1>: 1-bit value to control position of the XTAL switch during OOK operation, when B<4> = 0.  

D<1

1

>  

XTAL SWITCH DURING OOK  

OPERATION  

TERMINAL 31  

0

1

Unconnected (open)  

Connected (closed)  

High-Z  

Shorted to ground internally  

It is recommended that D<19> and D<11> be set to 0 during FSK reception and OOK operation.  

Bits D<21>, D<20>, and D<10> through D<1> are reserved and should be set to 0.  

operating modes  

Controlled with terminal 26, STDBY  

STDBY  

OPERATING MODE  

0

1

Power down of all blocks—programming mode  

Operational mode and programming mode  

Controlled with terminal 21, MODE  

MODE  

OPERATING MODE  

Enable A-word  

Enable B-word  

0

1

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

PRINCIPLES OF OPERATION  

Controlled with terminal 39, LEARN/HOLD  

LEARN/HOLD  

OPERATING MODE  

0

1

Selects data slicer decision level to HOLD  

Selects data slicer decision level to LEARN  

The transmit/receive mode is controlled by the TX/RX0, A<5>, TX/RX1, B<5>, and PARXED, B<3>, fields  

and the MODE and STDBY terminals.  

A<5>  

B<5>  

B<3>  

MODE  

STDBY  

OPERATING MODE  

Off, programming mode; SPI enabled  

X

0

X

X

X

0

X

0

0

1

Receive mode 0, RX chain disabled. Reference, PLL, VCO and  

dividers enabled  

0

1

X

X

X

0

0

1

1

1

0

1

0

1

0

1

0

0

0

1

1

1

1

1

1

1

1

1

1

1

Receive mode 0, RX chain enabled. Reference, PLL, VCO and  

dividers enabled  

Transmit mode 0, PA disabled. Reference, PLL, VCO and dividers  

enabled  

1

Transmit mode 0, PA enabled. Reference, PLL, VCO and dividers  

enabled  

X

X

X

X

Receive mode 1, RX chain disabled. Reference, PLL, VCO and  

dividers enabled  

Receive mode 1, RX chain enabled. Reference, PLL, VCO and  

dividers enabled  

Transmit mode 1, PA disabled. Reference, PLL, VCO and dividers  

enabled  

Transmit mode 1, PA enabled. Reference, PLL, VCO and dividers  

enabled  

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SWRS022D − MARCH 2004 − REVISED JUNE 2005  

APPLICATION INFORMATION  

BPF1  

MuRata  

SFECF10M7 Series  

C1  

3

1

82 pF  

C2  

100 pF  

C3  

120 pF  

L1  

4.7