Texas-Instruments-ULN2003APWR
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ULN200x, ULQ200x H
i
gh-Voltage, High-Current Darlington Transistor Arrays
The ULx2004A devices have a 10.5-k
Ω
series base
resistor to allow operation directly from CMOS
devices that use supply voltages of 6 V to 15 V. The
required input current of the ULx2004A device is
below that of the ULx2003A devices, and the required
voltage is less than that required by the ULN2002A
device.
1 Features
1
•
•
•
•
•
500-mA-Rated Collector Current (Single Output)
High-Voltage Outputs: 50 V
Output Clamp Diodes
Inputs Compatible With Various Types of Logic
Relay-Driver Applications
.
2 Applications
•
•
•
•
•
•
Relay Drivers
PART NUMBER
ULx200xD
PACKAGE
BODY SIZE (NOM)
9.90 mm × 3.91 mm
19.30 mm × 6.35 mm
10.30 mm × 5.30 mm
5.00 mm × 4.40 mm
Stepper and DC Brushed Motor Drivers
Lamp Drivers
SOIC (16)
ULx200xN
PDIP (16)
SOP (16)
Display Drivers (LED and Gas Discharge)
Line Drivers
ULN200xNS
ULN200xPW
TSSOP (16)
Logic Buffers
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
.
.
The ULx200xA devices are high-voltage, high-current
Darlington transistor arrays. Each consists of seven
NPN Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads.
Simplified Block Diagram
9
COM
1
2
3
4
5
6
7
16
15
14
13
12
11
10
The collector-current rating of a single Darlington pair
is 500 mA. The Darlington pairs can be paralleled for
higher current capability. Applications include relay
drivers, hammer drivers, lamp drivers, display drivers
(LED and gas discharge), line drivers, and logic
buffers. For 100-V (otherwise interchangeable)
data sheet for the SN75468 and SN75469 devices.
1B
2B
3B
4B
5B
6B
7B
1C
2C
3C
4C
5C
6C
7C
The ULN2002A device is designed specifically for use
with 14-V to 25-V PMOS devices. Each input of this
device has a Zener diode and resistor in series to
control the input current to
a safe limit. The
ULx2003A devices have a 2.7-k
Ω
series base resistor
for each Darlington pair for operation directly with
TTL or 5-V CMOS devices.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
7
8
9
6.6 Electrical
Characteristics: ULN2003A and
6.9 Electrical
Characteristics: ULQ2003A and
6.10 Switching
Characteristics: ULN2002A, ULN2003A,
13 Mechanical,
Packaging, and Orderable
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2015) to Revision O
Page
•
Changes from Revision M (February 2013) to Revision N
Page
•
Added
Pin Configuration and Functions
section,
ESD Ratings
table,
Feature Description
section,
Device Functional
Modes
,
Application and Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device
and Documentation Support
section, and
Mechanical, Packaging, and Orderable Information
section …………………………
1
•
•
Changes from Revision L (April 2012) to Revision M
Page
•
Changes from Revision K (August 2011) to Revision L
Page
•
2
Copyright © 1976–2016, Texas Instruments Incorporated
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5 Pin
Configuration and Functions
D, N, NS, and PW Package
16-Pin SOIC, PDIP, SO, and TSSOP
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2B
3B
4B
5B
6B
7B
E
1C
2C
3C
4C
5C
6C
7C
COM
Pin Functions
PIN
I/O
(1)
DESCRIPTION
NAME
1B
NO.
1
2B
2
3B
3
4B
4
I
Channel 1 through 7 Darlington base input
5B
5
6B
6
7B
7
1C
2C
3C
4C
5C
6C
7C
COM
E
16
15
14
13
12
11
10
9
O
Channel 1 through 7 Darlington collector output
—
—
Common cathode node for flyback diodes (required for inductive loads)
Common emitter shared by all channels (typically tied to ground)
8
(1) I
= Input, O = Output
Copyright © 1976–2016, Texas Instruments Incorporated
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6 Specifications
6.1 Absolute
Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)
(1)
MIN
MAX
50
UNIT
V
V
CC
Collector-emitter voltage
Clamp diode reverse voltage
(2)
Input voltage
(2)
50
V
V
I
30
V
Output clamp current
500
500
–2.5
70
mA
mA
A
I
OK
Total emitter-terminal current
ULN200xA
ULN200xAI
ULQ200xA
ULQ200xAT
–20
–40
–40
–40
105
85
T
A
Operating free-air temperature range
°C
105
150
260
150
T
J
Operating virtual junction temperature
°C
°C
°C
Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds
Storage temperature
T
stg
–65
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All
voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
6.2 ESD
Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101
(2)
Electrostatic
discharge
V
(ESD)
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
50
UNIT
V
V
CC
T
J
Collector-emitter voltage (non-V devices)
Junction temperature
0
–40
125
°C
6.4 Thermal
Information
ULx200x
D
N
NS
PW
THERMAL METRIC
(1)
UNIT
(SOIC)
(PDIP)
16 PINS
67
(SO)
16 PINS
64
(TSSOP)
16 PINS
108
16 PINS
73
R
θ
JA
R
θ
JC(top)
R
θ
JB
ψ
JT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
36
54
n/a
33.6
n/a
n/a
n/a
51.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
n/a
n/a
n/a
2.1
ψ
JB
n/a
n/a
n/a
51.4
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
4
Copyright © 1976–2016, Texas Instruments Incorporated
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6.5 Electrical
Characteristics: ULN2002A
T
A
= 25°C
ULN2002A
UNIT
PARAMETER
TEST FIGURE
TEST CONDITIONS
V
CE
= 2 V,
I
C
= 300 mA
V
S
= 50 V, I
O
= 300 mA
MIN
TYP
MAX
V
I(on)
V
OH
ON-state input voltage
13
V
High-level output voltage after
switching
V
S
– 20
mV
I
I
= 250
μ
A,
I
I
= 350
μ
A,
I
I
= 500
μ
A,
I
F
= 350 mA
V
CE
= 50 V,
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
0.9
1
1.1
1.3
1.6
2
Collector-emitter saturation
voltage
V
CE(sat)
V
V
1.2
1.7
V
F
Clamp forward voltage
Collector cutoff current
I
I
= 0
50
I
CEX
I
I
= 0
100
500
μ
A
V
CE
= 50 V,
T
A
= 70°C
V
I
= 6 V
I
C
= 500
μ
A
I
I(off)
I
I
OFF-state input current
Input current
V
CE
= 50 V,
V
I
= 17 V
V
R
= 50 V
V
R
= 50 V
V
I
= 0,
50
65
μ
A
0.82
1.25
100
50
mA
T
A
= 70°C
f = 1 MHz
I
R
C
i
Clamp reverse current
Input capacitance
μ
A
25
pF
6.6 Electrical
Characteristics: ULN2003A and ULN2004A
T
A
= 25°C
ULN2003A
MIN TYP
MAX
ULN2004A
TEST
FIGURE
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
I
C
= 125 mA
I
C
= 200 mA
I
C
= 250 mA
5
6
2.4
2.7
ON-state input
voltage
V
I(on)
V
CE
= 2 V
V
I
C
= 275 mA
I
C
= 300 mA
I
C
= 350 mA
7
8
3
High-level output
voltage after
switching
V
OH
V
S
= 50 V, I
O
= 300 mA
V
S
– 20
V
S
– 20
mV
V
I
I
= 250
μ
A,
I
I
= 350
μ
A,
I
I
= 500
μ
A,
V
CE
= 50 V,
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
I
I
= 0
0.9
1
1.1
1.3
1.6
50
0.9
1
1.1
1.3
1.6
50
Collector-emitter
saturation voltage
V
CE(sat)
1.2
1.2
Collector cutoff
current
I
CEX
I
I
= 0
100
100
500
μ
A
V
CE
= 50 V,
T
A
= 70°C
V
I
= 6 V
Clamp forward
voltage
I
F
= 350 mA
V
F
1.7
2
1.7
65
2
V
Off-state input
current
V
CE
= 50 V,
T
A
= 70°C,
I
I(off)
I
C
= 500
μ
A
50
65
50
μ
A
V
I
= 3.85 V
V
I
= 5 V
0.93
1.35
I
I
Input current
0.35
1
0.5 mA
1.45
V
I
= 12 V
V
R
= 50 V
V
R
= 50 V
V
I
= 0,
50
100
25
50
100
25
Clamp reverse
current
I
R
C
i
μ
A
T
A
= 70°C
f = 1 MHz
Input capacitance
15
15
pF
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6.7 Electrical
Characteristics: ULN2003AI
T
A
= 25°C
ULN2003AI
TEST
CONDITIONS
PARAMETER
TEST FIGURE
UNIT
MIN
TYP
MAX
I
C
= 200 mA
I
C
= 250 mA
I
C
= 300 mA
2.4
2.7
3
V
I(on)
ON-state input voltage
V
CE
= 2 V
V
mV
V
High-level output voltage after
switching
V
OH
V
S
= 50 V, I
O
= 300 mA
V
S
– 50
I
I
= 250
μ
A,
I
I
= 350
μ
A,
I
I
= 500
μ
A,
V
CE
= 50 V,
I
F
= 350 mA
V
CE
= 50 V,
V
I
= 3.85 V
V
R
= 50 V
V
I
= 0,
I
C
= 100 mA
0.9
1
1.1
1.3
1.6
50
2
V
CE(sat)
Collector-emitter saturation voltage
I
C
= 200 mA
I
C
= 350 mA
I
I
= 0
1.2
I
CEX
V
F
I
I(off)
I
I
Collector cutoff current
Clamp forward voltage
OFF-state input current
Input current
μ
A
V
1.7
65
I
C
= 500
μ
A
50
μ
A
mA
μ
A
pF
0.93
1.35
50
I
R
Clamp reverse current
Input capacitance
C
i
f = 1 MHz
15
25
6.8 Electrical
Characteristics: ULN2003AI
T
A
= –40°C to 105°C
ULN2003AI
PARAMETER
TEST FIGURE
TEST CONDITIONS
UNIT
MIN
TYP
MAX
2.7
2.9
3
I
C
= 200 mA
V
I(on)
ON-state input voltage
V
CE
= 2 V
I
C
= 250 mA
I
C
= 300 mA
V
mV
V
High-level output voltage after
switching
V
OH
V
S
= 50 V, I
O
= 300 mA
V
S
– 50
I
I
= 250
μ
A,
I
I
= 350
μ
A,
I
I
= 500
μ
A,
V
CE
= 50 V,
I
F
= 350 mA
V
CE
= 50 V,
V
I
= 3.85 V
V
R
= 50 V
V
I
= 0,
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
I
I
= 0
0.9
1
1.2
1.4
1.7
100
2.2
V
CE(sat)
Collector-emitter saturation voltage
1.2
I
CEX
V
F
I
I(off)
I
I
Collector cutoff current
Clamp forward voltage
OFF-state input current
Input current
μ
A
V
1.7
65
I
C
= 500
μ
A
30
μ
A
mA
μ
A
pF
0.93
1.35
100
25
I
R
Clamp reverse current
Input capacitance
C
i
f = 1 MHz
15
6
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6.9 Electrical
Characteristics: ULQ2003A and ULQ2004A
over recommended operating conditions (unless otherwise noted)
TEST
ULQ2003A
ULQ2004A
PARAMETER
TEST CONDITIONS
UNIT
FIGURE
MIN TYP
MAX
MIN TYP
MAX
I
C
= 125 mA
I
C
= 200 mA
I
C
= 250 mA
5
6
2.7
2.9
ON-state input
voltage
V
I(on)
V
CE
= 2 V
V
I
C
= 275 mA
I
C
= 300 mA
I
C
= 350 mA
7
8
3
High-level output
voltage after
switching
V
OH
V
S
= 50 V, I
O
= 300 mA
V
S
– 50
V
S
– 50
mV
V
I
I
= 250
μ
A,
I
I
= 350
μ
A,
I
I
= 500
μ
A,
V
CE
= 50 V,
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
I
I
= 0
0.9
1
1.2
1.4
1.7
100
0.9
1
1.1
1.3
1.6
50
Collector-emitter
saturation voltage
V
CE(sat)
1.2
1.2
Collector cutoff
current
I
CEX
V
CE
= 50 V,
T
A
= 70°C
I
I
= 0
100
μ
A
V
I
= 6 V
500
Clamp forward
voltage
V
F
I
F
= 350 mA
1.7
65
2.3
1.7
65
2
V
OFF-state input
current
V
CE
= 50 V,
T
A
= 70°C,
I
I(off)
I
C
= 500
μ
A
50
μ
A
V
I
= 3.85 V
V
I
= 5 V
0.93 1.35
I
I
Input current
0.35
1
0.5 mA
1.45
V
I
= 12 V
V
R
= 50 V
V
R
= 50 V
V
I
= 0,
T
A
= 25°C
f = 1 MHz
100
100
50
Clamp reverse
current
I
R
C
i
μ
A
100
Input capacitance
15
25
15
25 pF
6.10 Switching
Characteristics: ULN2002A, ULN2003A, ULN2004A
T
A
= 25°C
ULN2002A, ULN2003A,
ULN2004A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
0.25
0.25
MAX
t
PLH
t
PHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
1
μ
s
μ
s
1
6.11 Switching
Characteristics: ULN2003AI
T
A
= 25°C
ULN2003AI
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
0.25
0.25
MAX
t
PLH
t
PHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
1
1
μ
s
μ
s
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6.12 Switching
Characteristics: ULN2003AI
T
A
= –40°C to 105°C
ULN2003AI
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
1
MAX
10
10
t
PLH
t
PHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
μ
s
μ
s
1
6.13 Switching
Characteristics: ULQ2003A, ULQ2004A
over recommended operating conditions (unless otherwise noted)
ULQ2003A, ULQ2004A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
1
MAX
10
t
PLH
t
PHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
μ
s
μ
s
1
10
6.14 Typical
Characteristics
2.5
2.5
2
T
A
= 25
°
C
T
A
= 25
°
C
I =
250
µ
A
I
2
1.5
1
I =
350
µ
A
I
I =
250
µ
A
I
I =
350
µ
A
I
I =
500
µ
A
I
1.5
1
I =
500
µ
A
I
0.5
0
0.5
0
0
100 200 300 400 500 600 700 800
– Total
Collector Current –
mA
0
100 200 300 400 500 600 700 800
– Collector
Current –
mA
I
I
C(tot)
C
Figure 1. Collector-Emitter Saturation Voltage
vs Collector Current (One Darlington)
Figure 2. Collector-Emitter Saturation Voltage
vs Total Collector Current (Two Darlingtons in Parallel)
8
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Typical Characteristics (continued)
600
500
400
500
R
T
= 10
Ω
= 25
°
C
L
450
400
350
300
250
200
150
100
50
A
V
S
= 10 V
N = 1
N = 4
V
= 8 V
S
N = 3
300
200
100
0
N = 2
N = 6
N = 7
N = 5
T
A
= 70
°
C
N = Number of Outputs
Conducting Simultaneously
0
0
25
50
75
100 125 150 175 200
0
10 20 30 40 50 60 70 80 90
100
Duty Cycle –
%
I
– Input
Current –
µ
A
I
Figure 3. Collector Current vs Input Current
Figure 4. D Package Maximum Collector Current
vs Duty Cycle
2000
600
500
T
J
= -40°C to 105°C
1800
1600
1400
1200
N = 1
N = 3
N = 2
400
300
200
100
0
N = 4
1000
800
600
400
200
0
Maximum
N = 5
N = 6
N = 7
T
A
= 85
°
C
Typical
N = Number of Outputs
Conducting Simultaneously
0
10 20 30 40 50 60 70 80 90
100
Duty Cycle –
%
2
2.5
3 3.5
Input Voltage – V
4
4.5
5
Figure 6. Maximum and Typical Input Current
vs Input Voltage
Figure 5. N Package Maximum Collector Current
vs Duty Cycle
2.1
500
V
CE
= 2 V
T
J
= -40°C to 105°C
T
J
= -40°C to 105°C
450
1.9
1.7
400
350
300
250
Maximum
1.5
1.3
1.1
0.9
Minimum
200
150
Typical
100
250
350
450
550
650
100
200
300
400
500
Output Current – mA
Input Current – µA
Figure 7. Maximum and Typical Saturated V
CE
vs Output Current
Figure 8. Minimum Output Current vs Input Current
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7 Parameter
Measurement Information
Open
Open
V
V
CE
CE
I
I
CEX
CEX
Open
V
I
Figure 9. I
CEX
Test Circuit
Figure 10. I
CEX
Test Circuit
Open
Open
V
CE
I
I
I
I(off)
I(on)
C
V
Open
I
Figure 11. I
I(off)
Test Circuit
Figure 12. I
I
Test Circuit
I
I
is fixed for measuring V
CE(sat)
, variable for measuring h
FE
.
Open
Open
I
C
h
=
FE
I
I
V
V
V
CE
CE
I(on)
I
I
I
C
I
C
Figure 13. h
FE
, V
CE(sat)
Test Circuit
Figure 14. V
I(on)
Test Circuit
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Parameter Measurement Information (continued)
V
R
I
R
V
F
I
F
Open
Open
Figure 15. I
R
Test Circuit
Figure 16. V
F
Test Circuit
Figure 17.
Propagation Delay-Time Waveforms
200
W
≤
5 ns
≤
10 ns
V
IH
(see Note C)
90%
1.5 V
90%
1.5 V
Input
10%
10%
0 V
40
µ
s
V
OH
Output
V
OL
VOLTAGE WAVEFORMS
The pulse generator has the following characteristics: PRR = 12.5 kHz, Z
O
= 50
Ω
.
C
L
includes probe and jig capacitance.
For testing the ULN2003A device, ULN2003AI device, and ULQ2003A devices, V
IH
= 3 V; for the ULN2002A device,
V
IH
= 13 V; for the ULN2004A and the ULQ2004A devices, V
IH
= 8 V.
Figure 18.
Latch-Up Test Circuit and Voltage Waveforms
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8 Detailed
Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The ULN2003A device comprises seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULN2003A device has a series base resistor to each Darlington pair,
thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2003A
device offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and
LEDs. Applications requiring sink currents beyond the capability of a single output may be accommodated by
paralleling the outputs.
This device can operate over a wide temperature range (–40°C to 105°C).
8.2 Functional
Block Diagrams
All resistor values shown are nominal. The collector-emitter diode is a parasitic structure and should not be used
to conduct current. If the collectors go below GND, an external Schottky diode should be added to clamp
negative undershoots.
COM
Output C
7 V
10.5
kΩ
Input B
E
7.2
kΩ
3
kΩ
Figure 19.
ULN2002A Block Diagram
COM
COM
Output C
Output C
R
B
R
B
2.7
kΩ
10.5
kΩ
Input B
Input B
E
E
7.2
kΩ
3
kΩ
7.2
kΩ
3
kΩ
Figure 20. ULN2003A, ULQ2003A and ULN2003AI
Block Diagram
Figure 21. ULN2004A and LQ2004A Block Diagram
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8.3 Feature
Description
Each channel of the ULN2003A device consists of Darlington connected NPN transistors. This connection
creates the effect of a single transistor with a very high-current gain (
β
2). This can be as high as 10,000 A/A at
certain currents. The very high
β
allows for high-output current drive with a very low input current, essentially
equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-k
Ω
resistor connected between the input and
base of the predriver Darlington NPN. The 7.2-k
Ω
and 3-k
Ω
resistors connected between the base and emitter of
each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
8.4 Device
Functional Modes
8.4.1 Inductive
Load Drive
When the COM pin is tied to the coil supply voltage, ULN2003A device is able to drive inductive loads and
suppress the kick-back voltage through the internal free-wheeling diodes.
8.4.2 Resistive
Load Drive
When driving a resistive load, a pullup resistor is needed in order for ULN2003A device to sink current and for
there to be a logic high level. The COM pin can be left floating for these applications.
Copyright © 1976–2016, Texas Instruments Incorporated
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9 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application
Information
Typically, the ULN2003A device drives a high-voltage or high-current (or both) peripheral from an MCU or logic
device that cannot tolerate these conditions. This design is a common application of ULN2003A device, driving
inductive loads. This includes motors, solenoids and relays.
Figure 22
shows a model for each load type.
9.2 Typical
Application
ULN2003A
OUT1
3.3-V Logic
3.3-V Logic
3.3-V Logic
IN1
IN2
OUT2
OUT3
OUT4
IN3
IN4
V
SUP
IN5
OUT5
OUT6
OUT7
COM
IN6
IN7
GND
V
SUP
Figure 22.
ULN2003A Device as Inductive Load Driver
9.2.1 Design
Requirements
Table 1. Design Parameters
DESIGN PARAMETER
GPIO voltage
EXAMPLE VALUE
3.3 V or 5 V
Coil supply voltage
Number of channels
12 V to 48 V
7
20 mA to 300 mA per channel
100%
Output current (R
COIL
)
Duty cycle
14
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9.2.2 Detailed
Design Procedure
When using ULN2003A device in a coil driving application, determine the following:
•
•
•
•
Input voltage range
Temperature range
Output and drive current
Power dissipation
9.2.2.1 Drive
Current
The coil voltage (V
SUP
), coil resistance (R
COIL
), and low-level output voltage (V
CE(SAT)
or V
OL
) determine the coil
current.
I
COIL
= (V
SUP
– V
CE(SAT)
) / R
COIL
(1)
9.2.2.2 Low-Level
Output Voltage
The low-level output voltage (V
OL
) is the same as V
CE(SAT)
and can be determined by,
Figure 1
,
Figure 2
, or
9.2.2.3 Power
Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
For a more accurate determination of number of coils possible, use the below equation to calculate ULN2003A
device on-chip power dissipation P
D
:
N
V
´
I
Li
P
=
å
D
OLi
i
=
1
where
•
•
N is the number of channels active together
V
OLi
is the OUT
i
pin voltage for the load current I
Li
. This is the same as V
CE(SAT)
(2)
To ensure reliability of ULN2003A device and the system, the on-chip power dissipation must be lower that or
T
J(MAX)
–
T
A
(
)
PD
(MAX)
=
q
JA
where
•
•
T
J(max)
is the target maximum junction temperature
T
A
is the operating ambient temperature
•
R
θ
JA
is the package junction to ambient thermal resistance
(3)
Limit the die junction temperature of the ULN2003A device to less than 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
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9.2.3 Application
Curves
The characterization data shown in
Figure 23
and
Figure 24
were generated using the ULN2003A device driving
13
12
11
10
9
14
12
10
8
8
7
6
6
5
4
4
3
2
2
1
0
0
-0.004
0
0.004
0.008
Time (s)
0.012
0.016
-0.004
0
0.004
0.008
Time (s)
0.012
0.016
D001
D001
Figure 23. Output Response With Activation of Coil
(Turnon)
Figure 24. Output Response With De-activation of Coil
(Turnoff)
16
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9.3 System
Examples
ULN2002A
V
SS
V
ULQ2003A
V
CC
V
1
2
1
2
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
3
4
3
4
5
5
6
7
8
6
7
8
P-MOS
Output
Lam
Test
TTL
Output
Figure 25. P-MOS to Load
Figure 26. TTL to Load
ULN2004A
ULQ2004A
V
DD
V
V
V
ULQ2003A
CC
1
1
16
15
14
16
2
2
3
15
14
3
4
R
P
13
12
11
10
9
4
5
13
12
11
10
9
5
6
7
8
6
7
8
CMOS
Output
TTL
Output
Figure 27. Buffer for Higher Current Loads
Figure 28. Use of Pullup Resistors to Increase
Drive Current
Copyright © 1976–2016, Texas Instruments Incorporated
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10 Power
Supply Recommendations
This device does not need a power supply. However, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to ensure that the output voltage does not heavily exceed the COM pin
voltage. This discrepancy heavily forward biases the fly-back diodes and causes a large current to flow into
COM, potentially damaging the on-chip metal or over-heating the device.
11 Layout
11.1 Layout
Guidelines
Thin traces can be used on the input due to the low-current logic that is typically used to drive ULN2003A device.
Take care to separate the input channels as much as possible, as to eliminate crosstalk. TI recommends thick
traces for the output to drive whatever high currents that may be needed. Wire thickness can be determined by
the current density of the trace material and desired drive current.
Because all of the channels currents return to a common emitter, it is best to size that trace width to be very
wide. Some applications require up to 2.5 A.
11.2 Layout
Example
1C
2C
1B
2B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
3C
4C
5C
6C
3B
4B
5B
6B
7B
E
10 7C
9
VCOM
GND
Figure 29.
Package Layout
18
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12 Device
and Documentation Support
12.1 Documentation
Support
12.1.1 Related
Documentation
For related documentation, see the following:
12.2 Related
Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
ULN2002A
ULN2003A
ULN2003AI
ULN2004A
ULQ2003A
ULQ2004A
12.3 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1976–2016, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
ULN2002AN
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
N
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
ULN2002AN
ULN2002ANE4
ULN2003AD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
D
D
D
D
D
D
D
D
D
D
D
D
D
N
N
25
40
Pb-Free
(RoHS)
N / A for Pkg Type
ULN2002AN
ULN2003A
ULN2003A
ULN2003A
ULN2003A
ULN2003A
ULN2003A
ULN2003A
ULN2003AI
ULN2003AI
ULN2003AI
ULN2003AI
ULN2003AI
ULN2003AI
ULN2003AIN
ULN2003AIN
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ULN2003ADE4
ULN2003ADG4
ULN2003ADR
ULN2003ADRE4
ULN2003ADRG3
ULN2003ADRG4
ULN2003AID
40
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
40
Green (RoHS
CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Green (RoHS
& no Sb/Br)
ULN2003AIDE4
ULN2003AIDG4
ULN2003AIDR
ULN2003AIDRE4
ULN2003AIDRG4
ULN2003AIN
40
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
2500
2500
2500
25
Green (RoHS
CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Green (RoHS
& no Sb/Br)
CU NIPDAU
Pb-Free
(RoHS)
CU NIPDAU | CU SN
CU NIPDAU
ULN2003AINE4
25
Pb-Free
(RoHS)
N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
15-Apr-2017
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ULN2003AINSR
ULN2003AIPW
ULN2003AIPWE4
ULN2003AIPWG4
ULN2003AIPWR
ULN2003AIPWRG4
ULN2003AN
ACTIVE
SO
NS
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ULN2003AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
PW
PW
PW
PW
PW
N
90
90
Green (RoHS
& no Sb/Br)
UN2003AI
UN2003AI
UN2003AI
UN2003AI
UN2003AI
ULN2003AN
ULN2003AN
ULN2003A
ULN2003A
ULN2003A
UN2003A
UN2003A
UN2003A
UN2003A
ULN2004A
ULN2004A
ULN2004A
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
2000
2000
25
Green (RoHS
CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU | CU SN
CU NIPDAU
Pb-Free
(RoHS)
ULN2003ANE4
ULN2003ANSR
ULN2003ANSRE4
ULN2003ANSRG4
ULN2003APW
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SO
NS
NS
NS
PW
PW
PW
PW
D
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SO
Green (RoHS
& no Sb/Br)
CU NIPDAU
SO
Green (RoHS
& no Sb/Br)
CU NIPDAU
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
ULN2003APWG4
ULN2003APWR
ULN2003APWRG4
ULN2004AD
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
2000
2000
40
Green (RoHS
CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Green (RoHS
& no Sb/Br)
ULN2004ADE4
ULN2004ADG4
SOIC
D
40
Green (RoHS
& no Sb/Br)
SOIC
D
40
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
15-Apr-2017
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-20 to 70
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ULN2004ADR
ULN2004ADRE4
ULN2004ADRG4
ULN2004AN
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
Green (RoHS
CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ULN2004A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
N
N
NS
D
D
D
D
N
D
D
D
D
N
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
ULN2004A
ULN2004A
ULN2004AN
ULN2004AN
ULN2004A
ULQ2003A
ULQ2003A
ULQ2003A
ULQ2003A
ULQ2003A
ULQ2004A
ULQ2004A
ULQ2004A
ULQ2004A
ULQ2004AN
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
ULN2004ANE4
ULN2004ANSR
ULQ2003AD
25
Pb-Free
(RoHS)
N / A for Pkg Type
2000
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
ULQ2003ADG4
ULQ2003ADR
ULQ2003ADRG4
ULQ2003AN
40
Green (RoHS
& no Sb/Br)
2500
2500
25
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
-40 to 85
-40 to 85
ULQ2004AD
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ULQ2004ADG4
ULQ2004ADR
ULQ2004ADRG4
ULQ2004AN
40
Green (RoHS
& no Sb/Br)
2500
2500
25
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
15-Apr-2017
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ULQ2003A, ULQ2004A :
•
NOTE: Qualified Version Definitions:
Automotive – Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
2-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
ULN2003ADR
ULN2003ADR
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2500
2500
2500
2500
2500
2500
2500
2000
2000
2000
2000
2000
2000
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.8
16.4
16.8
16.4
16.4
16.8
16.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
16.4
16.8
16.4
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.9
6.9
6.9
6.9
6.9
6.9
6.5
6.5
6.5
6.5
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
5.6
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
1.6
1.6
1.6
1.6
1.6
1.6
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
ULN2003ADR
SOIC
D
ULN2003ADRG3
ULN2003ADRG4
ULN2003AIDR
ULN2003AIDR
ULN2003AIDRG4
ULN2003AIPWR
ULN2003AIPWR
ULN2003AIPWRG4
ULN2003APWR
ULN2003APWR
ULN2003APWRG4
ULN2004ADR
SOIC
D
SOIC
D
SOIC
D
SOIC
D
SOIC
D
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
PW
PW
D
5.6
5.6
5.6
5.6
5.6
10.3
10.3
10.3
10.3
ULN2004ADR
SOIC
D
ULN2004ADR
SOIC
D
ULN2004ADRG4
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
2-Sep-2016
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
ULN2004ADRG4
ULQ2003ADR
SOIC
SOIC
SOIC
D
D
D
16
16
16
2500
2500
2500
330.0
330.0
330.0
16.4
16.4
16.4
6.5
6.5
6.5
10.3
10.3
10.3
2.1
2.1
2.1
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
ULQ2003ADRG4
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ULN2003ADR
ULN2003ADR
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2500
2500
2500
2500
2500
2500
2500
2000
2000
2000
2000
2000
2000
333.2
364.0
367.0
364.0
333.2
333.2
364.0
333.2
364.0
367.0
367.0
364.0
367.0
367.0
345.9
364.0
367.0
364.0
345.9
345.9
364.0
345.9
364.0
367.0
367.0
364.0
367.0
367.0
28.6
27.0
38.0
27.0
28.6
28.6
27.0
28.6
27.0
35.0
35.0
27.0
35.0
35.0
ULN2003ADR
SOIC
D
ULN2003ADRG3
ULN2003ADRG4
ULN2003AIDR
SOIC
D
SOIC
D
SOIC
D
ULN2003AIDR
SOIC
D
ULN2003AIDRG4
ULN2003AIPWR
ULN2003AIPWR
ULN2003AIPWRG4
ULN2003APWR
ULN2003APWR
ULN2003APWRG4
SOIC
D
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
2-Sep-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ULN2004ADR
ULN2004ADR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
16
16
16
16
16
16
16
2500
2500
2500
2500
2500
2500
2500
367.0
333.2
364.0
367.0
333.2
333.2
367.0
367.0
345.9
364.0
367.0
345.9
345.9
367.0
38.0
28.6
27.0
38.0
28.6
28.6
38.0
ULN2004ADR
ULN2004ADRG4
ULN2004ADRG4
ULQ2003ADR
ULQ2003ADRG4
Pack Materials-Page 3
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