Texas-Instruments-ULN2003LVDR
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ULN2003LV 7
通道中继和电感负载灌电流驱动器
1
特性
3
说明
1
•
7
通道高灌电流驱动器
支持高达
8V
的输出上拉电压
ULN2003LV
是一款针对
TI
生产的广受欢迎的
ULN2003
系列
7
通道达灵顿
(Darlington)
复合晶体管
阵列的低压和低功耗升级产品。
ULN2003LV
下沉式
驱动器特有
7
个低输出阻抗驱动器以支持低压中继和
电感线圈应用。 低阻抗驱动器大大降低了片上功耗；
对于典型
3V
中继，功率耗散低了多达
5
倍。
ULN2003LV
驱动器与相似封装内的
ULN2003
系列器
件引脚到引脚兼容。
•
•
•
支持
3V
至
5V
的宽范围中继和电感线圈
0.4V
（典型值）的低输出
VOL
–
在
3.3V
的逻辑输入上，每通道具有
100mA
（典型值）的电流吸收能力
(1)
–
在
5.0V
的逻辑输入上，每通道具有
140mA
（典型值）的电流吸收能力
(1)
•
•
•
•
与
3.3V
和
5.0V
微控制器和逻辑接口兼容
用于电感反冲保护的内部续流二极管
输入下拉电阻可实现三态输入驱动器
ULN2003LV
支持
3.3V
至
5V CMOS
逻辑输入接口，
从而使得此器件与大范围的微控制器和其它逻辑接口兼
容。
ULN2003LV
特有一个改进的输入接口，此接口
可以大大降低取自外部驱动器的输入
DC
电流。
ULN2003LV
特有一个输入
RC
缓冲器，此缓冲器能够
极大地改进此器件在嘈杂运行条件下的性能。
用来消除嘈杂环境中寄生运行的输入电阻电容
(RC)
缓冲器
•
•
•
低输入和输出泄漏电流
易于使用的并行接口
ULN2003LV
通道输入特有一个内部输入下拉电阻器从
而可实现三态输入逻辑。
ULN2003LV
也可以支持其
他逻辑输入电平，例如
TTL
和
1.8V
，相关详细信息请
静电放电
(ESD)
保护性能超过
JESD 22
规范要求
–
2kV
人体放电模式
(HBM)
，
500V
组件充电模式
(CDM)
•
采用
16
引脚小外形尺寸集成电路
(SOIC)
和薄型小
外形尺寸
(TSSOP)
封装
ULN2003LV
通过将几条相邻的并联通道相组合来提供
增加电流吸收能力的灵活性。 在通常情况下，当所有
7
个通道并联时，
ULN2003LV
能够支持高达
1.0A
的
负载电流。 此外，
ULN2003LV
还可用于各类需要灌
电流驱动器的应用，例如驱动
LED
和逻辑电平转换。
(1)
总灌电流可能会受到内部结温、绝对最大电流等的限制
–
详细
信息请参见电气规范部分。
2
应用
•
在多种电信、消费类、和工业应用中的中继和电感
负载驱动器
•
•
照明灯和
LED
显示
逻辑电平转换器
器件型号
ULN2003LVDR
ULN2003LVPWR
封装
SOIC (16)
TSSOP (16)
封装尺寸（标称值）
3.90mm x 9.90mm
4.40mm x 5.00mm
(1)
要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化功能图
OUT1
16
1
2
3
4
5
6
IN1
IN2
15
OUT2
14
OUT3
IN3
OUT4
OUT5
13
12
11
10
IN4
IN5
IN6
OUT6
OUT7
COM
7
8
IN7
9
GND
ULN2003LV TSSOP/SOIC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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目录
1
2
3
4
5
6
8
9
7
4
修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2012) to Revision B
Page
•
已添加
引脚配置和功能
部分，
ESD
额定值
表，
特性描述
部分，
器件功能模式
，
应用和实施
部分，
电源相关建议
部分，
2
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5 Pin
Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
1
16
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
IN1
IN2
2
3
15
14
IN3
16-Pin
4
5
6
7
8
13
12
11
10
9
IN4
SOIC/TSSOP
IN5
IN6
IN7
GND
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
IN1
NO.
1
Input
Input
IN2
2
IN3
3
Input
IN4
4
Input
Logic Input Pins IN1 through IN7
Ground Reference Pin
IN5
5
Input
IN6
6
Input
IN7
7
Input
GND
COM
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
8
Ground
Output
Output
Output
Output
Output
Output
Output
Output
9
Internal Free-Wheeling Diode Common Cathode Pin
10
11
12
13
14
15
16
Channel Output Pins OUT7 through OUT1
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6 Specifications
6.1 Absolute
Maximum Ratings
Specified at T
J
= –40°C to 125°C unless otherwise noted.
(1)
MIN
MAX
UNIT
V
V
IN
Pins IN1- IN7 to GND voltage
–0.3
5.5
8
V
OUT
V
COM
Pins OUT1 – OUT7 to GND voltage
Pin COM to GND voltage
V
8
V
Maximum GND-pin continuous current (T
J
> +125°C)
Maximum GND-pin continuous current (T
J
< +100°C)
700
1.0
0.58
0.45
85
mA
A
I
GND
16 Pin – SOIC
16 Pin -TSSOP
W
P
D
Total device power dissipation at T
A
= 85°C
W
T
A
Operating free-air ambient temperature
Operating virtual junction temperature
Storage temperature
–40
–55
–55
°C
°C
°C
T
J
150
150
T
stg
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions
. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD
Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
Electrostatic
discharge
V
(ESD)
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
8
UNIT
V
V
OUT
V
COM
Channel off-state output pullup voltage
COM pin voltage
8
V
VINx = 3.3 V
VINx = 5.0 V
100
(1)
140
(1)
125
I
OUT(ON)
T
J
Per channel continuous sink current
Operating junction temperature
mA
ºC
–40
6.4 Thermal
Information
ULN2003LV
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
UNIT
16 PINS
112
69
16 PINS
142
74
R
θ
JA
R
θ
JC(top)
R
θ
JB
ψ
JT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
69
87
Junction-to-top characterization parameter
Junction-to-board characterization parameter
33
22
ψ
JB
69
87
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
4
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6.5 Electrical
Characteristics
Specified over the recommended junction temperature range T
J
= –40°C to 125°C unless otherwise noted. Typical values are
at T
J
= 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUTS IN1 THROUGH IN7 PARAMETERS
V
I(ON)
IN1–IN7 logic high input voltage
V
pull-up
= 3.3 V, R
pullup
= 1 k
Ω
, I
OUTX
= 3.2 mA
1.65
V
V
V
pullup
= 3.3 V, R
pullup
= 1 k
Ω
,
(I
OUTX
= <5 µA)
V
I(OFF)
IN1–IN7 logic low input voltage
0.4
12
0.6
I
I(ON)
IN1–IN7 ON state input current
IN1–IN7 OFF state input leakage
V
pullup
= 3.3 V, VIN
x
= 3.3 V
V
pullup
= 3.3 V, VIN
x
= 0 V
25
µA
nA
I
I(OFF)
250
OUTPUTS OUT1 THROUGH OUT7 PARAMETERS
V
INX
= 3.3 V, I
OUTX
= 50 mA
V
INX
= 3.3 V, I
OUTX
= 100 mA
V
INX
= 5.0 V, I
OUTX
= 100 mA
V
INX
= 5.0 V, I
OUTX
= 140 mA
V
INX
= 3.3 V, V
OUTX
= 0.4 V
V
INX
= 5.0 V, V
OUTX
= 0.4 V
V
INX
= 0 V, V
OUTX
= V
COM
= 8 V
0.17
0.36
0.26
0.40
100
0.24
0.49
0.42
V
OL(VCE-SAT)
OUT1–OUT7 low-level output voltage
V
OUT1–OUT7 ON-state continuous current
(1)
at V
OUTX
= 0.4V
(2)
80
95
I
OUT(ON)
mA
µA
140
I
OUT(OFF)(ICEX)
OUT1–OUT7 OFF-state leakage current
0.17
FREE-WHEELING DIODE PARAMETERS
(3
)
(
4)
VF
Forward voltage drop
I
F-peak
= 140 mA, VF = V
OUTx
– V
COM
,
1.2
V
I
F-peak
Diode peak forward current
140
mA
(1) The
typical continuous current rating is limited by V
OL
= 0.4V. Whereas, absolute maximum operating continuous current may be limited
by the Thermal Performance.parameters listed in the Dissipation Rating Table and other Reliability parameters listed in the
Recommended Operating ConditionsTable.
(3) Not
rated for continuous current operation – for higher reliability use an external freewheeling diode for inductive loads resulting in more
than specified maximum free-wheeling. diode peak current across various temperature conditions
(4) Specified
by design only.
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6.6 Switching
Characteristics
over operating free-air temperature range (unless otherwise noted)
(1
)
(
2)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
15
45
80
300
9
MAX
UNIT
V
INX
= 3.3V, V
pull-up
= 3.3 V, R
pull-up
= 50
Ω
V
INX
= 5.0V, V
pull-up
= 5 V, R
pull-up
= 1 k
Ω
V
INX
= 3.3V, V
pull-up
= 3.3 V, R
pull-up
= 50
Ω
V
INX
= 5.0V, V
pull-up
= 5 V, R
pull-up
= 1k
Ω
OUT1–OUT7 logic high propagation
delay
t
PHL
ns
t
PLH
OUT1–OUT7 logic low propagation delay
ns
R
PD
ζ
IN1–IN7 input pull-down Resistance
IN1–IN7 Input filter time constant
OUT1–OUT7 output capacitance
210
390
k
Ω
ns
pF
C
OUT
V
INX
= 3.3 V, V
OUTX
= 0.4 V
15
(1) Rise
and Fall propagation delays, t
PHL
and t
PLH
, are measured between 50% values of the input and the corresponding output signal
amplitude transition.
(2) Specified
by design only.
6.7 Dissipation
Ratings
(1
)
(
2)
See
DERATING
FACTOR ABOVE
T
A
= 25ºC
(3)
BOARD
PACKAGE
R
θ
JC
R
θ
JA
T
A
< 25°C
T
A
= 70°C
T
A
= 85°C
High-K
High-K
16-Pin SOIC
69°C/W
74°C/W
112°C/W
142°C/W
8.88 mW/ºC
7.11 mW/ºC
1.11 W
0.88 W
0.71 W
0.56 W
0.58 W
0.45 W
16-Pin TSSOP
(1) Maximum
dissipation values for retaining device junction temperature of 150°C
(2) Refer
to TI’s design support web page at
www.ti.com/thermal
for improving device thermal performance
(3) Operating
at the absolute T
J-max
of 150°C can affect reliability– for higher reliability it is recommended to ensure T
J
< 125°C
6
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6.8 Typical
Characteristics
T
A
= +25ºC
Figure 1. Load Current 1-Channel; VOL=0.4V
Figure 2. Load Current 7-Channels in Parallel; VOL=0.4V
Figure 3. VOL versus IOUT VIN = 1.8V, 3.3V, 5.0V
Figure 4. VOL versus IOUT 2-Channels in Parallel; VOL=0.4V
Figure 5. Freewheeling Diode VF vs IF
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7 Detailed
Description
7.1 Overview
ULN2003LV device is a seven-channel, low-side NMOS driver capable of driving 100-mA load with 3-V input
drive voltage through each channel. This device can drive low voltage can drive low-voltage relays, LEDs or
resistive loads. The ULN2003LV supports 3.3-V to 5-V CMOS logic input interface thus making it compatible to a
wide range of micro-controllers and other logic interfaces. The ULN2003LV features an improved input interface
that minimizes the input DC current drawn from the external drivers. The ULN2003LV features an input RC
snubber that greatly improves its performance in noisy operating conditions. The ULN2003LV channel inputs
feature an internal input pulldown resistor thus allowing input logic to be tri-stated. The ULN2003LV may also
support other logic input levels, for example, TTL and 1.8 V.
7.2 Functional
Block Diagram
/ha
hÜÇó
w/ Cilꢂerꢃ{nuꢄꢄer
wLb=3k
Q
Lbó
bC9Ç
tull-doꢀn
300k
Q
/Lb= ꢁpC
9{5
9{5
Figure 6.
Channel Block Diagram
7.3 Feature
Description
7.3.1 TTL
and Other Logic Inputs
ULN2003LV input interface is specified for standard 3-V and 5-V CMOS logic interface. However, ULN2003LV
input interface may support other logic input levels as well. Refer to
Figure 1
and
Figure 2
to establish VOL and
the corresponding typical load current levels for various input voltage
ranges.
The
Application
Information
section
shows an implementation to drive 1.8-V relays using ULN2003LV.
7.3.2 Input
RC Snubber
ULN2003LV features an input RC snubber that helps prevent spurious switching in noisy environment. Connect
an external 1-k
Ω
to 5-k
Ω
resistor in series with the input to further enhance the noise tolerance of the
ULN2003LV.
8
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Feature Description
(continued)
7.3.3 High-Impedance
Input Drivers
ULN2003LV features a 300-k
Ω
input pulldown resistor. The presence of this resistor allows the input drivers to
be tri-stated. When a high-impedance driver is connected to a channel input the ULN2003LV detects the channel
input as a low-level input and remains in the OFF position. The input RC snubber helps improve noise tolerance
when input drivers are in the high-impedance state.
7.4 Device
Functional Modes
As shown in
Figure 6
, each output of the ULN2003LV features an internal free-wheeling diode connected in a
common-cathode configuration
at the COM pin. The ULN2003LV provides flexibility of increasing current sink
capability through combining several adjacent channels in parallel. Under typical conditions the ULN2003LV can
support up to 1.0 A of load current when all 7-channels are connected in parallel. The ULN2003LV can also be
used in a variety of other applications requiring a sink drivers.
Table 1. ULN2003LV Function Table
(1)
INPUT (IN1 – IN7)
OUTPUT (OUT1–OUT7)
L
H
Z
Z
L
Z
(1) L
= Low-level (GND); H= High-level; Z= High-impedance
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8 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application
Information
The typical application of the ULN2003LV is a sink driver. The ULN2003LV provides a low-impedance path to
GND for driving external peripherals or open-drain signals. If all 7 channels are tied together, the ULN2003 can
sink up to 1 A of current in these applications
8.2 Typical
Application
To use ULN2003LV as an open-collector or an open-drain inverting logic level shifter configure the device as
shown in
Figure 7
. The ULN2003LV’s each channel input and output logic levels can also be set independently.
When
using different
channel input and output logic voltages connect the ULN2003LV COM pin to the maximum
voltage.
VSUP Level Shift Supply(Up t
o
8
V
)
Logic Inputs
ULN2003
L
V
(1.8V to 5V)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
OUT1_VSUP
OUT2_VSUP
OUT3_VSUP
OUT4_VSUP
OUT5_VSUP
OUT6_VSUP
OUT7_VSUP
Figure 7.
ULN2003LV as Inverting Logic Level Shifter
8.2.1 Design
Requirements
ULN2003LV can be used in digital application requiring logic level shifting up to 8 V at the output side.
Applications requiring a level shift operation from 1.8 V to 8 V. Since device pulls the output transistor low when
input is high, this configuration is useful for applications requiring inverting logic with the level shifting operation.
8.2.2 Detailed
Design Procedure
To operate in level shifting operation certain time aspects should be kept in mind. Depending on the pull up
resistors at the output ULN2003LV exhibits different propagation delays. The choice of pull up resistor is
dependent on the drive required at the output. The device can pull output to ground with the output transistor but
to transition from low to high output resistor plays a critical role. If high drive at output is required a lower
R
Pullup
= OUT1_VSUP / I
Drive
(1)
10
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Typical Application (continued)
For example, a drive of 5 mA is required at the output for 1.8-V to 5-V translation application.
R
Pullup
= OUT1_VSUP / I
Drive
= 5/0.005 =1 K
(2)
8.2.3 Application
Curve
Figure 8.
ULN2003LV Iref vs VOUTx
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8.3 System
Examples
8.3.1 Max
Supply Selector
The
Figure 9
implements a max supply selector along with a 4-channel logic level shifter using a single
ULN20003LV.
This setup configures ULN2003LV’s channel clamp diodes OUT5 – OUT7 in a diode-OR
configuration and thus the maximum supply among VSUP1, VSUP2 and VSUP3 becomes available at the COM
pin. The maximum supply is then used as a pull-up voltage for level shifters. Limit the net GND pin current to
less than 100mA DC to ensure reliability of the conducting diode. The unconnected inputs IN5-IN7 are pulled to
GND potential through 300k
Ω
internal pull-down resistor.
VSU
P
_
MAX
Logic Inputs
(1.8V to 5V)
ULN2003
L
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
VSUP3
VSUP2
VSUP1
VSUP_MAX
VSUP_MAX = Max of {VSUP1, VSUP2, VSUP3} – VF
VF = Diode forward drop@ Total ground-pin current
Figure 9.
ULN2003LV as Max Supply Selector
12
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System Examples (continued)
8.3.2 Constant
Current Generation
sources. The current
flowing through
the resistor R1 is copied on all other channels. To increase the current
sourcing connect several output channels in parallel. To ensure best current copying set voltage drop across
connected load such that VOUTx matches to VOUT7.
VSUP
VI
N
(
Up t
o
5
.5V)
VSUP LED Supply(Up to 8V)
R1 = (VIN-VOUT7)/IRE
F
7
Use plot to estimate VOU
T
7
f
or the desired IRE
F
7
R1
OUT7
ULN2003LV
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OU
T
1
OU
T
2
OU
T
3
OU
T
4
OU
T
5
OU
T
6
OU
T
7
COM
OU
T
7
VSUP
Figure 10.
ULN2003LV as a Constant Current Driver
Copyright © 2012–2015, Texas Instruments Incorporated
13
ZHCS846B
–
A
PRIL 201
2
–
R
EVISED JUNE 2015
System Examples (continued)
8.3.3 Unipolar
Stepper Motor Driver
The
Figure 11
shows an implementation of ULN2003LV for driving a uniploar stepper motor. The unconnected
input
channels
can be used for other functions. When an input pin is left open the internal 300k
Ω
pull down
resistor pulls the respective input pin to GND potential. For higher noise immunity use an external short across
an unconnected input and GND pins.
Motor
Motor Supply(Up t
o
8
V
)
VSUP
Motor Control Pulses
(3V to 5V)
ULN2003
L
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
Phase_A
Phase_C
Phase_B
Phase_D
VSUP
Figure 11.
ULN2003LV as a Stepper Motor Driver
8.3.4 NOR
Logic Driver
Figure 12
shows a NOR Logic driver implementation using ULN2003LV. The output channels sharing a common
pull-up resistor
implement a logic NOR of the respective channel inputs. The LEDs connected to outputs OUT5-
OUT7 light up when any of the inputs IN5-IN7 is logic-high ( > VIH).
VSUP
Logic Inputs
(1.8V to 5V)
ULN2003
L
V
OUT1
VSUP
IN1 NOR IN2
IN3 NOR IN4
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
IN
1
N
OR IN2 NOR I
N
3
VSUP
Figure 12.
ULN2003LV as a NOR driver
14
Copyright © 2012–2015, Texas Instruments Incorporated
ZHCS846B
–
A
PRIL 201
2
–
R
EVISED JUNE 2015
System Examples (continued)
8.3.5 1.8-V
Relay Driver
To drive lower voltage relays, like 1.8V, connect two or more adjacent channels in parallel as shown in
Figure 13
.
Connecting several channels in parallel lowers the channel output resistance and thus minimizes VOL
for a fixed
current.
VSUP
1.8V Relays
ULN2003
L
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
1
.
8
V Logic
1
.
8
V Logic
1.8V Logic
VSUP
Figure 13.
ULN2003LV Driving 1.8V Relays
Copyright © 2012–2015, Texas Instruments Incorporated
15
ZHCS846B
–
A
PRIL 201
2
–
R
EVISED JUNE 2015
9 Power
Supply Recommendations
The COM pin is the power supply pin of this device to power the gate drive circuitry. Although not required but
depending on the power supply, TI recommends to put a bypass capacitor of 100 nF across the Vcom pin and
Gnd.
10 Layout
10.1 Layout
Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive ULN2003LV. Take
care to separate the input channels as much as possible, as to eliminate cross-talk. Thick traces are
recommended for the output, in order to drive high currents that may be needed. Wire thickness can be
determined by the trace material’s current density and desired drive current. Since all of the channels currents
return to a common ground, it is best to size that trace width to be very wide. Some applications require up to 1
A.
10.2 Layout
Example
Lb1
Lb2
Lb3
Lb4
Lb5
Lb6
Lb7
Dnd
hÜÇ1
hÜÇ2
hÜÇ3
hÜÇ4
hÜÇ5
hÜÇ6
hÜÇ7
/ha
16
1
2
15
3
4
14
13
5
12
11
10
9
6
7
8
Cbypass 0.1uF
Figure 14.
Layout Example Recommendation
10.3 On-Chip
Power Dissipation
N
V
´
I
Li
P
=
å
D
OLi
i
=
1
where
•
•
N is the number of channels active together.
V
OLi
is the OUT
i
pin voltage for the load current I
Li
.
(3)
16
Copyright © 2012–2015, Texas Instruments Incorporated
ZHCS846B
–
A
PRIL 201
2
–
R
EVISED JUNE 2015
10.4 Thermal
Considerations
TI recommends to limit ULN2003LV IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate the
maximum allowable on-chip power dissipation for a target IC junction temperature:
T
J(MAX)
–
T
A
(
)
PD
(MAX)
=
q
JA
where
•
•
T
J(MAX)
is the target maximum junction temperature.
T
A
is the operating ambient temperature.
•
R
θ
JA
is the package junction to ambient thermal resistance.
(4)
10.4.1 Improving
Package Thermal Performance
The package R
θ
JA
value under standard conditions on a High-K board is listed in the
Dissipation Ratings
. R
θ
JA
value depends on the PCB layout. An external heat sink and/or a cooling mechanism,
like a cold air fan, can
help
reduce R
θ
JA
and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal
for a general guidance on improving device thermal performance.
版权
© 2012–2015, Texas Instruments Incorporated
17
ZHCS846B
–
A
PRIL 201
2
–
R
EVISED JUNE 2015
11
器件和文档支持
11.1
社区资源
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
11.2
商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
11.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12
机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权
© 2012–2015, Texas Instruments Incorporated
重要声明
德州仪器
(TI)
及其下属子公司有权根据
JESD46
最新标准
,
对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48
最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息
,
并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的
TI
销售条款与条件。
TI
保证其所销售的组件的性能符合产品销售时
TI
半导体产品销售条件与条款的适用规范。仅在
TI
保证的范围内，且
TI
认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI
对应用帮助或客户产品设计不承担任何义务。客户应对其使用
TI
组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI
不对任何
TI
专利权、版权、屏蔽作品权或其它与使用了
TI
组件或服务的组合设备、机器或流程相关的
TI
知识产权中授予 的直接或隐含权
限作出任何保证或解释。
TI
所发布的与第三方产品或服务有关的信息，不能构成从
TI
获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是
TI
的专利权或其它 知识产权方面的许可。
对于
TI
的产品手册或数据表中
TI
信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。
TI
对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售
TI
组件或服务时，如果对该组件或服务参数的陈述与
TI
标明的参数相比存在差异或虚假成分，则会失去相关
TI
组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。
TI
对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由
TI
提供，但他们将独力负责满足与其产品及在其应用中使用
TI
产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何
TI
组件而
对
TI
及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对
TI
组件进行特别的促销。
TI
的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI
组件未获得用于
FDA Class III
（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些
TI
特别注明属于军用等级或
“
增强型塑料
”
的
TI
组件才是设计或专门用于军事
/
航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的
TI
组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI
已明确指定符合
ISO/TS16949
要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到
ISO/TS16949
要
求，
TI
不承担任何责任。
产品
应用
数字音频
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP®
产品
DSP –
数字信号处理器
时钟和计时器
接口
工业应用
医疗电子
安防应用
汽车电子
视频和影像
逻辑
电源管理
微控制器
(MCU)
RFID
系统
OMAP
应用处理器
无线连通性
德州仪器在线技术支持社区
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道
1568
号，中建大厦
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楼邮政编码：
200122
Copyright © 2015,
德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
12-Sep-2015
PACKAGING INFORMATION
Orderable Device
ULN2003LVDR
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
D
16
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
UN2003LV
UN2003LV
ULN2003LVPWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
12-Sep-2015
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
11-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
ULN2003LVDR
SOIC
D
16
16
2500
2000
330.0
330.0
16.8
12.4
6.5
6.9
10.3
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
ULN2003LVPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
11-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ULN2003LVDR
SOIC
D
16
16
2500
2000
364.0
364.0
364.0
364.0
27.0
27.0
ULN2003LVPWR
TSSOP
PW
Pack Materials-Page 2
重要声明
德州仪器
(TI)
及其下属子公司有权根据
JESD46
最新标准
,
对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48
最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息
,
并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的
TI
销售条款与条件。
TI
保证其所销售的组件的性能符合产品销售时
TI
半导体产品销售条件与条款的适用规范。仅在
TI
保证的范围内，且
TI
认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI
对应用帮助或客户产品设计不承担任何义务。客户应对其使用
TI
组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI
不对任何
TI
专利权、版权、屏蔽作品权或其它与使用了
TI
组件或服务的组合设备、机器或流程相关的
TI
知识产权中授予 的直接或隐含权
限作出任何保证或解释。
TI
所发布的与第三方产品或服务有关的信息，不能构成从
TI
获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是
TI
的专利权或其它 知识产权方面的许可。
对于
TI
的产品手册或数据表中
TI
信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。
TI
对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售
TI
组件或服务时，如果对该组件或服务参数的陈述与
TI
标明的参数相比存在差异或虚假成分，则会失去相关
TI
组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。
TI
对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由
TI
提供，但他们将独力负责满足与其产品及在其应用中使用
TI
产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何
TI
组件而
对
TI
及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对
TI
组件进行特别的促销。
TI
的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI
组件未获得用于
FDA Class III
（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些
TI
特别注明属于军用等级或
“
增强型塑料
”
的
TI
组件才是设计或专门用于军事
/
航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的
TI
组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI
已明确指定符合
ISO/TS16949
要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到
ISO/TS16949
要
求，
TI
不承担任何责任。
产品
应用
数字音频
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP®
产品
DSP –
数字信号处理器
时钟和计时器
接口
工业应用
医疗电子
安防应用
汽车电子
视频和影像
逻辑
电源管理
微控制器
(MCU)
RFID
系统
OMAP
应用处理器
无线连通性
德州仪器在线技术支持社区
IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
