Texas-Instruments-ULN2803CDWR
| Part # | Texas-Instruments-ULN2803CDWR |
Download  | Texas-Instruments-ULN2803CDWR |
SLRS076
– AUGUST 2022
ULN2803C Darlington Transistor Array
1 Features
3 Description
•
500-mA-rated collector current
(single output)
High-voltage outputs: 50 V
Output clamp diodes
The ULN2803C device is a 50-
V
,
5
00-mA Darlington
transistor array. The device consists of eight NPN
Darlington pairs that feature high-voltage outputs with
common-cathode clamp diodes for switching inductive
loads. The collector-current rating of each Darlington
pair is 500 mA. The Darlington pairscan be connected
in parallel for higher current capability.
•
•
•
Inputs compatible with various types of logic
2 Applications
•
•
•
•
•
•
•
Applications include relay drivers, hammer drivers,
lamp drivers, display drivers (LED and gas discharge),
line drivers, and logic buffers. The ULN2803C device
has a 2.7-kΩ series base resistor for each Darlington
pair for operation directly with TTL or 5-V CMOS
devices.
Relay, solenoid, and lamp driving
Stepper motor driving
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ULN2803CDW
DW (SOIC, 20)
12.80 mm × 7.50 mm
(1) For
all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLRS076
– AUGUST 2022
Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2022
*
Initial release.
Copyright © 2022
T
e
xas Instruments Incorporated
2
SLRS076
– AUGUST 2022
5 Pin Configuration and Functions
Figure 5-1. DW Package 20-Pin SOIC Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
1B
NO.
1
2B
2
3B
3
4B
4
I
Channel 1 through 8 Darlington base input
5B
5
6B
6
7B
7
8B
8
1C
20
19
18
17
16
15
14
13
9
2C
3C
4C
O
Channel 1 through 8 Darlington collector output
5C
6C
7C
8C
GND
COM
—
I/O
—
Common emitter shared by all channels (typically tied to ground)
Common cathode node for flyback diodes (required for inductive loads)
No connect pin
12
NC
10, 11
Copyright © 2022
T
e
xas Instruments Incorporated
3
SLRS076
– AUGUST 2022
6 Specifications
6.1 Absolute Maximum Ratings
MIN
MAX
50
UNIT
V
V
CE
V
I
Collector-emitter voltage
30
V
Peak collector current
500
500
–2.5
150
150
mA
mA
A
I(clamp) Output
clamp current
T
o
tal substrate-terminal current
Junction temperature
Storage temperature
T
J
–65
–65
°C
°C
T
stg
(1) Operation
outside the Absolute Maximum Ratings may cause permanent device damage. Absolute MaximumRatings do not imply
functional operation of the device at these or any other conditions beyond those listedunder Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but withinthe Absolute Maximum Ratings, the device may not be fully functional,
and this may affect device reliability,functionality, performance, and shorten the device lifetime.
(2) All
voltage values, unless otherwise noted, are with respect to the emitter/substrate terminal GND.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
(ESD)
Electrostatic discharge
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
UNIT
V
CE
T
A
Collector-emitter voltage
Ambient temperature
50
85
V
–40
°C
6.4 Thermal Information
ULN2803C
DW (SOIC)
20 PINS
UNIT
R
θJA
Junction-to-ambient thermal resistance
68.8
34.3
°C/W
°C/W
R
θJC(top)
R
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
37.5
10.7
37.0
N/A
°C/W
°C/W
°C/W
°C/W
ψ
JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψ
JB
R
θJC(bot)
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report.
Copyright © 2022
T
e
xas Instruments Incorporated
4
SLRS076
– AUGUST 2022
6.5 Electrical Characteristics
at T
A
= 25°C free-air temperature (unless otherwise noted)
ULN2803C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
V
CE
= 50
V
,
I
CEX
Collector cutoff current
I
I
= 0
50
μA
μA
V
CE
= 50
V
,
T
A
= 70°C
I
C
= 500 μA,
I
I(off)
I
I(on)
Off-state input current
Input current
50
65
V
I
= 3.85
V
,
I
C
= 200 mA
I
C
= 250 mA
I
C
= 300 mA
0.93
1.35 mA
2.4
V
CE
= 2
V
,
V
I(on)
On-state input voltage
2.7
3
V
I
I
= 250 μA,
I
C
= 100 mA
I
C
= 200 mA
I
C
= 350 mA
0.9
1
1.1
1.3
1.6
I
I
= 350 μA,
V
CE(sat)
Collector-emitter saturation voltage
V
I
I
= 500 μA,
1.3
I
R
Clamp diode reverse current
Clamp diode forward voltage
Input capacitance
V
R
= 50
V
,
I
F
= 350 mA
V
I
= 0,
f = 1 MHz
50
2
μA
V
V
F
C
i
1.7
15
25
pF
6.6 Switching Characteristics
T
A
= 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
130
20
MAX UNIT
t
PLH
t
PHL
V
OH
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
High-level output voltage after switching
V
S
= 50
V
,
C
L
= 15 p
F
,
R
L
= 163 Ω,
ns
V
S
– 20
mV
Copyright © 2022
T
e
xas Instruments Incorporated
5
SLRS076
– AUGUST 2022
6.7 Typical Characteristics
μ
μ
μ
μ
μ
μ
Figure 6-1. Collector-Emitter Saturation Voltage vs
Collector Current (One Darlington)
Figure 6-2. Collector-Emitter Saturation Voltage
vs Total Collector Current (Two Darlingtons in
Parallel)
Copyright © 2022
T
e
xas Instruments Incorporated
6
SLRS076
– AUGUST 2022
7 Parameter Measurement Information
Open
V
CE
Open V
CE
I
C
I
I
CEX
I(off)
Open
Figure 7-1. I
CEX
Test Circuit
Figure 7-2. I
I(off)
Test Circuit
Open
Open
I
I
I
C
V
I
V
I
Open
V
CE
Figure 7-3. I
I(on)
Test Circuit
Figure 7-4. V
I(on)
Test Circuit
Open
V
R
I
C
h
I
=
FE
I
R
I
I
I
I
C
Open
V
CE
Figure 7-6. I
R
Test Circuit
Figure 7-5. h
FE
, V
CE(sat)
Test Circuit
I
F
V
F
Open
Figure 7-7. V
F
Test Circuit
Copyright © 2022
T
e
xas Instruments Incorporated
7
SLRS076
– AUGUST 2022
Input
Open
V
S
= 50 V
R =
163
Ω
L
Pulse
Generator
(see Note A)
Output
C =
15 pF
L
(see Note B)
Test Circuit
<5 ns
<10 ns
V
IH
(see Note C)
90%
50%
90%
50%
Input
10%
10%
0
0.5
µ
s
t
t
PLH
PHL
V
OH
50%
50%
Output
Voltage Waveforms
A. The
pulse generator has the following characteristics: PRR = 12.5 kHz, Z
O
= 50 Ω.
B. C
L
includes probe and jig capacitance.
C. V
IH
= 3
V
.
Figure 7-8. Propagation Delay Times
Copyright © 2022
T
e
xas Instruments Incorporated
8
SLRS076
– AUGUST 2022
V
S
Input
2 mH
163
Ω
Pulse
Generator
(see Note A)
Output
C =
15 pF
L
(see Note B)
Test Circuit
<5 ns
<10 ns
V
IH
(see Note C)
90%
1.5 V
90%
1.5 V
Input
10%
10%
0
40
µ
s
V
OH
Output
Voltage Waveforms
A. The
pulse generator has the following characteristics: PRR = 12.5 kHz, Z
O
= 50 Ω.
B. C
L
includes probe and jig capacitance.
C. V
IH
= 3
V
.
Figure 7-9. Latch-Up Test
Copyright © 2022
T
e
xas Instruments Incorporated
9
SLRS076
– AUGUST 2022
8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This feature is due
to its integration of eight Darlington transistors that are capable of sinking up to 500 mA and wide GPIO range
capability.
The ULN2803C is comprised of eight high voltage, high current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs.
T
o
m
aximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULN2803C has a series base resistor to each Darlington pair, thus
allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3
V
.
T
he ULN2803C
offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs.
Applications requiring sink currents beyond the capability of a single output can be accommodated by paralleling
the outputs.
8.2 Functional Block Diagram
COM
Output C
2.7 k
Ω
Input B
7.2 k
Ω
3 k
Ω
E
8.3 Feature Description
Each channel of ULN2803C consists of Darlington connected NPN transistors. This connection creates the
effect of a single transistor with a very-high current gain. The very high β allows for high output current drive with
a very-low input current, essentially equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-kΩ resistor connected between the input and
base of the predriver Darlington NPN.
The diodes connected between the output and COM pin are used to suppress the kickback voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kickback diode.
In normal operation, the diodes on base and collector pins to emitter are reverse biased. If these diodes are
forward biased, internal parasitic NPN transistors draw (a nearly equal) current from other (nearby) device pins.
8.4 Device Functional Modes
8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2803C can drive inductive loads and suppress the
kickback voltage through the internal free wheeling diodes.
8.4.2 Resistive Load Drive
When driving resistive loads, COM can be left unconnected or connected to the load voltage supply. If multiple
supplies are used, connect to the highest voltage supply.
Copyright © 2022
T
e
xas Instruments Incorporated
10
SLRS076
– AUGUST 2022
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
ULN2803C is typically used to drive a high-voltage or current peripherals from an MCU or logic device that
cannot tolerate these conditions. The following design is a common application of ULN2803C, driving inductive
loads. This includes motors, solenoids, and relays. Each load type can be modeled by what is seen in
Figure
9-1
.
9.2 Typical Application
Figure 9-1. ULN2803C as Inductive Load Driver
Copyright © 2022
T
e
xas Instruments Incorporated
11
SLRS076
– AUGUST 2022
9.2.1 Design Requirements
Table 9-1. Design Parameters
DESIGN PARAMETER
GPIO voltage
EXAMPLE VALUE
3.3 or 5 V
Coil supply voltage
Number of channels
12 to 50 V
8
Output current (R
COIL
)
20 to 300 mA per channel
100%
Duty cycle
9.2.2 Detailed Design Procedure
When using ULN2803C in a coil driving application, determine the following:
•
•
•
•
Input voltage range
T
e
mperature range
Output and drive current
Power dissipation
9.2.2.1 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance, and output low voltage (V
OL
or
V
CE(SAT)
).
I
COIL
= (V
SUP
– V
CE(SAT)
) / R
COIL
(1)
9.2.2.2 Output Low Voltage
The output low voltage (V
OL
) is the same thing as V
CE(SAT)
and can be determined by
Figure 6-1
,
Figure 6-2
, or
9.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation.
T
o
d
etermine the
N
V
´
I
Li
P
=
å
D
OLi
i
=
1
(2)
where
•
•
N is the number of channels active together.
V
OLi
is the OUT
i
pin voltage for the load current I
Li
. This is the same as V
CE(SAT)
.
To
e
nsure the reliability of ULN2803C and the system, the on-chip power dissipation must be lower that or equal
T
–
T
A
(
)
J MAX
(
)
P
D
(
MAX
=
)
q
JA
(3)
where
•
•
•
T
J(MAX)
is the target maximum junction temperature.
T
A
is the operating ambient temperature.
θ
JA
is the package junction to ambient thermal resistance.
Copyright © 2022
T
e
xas Instruments Incorporated
12
SLRS076
– AUGUST 2022
TI recommends to limit the ULN2803C IC die junction temperature to < 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
9.2.3 Application Curves
The following curves are generated with ULN2803C driving an OMRON G5NB relay – V
in
= 5.0 V; V
sup
= 12 V
and R
COIL
= 2.8 kΩ.
13
12
11
10
9
14
12
10
8
8
7
6
6
5
4
4
3
2
2
1
0
-0.004
0
-0.004
0
0.004
0.008
Time (s)
0.012
0.016
0
0.004
0.008
Time (s)
0.012
0.016
D001
D001
Figure 9-2. Output Response with Activation of
Coil (Turn-On)
Figure 9-3. Output Response with De-activation of
Coil (Turn Off)
9.3 Power Supply Recommendations
This devicedoes not need a power supply; however, the COM pin is typically tied to the system power supply.
With this case, make sure that the output voltage does not heavily exceed the COM pin voltage. This action can
heavily forward bias the flyback diodes and cause a large current to flow into COM, potentially damaging the
on-chip metal or overheating the part.
9.4 Layout
9.4.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive ULN2803C.
T
a
ke
care to separate the input channels as much as possible, as to eliminate crosstalk. TI recommends thick traces
for the output to drive high currents as desired. Wire thickness can be determined by the trace material current
density and desired drive current.
Because all of the channels currents return to a common emitter, size that trace width to be very wide. Some
applications require up to 2.5 A.
Copyright © 2022
T
e
xas Instruments Incorporated
13
SLRS076
– AUGUST 2022
9.4.2 Layout Example
Figure 9-4. ULN2803C Layout Example
Copyright © 2022
T
e
xas Instruments Incorporated
14
SLRS076
– AUGUST 2022
10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To
r
eceive notification of documentation updates, navigate to the device product folder on
ti.com
. Click on
Subscribe to updates
to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E
™
support forums
are an engineer’s go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided “AS IS” by the respective contributors. They do not constitute TI specifications and do
10.3 Trademarks
TI E2E
™
is a trademark of
T
e
xas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD.
T
e
xas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022
T
e
xas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
17-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ULN2803CDWR
ACTIVE
SOIC
DW
20
2000 RoHS
& Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ULN2803C
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
30-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension
designed to accommodate the component width
B0 Dimension
designed to accommodate the component length
K0 Dimension
designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch
between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
ULN2803CDWR
SOIC
DW
20
2000
330.0
24.4
10.9
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
30-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SOIC DW
20
SPQ
Length (mm)
Width (mm)
Height (mm)
356.0 356.0
41.0
ULN2803CDWR
2000
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC – 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 –
8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
EXAMPLE BOARD LAYOUT
DW0020A
SOIC – 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
DW0020A
SOIC – 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILIT
Y
,
F
ITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products.
Y
o
u are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to
TI’s
T
e
rms of Sale
or other applicable terms available either on
ti.com
or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed.
IMPORTANT NOTICE
Mailing Address:
T
e
xas Instruments, Post Office Box 655303, Dallas,
T
e
xas 75265
Copyright © 202
3
,
T
e
xas Instruments Incorporated
