Texas-Instruments-ULQ2003AQDRQ1
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ULQ200xA-Q1 H
i
gh-Voltage High-Current Darlington Transistor Arrays
1 Features
3 Description
The ULQ200xA-Q1 devices are high-voltage high-
current Darlington transistor arrays. Each consists of
seven npn Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads. The collector-current rating
of a single Darlington pair is 500 mA. The Darlington
pairs can be paralleled for higher current capability.
1
•
Qualified for Automotive Applications
•
ESD Protection Exceeds 200 V Using Machine
Model (C = 200 pF, R = 0)
•
•
•
•
•
500-mA-Rated Collector Current (Single Output)
High-Voltage Outputs: 50 V
Output Clamp Diodes
The ULQ2003A-Q1 has a 2.7-k
Ω
series base resistor
for each Darlington pair, for operation directly with
TTL or 5-V CMOS devices. The ULQ2004A-Q1 has a
10.5-k
Ω
series base resistor to allow operation
directly from CMOS devices that use supply voltages
of 6 V to 15 V. The required input current of the
ULQ2004A-Q1 is below that of the ULQ2003A-Q1.
Inputs Compatible With Various Types of Logic
Relay-Driver Applications
2 Applications
•
•
•
•
•
•
Relay Drivers
Stepper and DC Brushed Motor Drivers
Lamp Drivers
Display Drivers (LED and Gas Discharge)
Line Drivers
PART NUMBER
ULQ2003A-Q1
ULQ2004A-Q1
PACKAGE
SOIC (16)
TSSOP (16)
SOIC (16)
BODY SIZE (NOM)
9.90 mm x 3.90 mm
5.00 mm x 4.40 mm
9.90 mm x 3.90 mm
Logic Buffers
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
9
COM
1C
1
16
1B
2
15
14
13
12
11
10
2B
2C
3C
4C
5C
6C
7C
3
3B
4
4B
5
5B
6
6B
7
7B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
9
6.5 Electrical
Characteristics, ULQ2003AT and
6.7 Switching
Characteristics, ULQ2003A and
7
8
13 Mechanical,
Packaging, and Orderable
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2010) to Revision E
Page
•
Added
Pin Configuration and Functions
section,
ESD Ratings
table,
Feature Description
section,
Device Functional
Modes
,
Application and Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device
and Documentation Support
section, and
Mechanical, Packaging, and Orderable Information
section …………………………
1
2
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5 Pin
Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2B
3B
4B
5B
6B
7B
E
1C
2C
3C
4C
5C
6C
7C
COM
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
1B
2
2B
3
3B
4
4B
I
Channel 1 through 7 Darlington base input
5
5B
6
6B
7
7B
8
E
—
—
Common emitter shared by all channels (typically tied to ground)
9
COM
7C
6C
5C
4C
3C
2C
1C
Common cathode node for flyback diodes (required for inductive loads)
10
11
12
13
14
15
16
O
Channel 1 through 7 Darlington collector output
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6 Specifications
6.1 Absolute
Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)
(1)
MIN
MAX
50
UNIT
V
V
CE
Collector-emitter voltage
Clamp diode reverse voltage
(2)
Input voltage
(2)
50
V
V
I
30
V
Peak collector current
Output clamp current
500
500
–2.5
mA
mA
A
I
OK
Total emitter-terminal current
P
D
T
A
Continuous total power dissipation
Operating free-air temperature
ULQ200xAT
ULQ200xAQ
–40
–40
105
125
150
150
°C
T
J
Junction temperature
Storage temperature
°C
°C
T
stg
–65
(1) Stresses
beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All
voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
6.2 ESD
Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V
(ESD)
V
(1) AEC
Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
50
UNIT
V
CE
T
J
Collector-emitter voltage
Junction temperature
0
V
–40
125
°C
6.4 Thermal
Information
ULQ2003A-Q1,
ULQ2004A-Q1
ULQ2003A-Q1
THERMAL METRIC
(1)
UNIT
D (SOIC)
16 PINS
73
PW (TSSOP)
16 PINS
108
R
θ
JA
Junction-to-ambient thermal resistance
°C/W
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
4
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6.5 Electrical
Characteristics, ULQ2003AT and ULQ2003AQ
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I
C
= 200 mA
MIN
TYP
MAX UNIT
2.7
V
CE
= 2 V, see
V
I(on)
On-state input voltage
I
C
= 250 mA
2.9
3
V
I
C
= 300 mA
ULQ2003AT
ULQ2003AQ
ULQ2003AT
ULQ2003AQ
ULQ2003AT
ULQ2003AQ
0.9
1
1.2
1.3
1.4
1.5
1.7
1.8
100
1
Collector-emitter
saturation voltage
V
CE(sat)
V
1
1.2
1.2
V
CE
= 50 V,
Collector cutoff current
I
I
= 0, see
T
A
= 25°C
T
A
= 105°C, ULQ2003AT
I
CEX
μ
A
165
2.2
V
F
I
I(off)
I
I
1.7
65
V
Off-state input current
Input current
30
μ
A
mA
μ
A
pF
0.93
1.35
100
25
I
R
Input capacitance
V
I
= 0, f = 1 MHz
C
i
15
6.6 Electrical
Characteristics, ULQ2004AT
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
C
= 125 mA
I
C
= 200 mA
I
C
= 275 mA
I
C
= 350 mA
5
6
V
CE
= 2 V, see
V
I(on)
V
CE(sat)
I
CEX
On-state input voltage
V
7
8
0.9
1
1.1
1.3
1.6
50
Collector-emitter saturation
voltage
V
1.2
T
A
= 25°C
T
A
= 105°C
I
I
= 0
V
CE
= 50 V,
Collector cutoff current
μ
A
100
500
2.1
V
CE
= 50 V, see
V
I
= 1 V
V
F
Clamp forward voltage
Off-state input current
1.7
65
V
I
I(off)
50
μ
A
0.35
1
0.5
1.45
50
I
I
Input current
mA
T
A
= 25°C
V
R
= 50 V, see
I
R
C
i
Clamp reverse current
Input capacitance
μ
A
T
A
= 105°C
100
25
V
I
= 0, f = 1 MHz
15
pF
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MAX UNIT
6.7 Switching
Characteristics, ULQ2003A and ULQ2004A
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1
t
PLH
Propagation delay time, low- to high-level output
t
PHL
Propagation delay time, high- to low-level output
V
OH
High-level output voltage after switching
10
10
μ
s
μ
s
1
V
S
– 500
mV
6.8 Dissipation
Ratings
DERATING
FACTOR
ABOVE
T
A
= 25°C
POWER
RATING
T
A
= 85°C
POWER RATING
T
A
= 105°C
POWER RATING
T
A
= 125°C
POWER RATING
PACKAGE
T
A
= 25°C
D
950 mW
7.6 mW/°C
494 mW
342 mW
190 mW
6.9 Typical
Characteristics
2.5
2.5
T
A
= 25
°
C
T
A
= 25
°
C
I =
250
µ
A
I
2
1.5
1
2
1.5
1
I =
350
µ
A
I
I =
250
µ
A
I
I =
350
µ
A
I
I =
500
µ
A
I
I =
500
µ
A
I
0.5
0
0.5
0
0
100 200 300 400 500 600 700 800
– Total
Collector Current –
mA
0
100 200 300 400 500 600 700 800
– Collector
Current –
mA
I
C(tot)
I
C
Figure 2. Collector-Emitter Saturation Voltage vs Total
Collector Current (Two Darlingtons in Parallel)
Figure 1. Collector-Emitter Saturation Voltage vs Collector
Current (One Darlington)
6
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7 Parameter
Measurement Information
Open
V
CE
Open
I
CEX
I
I(on)
Open
V
Open
I
Figure 3.
I
CEX
Test Circuit
Figure 6.
I
I
Test Circuit
Open
V
CE
V
R
I
CEX
I
R
V
I
Open
Figure 4.
I
CEX
Test Circuit
Open
V
CE
Figure 7.
I
R
Test Circuit
I
I
I(off)
C
V
F
I
F
Open
Figure 5.
I
I(off)
Test Circuit
Figure 8.
V
F
Test Circuit
Open
Open
I
C
h
=
FE
I
I
V
CE
I
I
C
I
V
V
CE
I(on)
I
C
A. I
I
is fixed for measuring V
CE(sat)
, variable for
measuring h
FE
.
Figure 10.
V
I(on)
Test Circuit
Figure 9.
h
FE
, V
CE(sat)
Test Circuit
Figure 11.
Propagation Delay-Time Waveforms
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200
W
≤
5 ns
≤
10 ns
V
IH
(see Note C)
90%
90%
1.5 V
Input
1.5 V
10%
10%
0 V
40
µ
s
V
OH
Output
V
OL
VOLTAGE WAVEFORMS
A. The
pulse generator has the following characteristics: PRR = 12.5 kHz, Z
O
= 50
Ω
.
B. C
L
includes probe and jig capacitance.
C. For
testing the ULQ2003A, V
IH
= 3 V; for the ULQ2004A, V
IH
= 8 V.
Figure 12.
Latch-Up Test Circuit and Voltage Waveforms
8
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8 Detailed
Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The ULQ200xA-Q1 devices comprise seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULNQ200xA-Q1 devices have a series base resistor to each
Darlington pair, thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V.
The ULQ2003xA-Q1 device offers solutions to a great many interface needs, including solenoids, relays, lamps,
small motors, and LEDs. Applications requiring sink currents beyond the capability of a single output may be
accommodated by paralleling the outputs.
This device can operate over a wide temperature range (–40°C to 105°C for ULQ200xAT or –40°C to 125°C for
ULQ2003AQ).
8.2 Functional
Block Diagram
9
COM
1
2
3
4
5
6
7
16
15
14
13
12
11
10
1B
2B
3B
4B
5B
6B
7B
1C
2C
3C
4C
5C
6C
7C
Figure 13.
Logic Diagram
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Functional Block Diagram (continued)
R
B
ULQ2003A: R
= 2.7 k
W
B
ULQ2004A: R
= 10.5 k
W
7.2 k
W
3 k
W
B
A. All
resistor values shown are nominal.
B. The
collector-emitter diode is a parasitic structure and should not be used to conduct current. If the collector(s) go
below ground an external Schottky diode should be added to clamp negative undershoots.
Figure 14.
Schematics (Each Darlington Pair)
8.3 Feature
Description
Each channel of the ULQ200xA-Q1 devices consist of Darlington connected NPN transistors. This connection
creates the effect of a single transistor with a very high-current gain (
β
2). This can be as high as 10,000 A/A at
certain currents. The very high
β
allows for high-output current drive with a very low input current, essentially
equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-k
Ω
or 10.5-k
Ω
resistor connected between the
input and base of the predriver Darlington NPN. The 7.2-k
Ω
and 3-k
Ω
resistors connected between the base and
emitter of each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the
input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
8.4 Device
Functional Modes
8.4.1 Inductive
Load Drive
When the COM pin is tied to the coil supply voltage, ULQ200xA-Q1 devices are able to drive inductive loads and
suppress the kick-back voltage through the internal free-wheeling diodes.
8.4.2 Resistive
Load Drive
When driving a resistive load, a pullup resistor is needed in order for the ULQ200xA-Q1 devices to sink current
and for there to be a logic high level. The COM pin can be left floating for these applications.
10
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9 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application
Information
Typically, the ULQ200xA-Q1 device drives a high-voltage or high-current (or both) peripheral from an MCU or
logic device that cannot tolerate these conditions. This design is a common application of ULQ200xA-Q1 device,
driving inductive loads. This includes motors, solenoids and relays.
Figure 15
shows an example of driving
multiple inductive loads.
9.2 Typical
Application
ULQ2003A-Q1
3.3-V Logic
3.3-V Logic
3.3-V Logic
IN1
OUT1
OUT2
OUT3
OUT4
IN2
IN3
IN4
V
SUP
IN5
OUT5
OUT6
OUT7
COM
IN6
IN7
GND
V
SUP
Figure 15.
ULQ2003A-Q1 Device as Inductive Load Driver
9.2.1 Design
Requirements
Table 1. Design Parameters
DESIGN PARAMETER
GPIO voltage
EXAMPLE VALUE
3.3 V or 5 V
Coil supply voltage
Number of channels
12 V to 48 V
7
20 mA to 300 mA per channel
100%
Output current (R
COIL
)
Duty cycle
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9.2.2 Detailed
Design Procedure
When using ULQ2003A-Q1 device in a coil driving application, determine the following:
•
•
•
•
Input voltage range
Temperature range
Output and drive current
Power dissipation
9.2.2.1 Drive
Current
The coil voltage (V
SUP
), coil resistance (R
COIL
), and low-level output voltage (V
CE(SAT)
or V
OL
) determine the coil
current.
I
COIL
= (V
SUP
– V
CE(SAT)
) / R
COIL
(1)
9.2.2.2 Low-Level
Output Voltage
The low-level output voltage (V
OL
) is the same as V
CE(SAT)
and can be determined by,
Figure 1
or
Figure 2
.
9.2.2.3 Power
Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
For a more accurate determination of number of coils possible, use
Equation 2
to calculate ULQ200xA-Q1 device
on-chip power dissipation P
D
:
N
V
´
I
Li
P
=
å
D
OLi
i
=
1
where
•
•
N is the number of channels active together
V
OLi
is the OUT
i
pin voltage for the load current I
Li
. This is the same as V
CE(SAT)
(2)
To ensure reliability of ULQ200xA-Q1 device and the system, the on-chip power dissipation must be lower that or
T
J(MAX)
–
T
A
(
)
PD
(MAX)
=
q
JA
where
•
•
T
J(max)
is the target maximum junction temperature
T
A
is the operating ambient temperature
•
R
θ
JA
is the package junction to ambient thermal resistance
(3)
Limit the die junction temperature of the ULQ200xA-Q1 device to less than 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
12
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9.2.3 Application
Curve
600
500
400
N = 1
N = 4
N = 3
300
200
100
0
N = 2
N = 6
N = 7
N = 5
T
A
= 70
°
C
N = Number of Outputs
Conducting Simultaneously
0
10 20 30 40 50 60 70 80 90
100
Duty Cycle –
%
Figure 16.
D Package Maximum Collector Current vs Duty Cycle
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9.3 System
Examples
ULQ2003A
V
V
DD
V
V
ULQ2004A
CC
1
1
2
16
15
14
16
2
15
14
13
12
11
10
9
3
4
3
4
13
12
11
10
9
5
5
6
7
8
6
7
8
CMOS
Output
Lam
Test
TTL
Output
Figure 17. TTL to Load
Figure 18. Buffer for Higher Current Loads
V
V
ULQ2003A
CC
1
16
15
14
2
3
4
5
R
P
13
12
11
10
9
6
7
8
TTL
Output
Figure 19. Use of Pullup Resistors to Increase Drive Current
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10 Power
Supply Recommendations
This device does not need a power supply. However, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to ensure that the output voltage does not heavily exceed the COM pin
voltage. This discrepancy heavily forward biases the fly-back diodes and causes a large current to flow into
COM, potentially damaging the on-chip metal or over-heating the device.
11 Layout
11.1 Layout
Guidelines
Thin traces can be used on the input due to the low-current logic that is typically used to drive the ULQ200xA-Q1
devices. Take care to separate the input channels as much as possible, as to eliminate crosstalk. TI
recommends thick traces for the output to drive whatever high currents that may be needed. Wire thickness can
be determined by the current density of the trace material and desired drive current.
Because all of the channels currents return to a common emitter, it is best to size that trace width to be very
wide. Some applications require up to 2.5 A.
11.2 Layout
Example
1C
2C
1B
2B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
3C
4C
5C
6C
3B
4B
5B
6B
7B
E
10 7C
9
VCOM
GND
Figure 20.
Package Layout
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12 Device
and Documentation Support
12.1 Related
Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
ULQ2003A-Q1
ULQ2004A-Q1
12.2 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
Copyright © 2002–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
5-Nov-2014
PACKAGING INFORMATION
Orderable Device
ULQ2003AQDRQ1
ULQ2003ATDG4Q1
ULQ2003ATDQ1
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
D
16
16
16
16
16
16
16
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ULQ2003AQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
40
Green (RoHS
& no Sb/Br)
ULQ2003AT
ULQ2003AT
ULQ2003AT
ULQ2003AT
U2003AT
40
Green (RoHS
& no Sb/Br)
ULQ2003ATDRG4Q1
ULQ2003ATDRQ1
ULQ2003ATPWRQ1
ULQ2004ATDRG4Q1
ULQ2004ATDRQ1
D
2500
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
PW
D
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ULQ2004AT
ULQ2004AT
D
Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
5-Nov-2014
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ULQ2003A-Q1, ULQ2004A-Q1 :
•
NOTE: Qualified Version Definitions:
Catalog – TI’s standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
ULQ2003ATPWRQ1
TSSOP
PW
16
2500
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
TSSOP PW
16
SPQ
Length (mm)
Width (mm)
Height (mm)
367.0 367.0
35.0
ULQ2003ATPWRQ1
2500
Pack Materials-Page 2
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