tps1653
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TPS16530 58 V
、
4.5 A
电子保险丝（带脉冲电流支持），用于负载瞬态
1
特性
3
说明
• 工作电压
为
4.5V
至
58V
，
TPS16530
是一款易于使用的
正
58V
、
绝对最大值
为
67V
4.5A
电子保险丝
，
具有一
个
31m
Ω
的
集
成
FET
，
不仅
提供对负载、电源和电子保险丝本身的保护以及可调特
性
，
例如精确的过流保护、快速短路保护、输出压摆率
控制和欠压锁定
，
还可以使用
PGOOD
来启用和禁用
下游直流
/
直流转换器控制。
• 集成
式
58V
、
31m
Ω
R
ON
热插
拔
FET
• 可调节电流限值
：
0.6A
至
4.5A (±7%)
•
在
56V
电压下工作时提供符
合
IPC9592B
标准的间
隙
（
20
引
脚
HTSSOP
）
•
2x
脉冲电流支持
，
用于负载瞬态
• 低静态电流
，
关断时
为
21µA
• 精度
为
± 2%
的可调
节
UVLO
切断
借助使能引脚
，
可以从外部控制内部
FET
的启用和禁
用。关断引脚可用于将器件置于低功耗关断模式。为实
现系统状态监视和下游负载控制
，
该器件提供了故障和
精确的电流监视器输出。
MODE
引脚可用于在两种限
流故障响应
（
闭锁自动重试
）
之间灵活地对器件进行配
置。
• 可调节输出压摆率控制
，
用于实现浪涌电流限制
– 通过在器件加电期间进行热调节
，
为大型及未知
电容负载充电
• 电源正常输
出
(PGOOD)
这些器件采
用
20
引
脚
HTSSOP
和
24
引脚
VQFN
封装
，
并且额定工作温度范围为
-40°C
至
+125°C
。
• 可选过流故障响应选项
（
自动重试和闭锁模式
）
• 模拟电流监控
器
(IMON)
输
出
(± 6%)
• 采用易于使用
的
20
引
脚
HTSSOP
和
24
引
脚
VQFN
封装
封装尺寸
（
标称值
）
器件型号
TPS16530
TPS16530
封装
2
应用
VQFN (24)
HTSSOP (20)
4.00mm × 4.00mm
6.50mm x 4.40mm
• 在电信无线电中提供功率放大器保护
• 医疗设备
• 火警控制面板
(1)
如需了解所有可用封装
，
请参阅数据表末尾的可订购产品附
录。
• 工业打印机
IN
OUT
VIN
VOUT
C
OUT
UVLO
C
IN
31 m
PGOOD
FLT
TPS16530
ON/OFF Control
SHDN
IMON
dVdT
ILIM
EN
MODE
R
ILIM
GND
简化版原理图
脉冲电流支持
本文档旨在为方便起见
，
提供有
关
TI
产品中文版本的信息
，
以确认产品的概要。有关适用的官方英文版本的最新信息
，
请访问
Table of Contents
4 Revision History
注
：
以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
August 2021
*
Initial Release
Copyright © 2021
T
e
xas Instruments Incorporated
2
5 Pin Configuration and Functions
IN
IN
1
2
3
4
OUT
20
OUT
OUT
19
18
17
18
17
OUT
OUT
1
2
3
4
5
6
IN
P_IN
N.C
IN
IN
N.C
PGOOD
5
6
16
15
14
N.C
N.C
P_IN
16
15
PGOOD
N.C
PowerPad
TM
PowerPAD™
FLT
UVLO
N.C
7
8
IMON
14
13
FLT
EN
SHDN
MODE
13
12
IMON
UVLO
GND
9
10
11
dVdT
ILIM
图
5-2. TPS16530 PWP Package 20-Pin HTSSOP
图
5-1. TPS16530 RGE Package 24-Pin VQFN Top
Top View
View
表
5-1. Pin Functions
PIN
TPS16530
HTSSOP
TYPE
DESCRIPTION
NAME
VQFN
1
2
1
2
3
4
IN
P
Power Input. Connects to the DRAIN of the internal FE
T
.
—
P_IN
5
P
I
Supply voltage of the device. Always connect P_IN to IN directly.
Input for setting the programmable undervoltage lockout threshold. An
undervoltage event turns off the internal FET and asserts FLT to indicate the
power-failure. If not used, this pin can be connected to IN or P_IN.
UVLO
6
6
Active low enable pin. If not used, this pin can be connected to GND. Do not
leave this pin open or floating.
EN
7
8
8
9
I
GND
Connect GND to system ground
—
A capacitor from this pin to GND sets output voltage slew rate. Leaving this
pin floating enables device power up in thermal regulation resulting in fast
dVdT
9
10
I/O
Short Circuit Protection
section.
ILIM
10
11
11
12
I/O
I
Modes
section.
MODE
Shutdown pin. Pulling SHDN low makes the device to enter into low power
shutdown mode. Cycling SHDN pin voltage resets the device that has latched
off due to a fault condition.
SHDN
12
13
I
Analog current monitor output. This pin sources a scaled down ratio of
current through the internal FE
T
. A
r
esistor from this pin to GND converts
current to proportional voltage. If unused, leave this pin floating.
IMON
FLT
13
14
14
15
O
O
Fault event indicator. It is an open drain output. If unused, leave floating or
connect to GND.
Copyright © 2021
T
e
xas Instruments Incorporated
3
表
5-1. Pin Functions (continued)
PIN
TPS16530
HTSSOP
TYPE
DESCRIPTION
NAME
VQFN
Active High. A high indicates that the internal FET is enhanced. PGOOD
goes low when the internal FET is turned OFF during a fault or when SHDN
is pulled low. If PGOOD is unused then connect to GND or leave it floating.
PGOOD
16
16
O
P
17
18
18
19
20
5
OUT
Power Output of the device
—
3
4
7
15
19
20
21
22
23
24
17
—
—
—
—
—
—
Internally Not connected. Can be connected to other pins (P_IN, OU
T
,
G
ND)
for enhanced thermal performance.
N.C
—
Connect the PowerPAD to GND plane for heat sinking. Do not use the
PowerPAD as the only electrical connection to GND.
PowerPAD
™
—
Copyright © 2021
T
e
xas Instruments Incorporated
4
6 Specifications
6.1 Absolute Maximum Ratings
MIN
–
0.3
–
0.3
MAX
67
UNIT
V
IN, P_IN, OU
T
,
U
VLO, FLT, PGOOD
Input Voltage
EN, dVd
T
,
I
MON, MODE, SHDN, ILIM
Input Voltage
5.5
10
I
FLT
, I
dVdT
, I
PGOOD
Sink current
mA
I
dVdT
, I
ILIM ,
I
MODE,
I
SHDN
Source current
Internally limited
Operating Junction temperature
Transient junction temperature
Storage temperature
150
T
(TSD)
150
–
40
–
40
–
65
T
J
°C
T
stg
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
V
(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
±1000
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
NOM
MAX
58
58
4
UNIT
IN, P_IN
OU
T
,
U
VLO, PGOOD, FLT
Input Voltage
V
EN, dVd
T
,
I
MON, MODE
0
SHDN
ILIM
0
5
Resistance
Resistance
4
30
k
Ω
IMON
IN, P_IN, OUT
dVdT
1
0.1
10
–
40
µF
nF
°C
External Capacitance
T
J
Operating Junction temperature
25
125
6.4 Thermal Information
TPS16530
RGE (VQFN)
PWP (HTSSOP)
UNIT
24 PINS
32.1
26
20 PINS
31.2
22.5
8.9
R
θ
JA
R
θ
JC(top)
R
θ
JB
Ψ
JT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
9.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
0.3
9.7
8.8
Ψ
JB
Copyright © 2021
T
e
xas Instruments Incorporated
5
6.4 Thermal Information (continued)
TPS16530
RGE (VQFN)
24 PINS
3
PWP (HTSSOP)
20 PINS
UNIT
R
θ
JC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report.
6.5 Electrical Characteristics
–
40°C
≤
T
A
= T
J
≤
+125°C, 4.5 V < V
(IN)
= V
(P_IN)
< 58
V
,
V
(SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD = FLT = OPEN,
C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPP
L
Y
V
OLTAGE
V
(IN)
, V
(P_IN)
IQ
(ON)
Operating input voltage
Supply current
4.5
58
1.7
60
V
Enabled: V
(SHDN)
= 2 V
1.38
21
mA
µA
IQ
(OFF)
V
(SHDN)
= 0 V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V
(UVLOR)
V
(UVLOF)
I
(UVLO)
UVLO threshold voltage, rising
UVLO threshold voltage, falling
UVLO Input leakage current
1.176
1.09
1.2
1.122
30
1.224
1.15
150
V
V
nA
0 V
≤
V
(UVLO)
≤
58 V
–
150
Enable (EN) INPUT
V
(ENR)
Enable threshold voltage, rising
Enable threshold voltage, falling
Enable Input leakage current
1.25
150
V
V
V
(ENF)
0.65
I
(EN)
13.5
nA
0 V
≤
V
(EN)
≤
4 V
–
150
CURRENT LIMIT PROGRAMMING (ILIM)
I
(OL)
Over Load current limit
0.54
1.84
0.6
2
0.66
2.16
A
A
A
A
A
A
R
(ILIM)
= 30 k
Ω
, V
(IN)
–
V
(OUT)
= 1 V
R
(ILIM)
= 9 k
Ω
, V
(IN)
–
V
(OUT)
= 1 V
R
(ILIM)
= 4.02 k
Ω
, V
(IN)
–
V
(OUT)
= 1 V
4 k
Ω
< R
(ILIM)
< 30 k
Ω
I
(OL)
Over Load current limit
I
(OL)
Over Load current limit
4.185
4.5
4.815
I
(OL_Pulse)
I
(FASTRIP)
I
(SCP)
Transient Pulse Over current limit
Fast-trip comparator threshold
Short Circuit Protect current
2 × I
(OL)
3 × I
(OL)
45
PASS FET OUTPUT (OUT)
R
ON
R
ON
IN to OUT total ON resistance
26
33
30.44
30.44
34.5
45
0.6 A
≤
I
(OUT)
≤
4.5 A,T
J
= 25°C
0.6 A
≤
I
(OUT)
≤
4.5 A,T
J
= 85°C
m
Ω
m
Ω
IN to OUT total ON resistance
IN to OUT total ON resistance
0.6 A
≤
I
(OUT)
≤
4.5 A,
–
40°C
≤
T
J
≤
+125°C
R
ON
19
53
m
Ω
OUTPUT RAMP CONTROL (dVdT)
I
(dVdT)
dVdT charging current
V
(dVdT)
= 0 V
1.775
23.5
3.8
2
25
2.225
26
µA
V/V
V
GAIN
(dVdT)
V
(dVdTmax)
R
(dVdT)
dVdT to OUT gain
V
(OUT)
/V
(dVdT)
dVdT maximum capacitor voltage
dVdT discharging resistance
4.17
16.6
4.75
26.6
10
Ω
LOW IQ SHUTDOWN (SHDN) INPUT
V
(SHDN)
Open circuit voltage
I
(SHDN)
= 0.1 µA
2.48
0.8
2.7
3.3
2
V
V
SHDN threshold voltage for low IQ
shutdown, falling
V
(SHUTF)
V
(SHUTR)
I
(SHDN)
SHDN threshold rising
Leakage current
V
V
(SHDN)
= 0 V
µA
–
10
Copyright © 2021
T
e
xas Instruments Incorporated
6
6.5 Electrical Characteristics (continued)
–
40°C
≤
T
A
= T
J
≤
+125°C, 4.5 V < V
(IN)
= V
(P_IN)
< 58
V
,
V
(SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD = FLT = OPEN,
C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT MONITOR OUTPUT (IMON)
GAIN
(IMON)
Gain factor I
(IMON)
:I
(OUT)
25.66
26.22
27.9
27.9
30.14 µA/A
29.58 µA/A
0.6 A
≤
I
(OUT)
≤
2 A
2 A
≤
I
(OUT)
≤
4.5 A
0 V
≤
V
(FLT)
≤
58 V
0 V
≤
V
(PGOOD)
≤
58 V
FAULT FLAG (FLT): ACTIVE LOW
R
(FLT)
FLT Pull-down resistance
I
(FLT)
FLT Input leakage current
POWER GOOD (PGOOD)
R
(PGOOD)
PGOOD Pull-down resistance
I
(PGOOD)
PGOOD Input leakage current
THERMAL PROTECTION
T
(J_REG)
Thermal regulation set point
36
74
30
130
150
Ω
nA
–
150
36
74
130
150
Ω
nA
–
150
136
145
165
11
154
ºC
ºC
ºC
Thermal shutdown (TSD) threshold,
rising
T
(TSD)
T
(TSDhyst)
TSD hysteresis
Mode selection
MODE
MODE = Open
Latch
MODE_SEL
Auto
–
Retry
MODE = Short to GND
6.6 Timing Requirements
–
40°C
≤
T
A
= T
J
≤
+125°C, 4.5 V < V
(IN)
= V
(P_IN)
< 58
V
,
V
(SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD = FLT = OPEN,
C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
UVLO INPUT (UVLO)
UVLO
↑
(100 mV above V
(UVLOR)
) to
V
(OUT)
= 100 m
V
,
C
(dVdT)
≥
10 n
F
,
[C
(dVdT)
in nF]
742 +
49.5 x
C
(dVdT)
UVLO_t
on(dly)
UVLO switch turnon delay
µs
UVLO
↓
(20 mV below V
(UVLOF)
) to FLT
↓
UVLO_t
off(dly)
t
UVLO_FLTdly)
UVLO switch turnoff delay
9
11
16
µs
µs
UVLO to fault de-assertion delay
500
617
700
UVLO
↑
to FLT
↑
delay
ENABLE INPUT (EN)
EN_t
OFF(dly)
Enable turn-off delay
8.5
0.8
11
14
µs
µs
EN
↑
(20 mV above V
(OVPR)
) to FLT
↓
150 +
49.5 x
C
(dVdT)
EN
↓
(100 mV below V
(OVPF)
) to FET
ON C
(dVdT)
≥
10 n
F
,
[
C
(dVdT)
in nF]
EN_t
on(dly)
Enable turn-on delay
SHUTDOWN CONTROL INPUT (SHDN)
t
SD(dly)
SHUTDOWN entry delay
1
1.5
µs
SHDN
↓
(below V
(SHUTF)
) to FET OFF
CURRENT LIMIT
t
FASTTRIP(dly)
t
FASTTRIP(dly)
t
CL_ILIM(dly)
Hot-short response time
Soft short response
I
(OUT)
> I
(SCP)
1
3.2
µs
µs
I
(FASTTRIP)
< I
(OUT)
< I
(SCP)
2.2
4.5
Maximum duration in current limit
129
162
202
ms
Maximum duration in 2x Pulse current
limiting
t
CB(dly)
20
25.5
1.3
31
ms
ms
I
(OL)
< I
(OUT)
≤
I
(2xOL)
t
CL_ILIM_FLT(dly)
FLT delay in current limit
1.09
1.6
OUTPUT RAMP CONTROL (dVdT)
Copyright © 2021
T
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xas Instruments Incorporated
7
6.6 Timing Requirements (continued)
–
40°C
≤
T
A
= T
J
≤
+125°C, 4.5 V < V
(IN)
= V
(P_IN)
< 58
V
,
V
(SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD = FLT = OPEN,
C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
C
(dVdT)
= Open, 10% to 90%
V
(OUT)
, C
(OUT)
= 1 µF; V
(IN)
= 24V
t
(FASTCHARGE)
t
(dVdT)
Output ramp time in fast charging
350
495
700
µs
C
(dVdT)
= 22 n
F
,
1
0% to 90%
V
(OUT),
V
(IN)
= 24V
Output ramp time
8.35
ms
POWER GOOD (PGOOD)
t
PGOODR
PGOOD delay (deglitch) time
Rising edge
Falling edge
8
8
11.5
10
13
13
ms
ms
t
PGOODF
PGOOD delay (deglitch) time
FAULT FLAG (FLT)
FLT assertion delay in Pulse over
current limiting
t
CB_FLT(dly)
22
25.5
30
ms
Delay from I
(OUT)
> I
(OL)
to FLT
↓
.
THERMAL PROTECTION
t
(TSD_retry)
Retry delay in TSD
Thermal Regulation timeout
MODE = GND
500
1
648
1.3
800
1.6
ms
s
t
(Treg_timeout)
Copyright © 2021
T
e
xas Instruments Incorporated
8
6.7 Typical Characteristics
–
40°C
≤
T
A
= T
J
≤
+125°C, V
(IN)
= V
(P_IN)
= 24 V, V
( SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD =
FLT = OPEN, C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (Unless stated otherwise)
48
T
A
= 125
C
T
A
= 85
C
T
A
= 25
C
T
A
= -40
C
45
42
39
36
33
30
27
24
21
18
15
12
9
6
0
5
10 15 20 25 30 35 40 45 50 55 60
V
IN
(V)
图
6-1. On-Resistance vs Temperature Across Load Current
图
6-2. Input Supply Current vs Supply Voltage in Shutdown
1.46
5
T
A
= 125
C
4.5
T
A
= 85
C
T
A
= 25
C
T
A
= -40
C
1.44
1.42
1.4
4
3.5
3
R
ILIM
= 30k
R
ILIM
= 18k
R
ILIM
= 9k
R
ILIM
= 4.02k
1.38
1.36
1.34
1.32
1.3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60
V
IN
(V)
-40
-20
0
20
40
60
80
100 120 140
Temperature (
C)
图
6-3. Input Supply Current vs Supply Voltage During Normal
图
6-4. Overload Current Limit vs Temperature
Operation
I
OUT
= 4.5 A
图
6-5. Current Monitor Gain vs Output Current
图
6-6. IMON Offset vs Temperature
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6.7 Typical Characteristics (continued)
–
40°C
≤
T
A
= T
J
≤
+125°C, V
(IN)
= V
(P_IN)
= 24
V
,
V
( SHDN)
= 2
V
,
R
(ILIM)
= 30 k
Ω
, IMON = PGOOD =
FLT = OPEN, C
(OUT)
= 1
μ
F
,
C
(dVdT)
= OPEN. (Unless stated otherwise)
2000
1000
500
2000
1000
500
T
A
= -40
C
T
A
= 0
C
T
A
= 25
C
T
A
= 85
C
T
A
= 125
C
T
A
= -40
C
T
A
= 0
C
T
A
= 25
C
T
A
= 85
C
T
A
= 125
C
200
100
50
200
100
50
20
10
5
20
10
5
2
1
2
1
0.5
0.5
0.2
0.2
5 6 7
8 10
20 30
40 50
70 100
Power Dissipation (W)
200 300
500
4
5 6
7 8
10
20 30
40 50
70 100
Power Dissipation (W)
200 300400
T
a
ken on HTSSOP with 110 cm
2
copper connected to
Exposed PAD
T
a
ken on VQFN device with 95 cm
2
copper connected to
Exposed PAD
图
6-8. Thermal Shutdown Time vs Power Dissipation for PWP
图
6-7. Thermal Shutdown Time vs Power Dissipation for RGE
Package
Package
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7 Parameter Measurement Information
V
(OUT)
V
UVLO
V
(UVLOF)
-0.02 V
0.1 V
V
UVLO
FLT
V
(UVLOR)
+0.1V
10%
time
0
time
0
UVLO_t
ON(dly)
UVLO_t
off(dly)
V
(ENR)
+0.02V
V
(EN)
V
(OUT)
0.1 V
FLT
V
EN
V
(ENF)
-0.02 V
10%
0
0
time
time
EN_t
OFF(dly)
EN_t
ON(dly)
V
(OUT)
I
(FASTRIP)
I
(OL)
I
(OUT)
I
(OUT)
2×I
OL
I
OL
t
CL_ILIM(dly)
0
t
CL_ILIM(dly)
time
0
t
CB(dly)
t
FASTRIP(dly)
图
7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The TPS16530 is a 58-V industrial eFuse. The device provides robust protection for all systems and applications
powered from 4.5 V to 58
V
.
F
or hot-pluggable boards, the device provides hot-swap power management with
in-rush current control and programmable output voltage slew rate features using the dVdT pin. Load, source
and device protections are provided with many programmable features including overcurrent and undervoltage.
The precision overcurrent limit (±7% at 6 A) helps to minimize over design of the input power supply, while the
fast response short circuit protection 1 µs (typical) immediately isolates the faulty load from the input supply
when a short circuit is detected.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The device’s overall threshold accuracy of 2% ensures tight supervision of
bus, eliminating the need for a separate supply voltage supervisor chip.
Additional features of the TPS16530 include:
•
±6% current monitor output (IMON) for health monitoring of the system
•
A choice of latch off or automatic restart mode response during current limit and thermal fault using MODE
pin
•
PGOOD indicator output
•
Over temperature protection to safely shutdown in the event of an overcurrent event
•
De-glitched fault reporting for faults
•
Enable and Disable control from an MCU using EN pin
•
Low power shutdown using SHDN pin
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8.2 Functional Block Diagram
OUT
IN
P_IN
31 m
Charge
Pump
Current
Sense
P_IN
+
+
PORb
X27.9 µ
IMON
4.3 V
4.2 V
CP
UVLO
5 V
Gate Control Logic
Current Limit Amp
UVLOb
1.2 V
1.12 V
SWEN
Fast-Trip Comp
(Threshold= 45A)
Timeout
t
CB(dly)
t
CL_ILIM(dly)
ILIM
TSD
Thermal
Shutdown
OLR
Open/ Short
detect
EN
+
EN
SHDNb
1.25 V
0.65 V
4.17V
Ramp Control
2µA
25x
SWEN
FLT
* Only for Latch Mode
dVdT
70
SET
UVLOb
PORb
S
Q
16
TSD
CLR
R
Q
SHDNb
GND
PORb
Fault Latch
Gate Enhanced
(HS_FET)
PGOOD
11.5 ms
10 ms
1.2 Meg
SET
S
R
Q
Q
MODE
3V
2.7V
Overload fault response
(Auto-Retry/Latch-off)
select detection
65
OLR
10 µsec
0.8V
CLR
UVLOb
SHDNb
+
SHDNb
TPS16530
SHDN
8.3 Feature Description
8.3.1 Hot Plug-In and In-Rush Current Control
The devices are designed to control the inrush current upon insertion of a card into a live backplane or other
“hot” power source. This limits the voltage sag on the backplane
’
s supply voltage and prevents unintended
resets of the system power. The controlled start-up also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on. The fastest output slew rate of 24V/500 µs can be achieved by leaving dVdT pin floating.
dV
dT
V
(IN)
t
dVdT
I
=
C
ì
where
í
I
(INRUSH)
=
C
(OUT)
ì
(1)
t
dVdT
= 20.8 × 10
3
× V
(IN)
× C
(dVdT)
(2)
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VIN
VOUT
PGOOD
IIN
C
dVdT
= 100 nF
C
OUT
= 1000 µF
R
ILIM
= 4.02 k
Ω
图
8-1. Hot Plug In and Inrush Current Control at 24-V Input
8.3.1.1 Thermal Regulation Loop
The average power dissipation within the eFuse during power up with a capacitive load can be calculated using
P
D(INRUSH)
=
0.
5
ì
V
(IN)
ì
I
(INRUSH)
(3)
System designs requiring to charge large output capacitors rapidly may result in an operating point that exceeds
the power dissipation versus time boundary limits of the device defined by
图
6-7
characteristic curve. This may
result in increase in junction temperature beyond the device’s maximum allowed junction temperature.
T
o
k
eep
the junction temperature within the operating range, the thermal regulation control loop regulates the junction
temperature at T
(J_REG)
, 145°C (typical) by controlling the inrush current profile and thereby limiting the power
dissipation within the device automatically. An internal 1.3 sec (typical), t
(Treg_timeout)
timer starts from the
instance the thermal regulation operation kicks in. If the output does not power up within this time then the
internal FET is turned OF
F
.
S
ubsequent operation of the device depends on the MODE configuration (Auto-Retry
or latch OFF) setting as per the
表
8-2
. The maximum time-out of 1.3 sec (typical) in thermal regulation loop
operation ensures that the device and the system board does not heat up during steady fault conditions such as
wake up with output short-circuit. This scheme ensures reliable power up operation.
Thermal regulation control loop is internally enabled during power up by V
(IN)
, UVLO cycling and turn ON using
SHDN control.
图
8-2
illustrates performance of the device operating in thermal regulation loop during power up
by V
(IN)
with a large output capacitor. The Thermal regulation loop gets disabled internally after the power up
sequence when the internal FET’s gate gets fully enhanced or when the t
(Treg_timeout)
of 1.3 sec (typical) time is
elapsed.
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C
dVdT
= Open
V
IN
= 35 V
R
ILIM
= 4.02 k
Ω
图
8-2. Thermal Regulation Loop Response During Power Up With 4.7-mF Capacitive Load
8.3.2 Undervoltage Lockout (UVLO)
The TPS16530 device features an accurate ± 2% adjustable undervoltage lockout functionality. When the
voltage at UVLO pin falls below V
(UVLOF)
during input undervoltage fault, the internal FET quickly turns off and
FLT is asserted. The UVLO comparator has a hysteresis of 78 mV (typical).
T
o
s
et the input UVLO threshold,
connect a resistor divider network from IN supply to UVLO terminal to GND as shown in
图
8-3
. If the Under-
Voltage Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO
terminal must not be left floating.
V
(IN)
IN
P_IN
R
1
UVLO
+
UVLOb
1.2 V
R
2
1.12 V
图
8-3. UVLO Thresholds Set by R
1
and R
2
8.3.3 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
8.3.3.1 Overload Protection
The TPS16530 device features accurate overload current limiting and fast short circuit protection feature. The
device supports a pulse current up to 9A (2 × I
OL
) for transient loads.
表
8-1
describes the overload response of
TPS16530 device.
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表
8-1. Overload Response of TPS16530 Device
Output Current
Overload or Over-Current Response
I
OUT
< I
OL
No action. Device provides current up-to I
OL
Device provides current up to 2 × I
OL
for a duration of t
CB(dly)
and then limits current to I
OL
for a
maximum duration of t
CL_ILIM(dly)
Device limits current to 2 × I
OL
for a maximum duration of t
CB(dly)
and then limits current to I
OL
for a
maximum duration of t
CL_ILIM(dly)
.
I
OL
≤
I
OUT
< 2 × I
OL
2 × I
OL
≤
I
OUT
< 3 × I
OL
3 × I
OL
≤
I
OUT
.
.
Device provides fast trip protection or short circuit protection and turns off the internal FE
T
.
S
ee the
Short Circuit Protection
section.
The power dissipation across the device during this operation will be [(V
IN
–
V
OUT
) × I
OL
] for I
OUT
< 2 × I
OL
or
[(V
IN
–
V
OUT
) × 2 × I
OL
] for 2 × I
OL
< I
OUT
< 3 × I
OL
and this could heat up the device and eventually enter into
thermal shutdown.
For current limit of I
OL,
the maximum duration for current limiting is t
CL_ILIM(dly)
, 162 msec (typical). For current
limit of 2 × I
OL,
the maximum duration for current limiting is t
CB(dly)
, 25 msec (typical) .
If the thermal shutdown occurs before this time the internal FET turns OFF and the device operates either in
auto-retry or latch off mode based on MODE pin configuration in
表
8-2
. Set the current limit using
方程
式
4
.
18
I
OL
=
R
ILIM
(4)
where
•
I
(OL)
is the overload current limit in Ampere
•
R
(ILIM)
is the current limit resistor in k
Ω
During the overload current limiting, if the overload condition exists for more than t
CL_ILIM_FLT(dly)
, 1.3 msec
(typical), the FLT asserts to warn of impending turnoff of the internal FE
T
s
d
ue to the subsequent thermal
shutdown event or due to t
CL_ILIM(dly)
timer expiry. The FLT signal remains asserted until the fault condition is
removed and the device resumes normal operation.
图
8-4
shows the device behavior in case of overload event.
The device provides a pulse current of 7 A for a duration of 25 ms and then turns off the internal FET due to
thermal shutdown before the expiry of t
CL_ILIM(dly)
.
The 2 × I
(OL)
pulse current support is activated only after PGOOD goes high. If PGOOD is in low state such as
during start-up operation or during auto-retry cycles, the 2 × I
(OL)
pulse current support is not activated and the
device limits the current at I
(OL)
level.
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V
IN
= 58 V
ILIM = 4.5 A
I
OUT
= 4 A to 7 A
图
8-4. Pulse Current Support
The TPS16530 device feature ILIM pin short and open fault detection and protection. The internal FET is turned
OFF when ILIM pin is detected short or open to GND and it remains OFF till the ILIM pin fault is removed.
8.3.3.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator. The fast-trip comparator architecture is designed for fast turn OFF t
FASTTRIP(dly)
= 1 µs (typical) with
I
(SCP)
= 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to
I
(FASTTRIP)
. The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device
turns back on slowly, allowing the current-limit loop to regulate the output current to I
(OL)
. Then the device
functions similar to the overload condition.
图
8-5
illustrates output hot-short performance of the device.
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VOUT
IIN
IMON
FLTb
V
IN
= 50 V
R
ILIM
= 18 k
Ω
图
8-5. Output Hot-Short Response
The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This performance is achieved by controlling the turn OFF time of the internal FET based on the
overcurrent level, I
(FASTTRIP)
, through the device. The higher the overcurrent, the faster the turn OFF time,
t
FASTTRIP(dly)
. At Overload current level in the range of I
FASTTRIP
< I
OUT
< I
SCP
, the fast-trip comparator response
is 3.2 µs (typical).
8.3.3.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, the current begins to limit at I
(OL)
. Due to high power
dissipation of VIN × I
(OL)
within the device the junction temperature increases. Subsequently, the thermal
regulation control loop limits the load current to regulate the junction temperature at T
(J_REG)
, 145°C (typical) for
a duration off t
(Treg_timeout)
, 1.25 sec (typical). Subsequent operation of the device depends on the MODE
configuration (Auto-Retry or latch OFF) setting as per
表
8-2
. FLT gets asserted after t
(Treg_timeout)
and remains
asserted till the output short-circuit is removed.
图
8-6
illustrates the behavior of the device in this condition.
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V
IN
= 58 V
ILIM = 4.5 A
图
8-6. Start-Up With Short on Output
8.3.4 Current Monitoring Output (IMON)
The TPS16530 device features an accurate analog current monitoring output. A current source at IMON terminal
is internally configured to be proportional to the current flowing from IN to OU
T
.
T
his current can be converted
into a voltage using a resistor R
(IMON)
from IMON terminal to GND terminal. The IMON voltage can be used as a
means of monitoring current flow through the system. The maximum voltage (V
(IMONmax
) for monitoring the
current is limited to 4
V
.
T
his limit puts a limitation on maximum value of R
(IMON)
resistor and is determined by
方
V
(
IMON
)
=
I
[
(
OUT
)
ì
GAIN
(
IMON
)
ì
R
(
IMON
)
]
(5)
Where,
•
GAIN
(IMON)
is the gain factor I
(IMON)
:I
(OUT)
= 27.9
μ
A/A (typical)
•
I
(OUT)
is the load current
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VIN
VOUT
IMON
IIN
图
8-7. IMON Response During a Load Step
The IMON pin must not have a bypass capacitor to avoid delay in the current monitoring information.
8.3.5 FAULT Response (FLT)
The FLT open-drain output asserts (active low) under the faults events such as undervoltage, overload, current
limiting, ILIM pin short and thermal shutdown conditions. The device is designed to eliminate false reporting by
using an internal “de-glitch” circuit for fault conditions without the need for an external circuitry. FLT can be left
open or connected to GND when not used.
8.3.6 Power Good Output (PGOOD)
The devices feature an open drain Power good (PGOOD) indicator output. PGOOD can be used for enable and
disable control of the downstream loads like DC/DC converters. PGOOD goes high when the internal FET
’
s
gate is enhanced. It goes low when the internal FET turns OFF during a fault event or when SHDN is pulled low
or when EN is pulled high. There is a deglitch of 11.5 msec (typical), t
PGOODR
, at the rising edge and 10 msec
(typical), t
PGOODF
, on falling edge. PGOOD is a rated for 58 V and can be pulled to IN or OUT through a resistor.
8.3.7 IN, P_IN, OUT and GND Pins
Connect a minimum of 0.1-µF capacitor across IN and GND. Connect P_IN and IN together. Do not leave any of
the IN and OUT pins unconnected.
8.3.8 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FET if the junction
temperature exceeds T
(TSD)
, 165°C (typical). After the thermal shutdown event, depending upon the mode of
fault response configured as shown in
表
8-2
, the device either latches off or commences an auto-retry cycle of
648 msec (typical), t
(TSD_retry)
after T
J
< [T
(TSD)
–
11°C]. During the thermal shutdown, the fault pin FLT pulls low
to indicate a fault condition.
8.3.9 Low Current Shutdown Control (SHDN)
The internal and the external FET and hence the load current can be switched off by pulling the SHDN pin below
a 0.8-V threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device.
The device quiescent current reduces to 21
μ
A (typical) in shutdown state.
T
o
a
ssert SHDN low, the pull down
must have sinking capability of at least 10 µA.
T
o
e
nable the device, SHDN must be pulled up to at least 2
V
.
Once the device is enabled, the internal FET turns on with dVdT mode.
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8.3.10 Enable Input (EN)
The EN pin can be used to turn-on or turn-off the internal FE
T
.
E
N can be used with a 1.8-V Digital IO of FPGA
or MCU. For rising and falling thresholds of EN pin. See V
ENR
and V
ENF
in
Electrical Characteristics
. After the EN
is made low, the output ramps with slew rate configured by dVdT pin.
EN pin does not reset the latch in latch mode (MODE = Open) and making EN pin high asserts the FLT pin. See
8.4 Device Functional Modes
The TPS16530 device respond differently to overload with MODE pin configurations.
表
8-2
lists the operational
differences.
表
8-2. Device Operational Differences Under Different MODE Configurations
MODE Pin Configuration
Current Limiting, Over Current Fault and Thermal Shutdown Operation
Active Current limiting for a maximum duration of t
CL_ILIM(dly)
. There after Latches OF
F
.
L
atch
reset by toggling SHDN or UVLO low to high or power cycling IN.
Open
Active Current limiting for a maximum duration of t
CL_ILIM(dly)
. There after auto-retries after a
Shorted to GND
delay of t
(TSD_retry)
.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI
’
s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS16530 is a 58-V eFuse, typically used for Hot-Swap and Power rail protection applications. The device
operates from 4.5 V to 58 V with programmable current limit, undervoltage protections. The device aids in
controlling in-rush current and provides current limiting for systems such as telecom radios and industrial
printers. The device also provides robust protection for multiple faults on the system rail.
9.2 Typical Application
VIN : 20 – 50V
VOUT
IN
OUT
C
OUT
100 µF
P_IN
31m
R
1
887 k
PGOOD
FLT
UVLO
TPS16530
R
2
63.4 k
SHDN
IMON
ILIM
EN
R
IMON
30 k
dVdT
22 nF
R
ILIM
18 k
MODE
GND
图
9-1. 20 V
–
50
V
,
1
-A eFuse Protection Circuit for Telecom Radios
9.2.1 Design Requirements
表
9-1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
20 V
–
50 V
18 V
V
(IN)
Input voltage range
V
(UV)
I
(LIM)
C
OUT
I
(INRUSH)
Undervoltage lockout set point
Overload Current limit
Output capacitor
1 A
100 µF
Inrush Current limit
300 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Current-Limit Threshold R
(ILIM)
Selection
18
R
(
ILIM
=
=
18k
W
)
I
OL
(6)
where
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•
I
LIM
= 1 A
Choose the closest standard 1% resistor value: R
(ILIM)
= 18 k
Ω
9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
The Undervoltage Lockout (UVLO) trip point are adjusted using an external voltage divider network of R
1
and R
2
connected between IN, UVLO, and GND pins of the device. The values required for setting the undervoltage are
calculated by solving V
(UVLOR)
= R
2
/ (R
1
+R
2
) × V
(UV_IN)
.
For minimizing the input current drawn from the power supply, {I
(R12)
= V
(IN)
/ (R
1
+ R
2
)}, TI recommends to use
higher value resistance for R
1
and R
2
.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R
12
) must be chosen to be 20 times greater than the leakage
current of UVLO pin.
Choose the closest standard 1% resistor values: R
1
= 887 k
Ω
, R
2
= 63.4 k
Ω
.
9.2.2.3 Setting Output Voltage Ramp Time (t
dVdT
)
9.2.2.3.1 Support Component Selections R
PGOOD
and C
(IN)
The R
PGOOD
serves as pull-up for the open-drain output. The current sink by this pin must not exceed 10 mA
(see the
Absolute Maximum Ratings
table). TI recommends typical resistance value in the range of 10 k
Ω
to 100
k
Ω
for R
PGOOD
.
图
9-6
illustrates the power up performance of the system. The C
IN
is a local bypass capacitor to
suppress noise at the input. TI recommends a minimum of 0.1 µF for C
(IN)
.
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9.2.3 Application Curves
VIN
VIN
VOUT
VOUT
PGOOD
PGOOD
IIN
IIN
图
9-2. Hot-Plug In at 50-V Supply with No Load
图
9-3. Hot-Plug In at 50-V Supply with 60-
Ω
Load
VOUT
IIN
IMON
FLTb
ILIM = 4.5 A
图
9-5. Output Hot-short Performance with 50-V
Input Supply
图
9-4. Overload Performance During Load Step
from 4 A to 7 A
SHDNb
SHDNb
VOUT
VOUT
PGOOD
PGOOD
IIN
IIN
图
9-6. Turn ON Using SHDN Control
图
9-7. Turn OFF Using SHDN Control
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9.3 System Examples
9.3.1 48-V Power Amplifier Protection for Telecom Radios
With the TPS16530, a simple 48-V power supply path protection can be realized for telecom radios.
图
9-8
shows the simplified schematic for this. For start-up with negative gate voltage drive at GaN FE
T
s
, TI
recommends to use appropriate resistors for biasing the gate of GaN FE
T
s
t
o keep V
OUT
>
–
0.2 V and I
OUT
< 70
μ
A from TPS16530.
V
OUT
IN
OUT
48V-52V
D
UVLO
C
IN
31 m
G
GaN
FET
PGOOD
FLT
S
TPS16530
SHDN
IMON
dVdT
ILIM
EN
R
IMON
MODE
R
ILIM
GND
图
9-8. TPS16530 Configured for 48-V Power Amplifier Protection
Protection features with this configuration include:
•
Accurate current limiting with pulse current support
•
Inrush current control with 24-V/500-µs output voltage slew rate
Copyright © 2021
T
e
xas Instruments Incorporated
25
10 Power Supply Recommendations
The TPS16530 eFuse is designed for the supply voltage range of 4.5 V
≤
V
IN
≤
58
V
.
I
f the input supply is
located more than a few inches from the device, TI recommends an input ceramic bypass capacitor higher than
0.1
μ
F
.
P
ower supply must be rated higher than the current limit set to avoid voltage droops during overcurrent
and short circuit conditions.
10.1 Transient Protection
In case of short circuit and overload current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the
input or output of the device. These transients can exceed the
Absolute Maximum Ratings
of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
•
Minimizing lead length and inductance into and out of the device
•
Using large PCB GND plane
•
Use of a Schottky diode across the output and GND to absorb negative spikes
•
A low value ceramic capacitor (C
(IN)
to approximately 0.1
μ
F) to absorb the energy and dampen the
transients.
L
IN
( )
V
spike Absolute
=
V
IN
+
I
Load
( )
)
´
(
)
(
C
IN
( )
(7)
where
•
V
(IN)
is the nominal supply voltage
•
I
(LOAD)
is the load current
•
L
(IN)
equals the effective inductance seen looking into the source
•
C
(IN)
is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
negative surge tests on the supply lines. In such applications, TI recommends to place at least 1 µF of input
capacitor.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
Copyright © 2021
T
e
xas Instruments Incorporated
26
Input
Output
C
OUT
IN
OUT
P_IN
*
31 m
*
R
1
R
2
PGOOD
FLT
UVLO
TPS16530
SHDN
EN
IMON
ILIM
dVdT
C
dVdT
MODE
R
ILIM
GND
*
Optional components needed for suppression of transients
图
10-1. Circuit Implementation with Optional Protection Components for TPS16530
Copyright © 2021
T
e
xas Instruments Incorporated
27
11 Layout
11.1 Layout Guidelines
•
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND.
•
High current carrying power path connections must be as short as possible and must be sized to carry at
•
Locate all the TPS16530 device support components R
(ILIM)
, C
(dVdT)
, R
(IMON)
, UVLO resistors close to the
device pin. Connect the other end of the component to the GND with shortest trace length.
•
The trace routing for the R
(ILIM)
component to the device must be as short as possible to reduce parasitic
effects on the current limit accuracy. These traces must not have any coupling to switching signals on the
board.
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
•
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability.
T
o
o
perate at rated power, the PowerPAD must be soldered directly to the board GND plane
directly under the device. Other planes, such as the bottom side of the circuit board, can be used to increase
heat sinking in higher current applications.
Copyright © 2021
T
e
xas Instruments Incorporated
28
11.2 Layout Example
T
o
p Layer
Bottom layer GND plane
T
o
p Layer GND Plane
Via to Bottom Layer
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
D2
D1
VOUT PLANE
OUT
OUT
IN
IN
N.C
PGOOD
N.C
P_IN
N.C
FLT
UVLO
IMON
TOP Layer
GND Plane
BOTTOM Layer GND Plane
图
11-1. PCB Layout Example With QFN Package With a 2-Layer PCB
Copyright © 2021
T
e
xas Instruments Incorporated
29
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
C
OUT
D2
D1
VIN PLANE
VOUT PLANE
IN
IN
OUT
OUT
OUT
N.C
IN
P_IN
PGOOD
FLT
N.C
UVLO
N.C
IMON
EN
SHDN
MODE
GND
ILIM
dVdT
T
o
p Layer
TOP Layer
GND Plane
Bottom layer GND plane
T
o
p Layer GND Plane
Via to Bottom Layer
BOTTOM Layer GND Plane
图
11-2. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB
Copyright © 2021
T
e
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30
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
12.2
接收文档更新通知
改摘要。有关更改的详细信息
，
请查看任何已修订文档中包含的修订历史记录。
12.3
支持资源
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成
TI
技术规范
，
并且不一定反映
TI
的观点
；
请参阅
12.4 Trademarks
PowerPAD
™
is a trademark of
T
e
xas Instruments.
TI E2E
™
is a trademark of
T
e
xas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD.
T
e
xas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6
术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021
T
e
xas Instruments Incorporated
31
重要声明和免责声明
TI
提供技术和可靠性数据
（
包括数据表
）
、设计资源
（
包括参考设计
）
、应用或其他设计建议、网络工具、安全信息和其他资源
，
不保证没
有瑕疵且不做出任何明示或暗示的担保
，
包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使
用
TI
产品进行设计的熟练开发人员使用。您将自行承担以下全部责任
：
(1)
针对您的应用选择合适
的
TI
产品
，
(2)
设计、验
证并测试您的应用
，
(3)
确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更
，
恕不另行通知。
TI
授权您仅可
将这些资源用于研发本资源所述
的
TI
产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其
他
TI
知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中
对
TI
及其代表造成的任何索赔、损害、成本、损失和债务
，
TI
对此概不负责。
提供这些资源并不会扩展或以其他方式更
改
TI
针
对
TI
产品发布的适用的担保或担保免责声明。
重要声明
邮寄地址
：
T
e
xas Instruments, Post Office Box 655303, Dallas,
T
e
xas 75265
Copyright © 2021
，
德州仪
器
(TI)
公司
PACKAGE OPTION ADDENDUM
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS16530PWPR
TPS16530RGER
ACTIVE
ACTIVE
HTSSOP
VQFN
PWP
RGE
20
24
2000 RoHS
& Green
3000 RoHS
& Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TPS16530
NIPDAU
TPS
16530
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PWP0020T
PowerPAD
TM
TSSOP – 1.2 mm max height
S
C
A
L
E
2
.
3
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
0.1 C
A
PIN 1 INDEX
AREA
18X 0.65
SEATING
20
PLANE
1
2X
6.6
6.4
5.85
NOTE 3
10
11
0.30
20X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL
A
(0.15) TYP
2X 1.15 MAX
NOTE 5
11
10
2X 0.3 MAX
NOTE 5
0.25
1.2 MAX
GAGE PLANE
21
2.96
2.21
0.15
0.05
0.75
0.50
THERMAL
PAD
0 -8
A
15
DETAIL A
TYPICAL
1
20
2.96
2.16
4224598/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
EXAMPLE BOARD LAYOUT
PWP0020T
PowerPAD
TM
TSSOP – 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.96)
METAL COVERED
BY SOLDER MASK
20X (1.5)
SYMM
1
20
20X (0.45)
(R0.05) TYP
(1.3)
TYP
(6.5)
NOTE 9
21
SYMM
(2.96)
SOLDER MASK
DEFINED PAD
18X (0.65)
10
11
(1.3) TYP
SEE DETAILS
(
0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4224598/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
EXAMPLE STENCIL DESIGN
PWP0020T
PowerPAD
TM
TSSOP – 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.96)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
20X (1.5)
1
20
20X (0.45)
(R0.05) TYP
SYMM
21
(2.96)
BASED ON
0.125 THICK
STENCIL
18X (0.65)
11
10
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.31 X 3.31
2.96 X 2.96 (SHOWN)
2.70 X 2.70
0.125
0.15
0.175
2.50 X 2.50
4224598/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
GENERIC PACKAGE VIEW
RGE 24
VQFN – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN – 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A
08/2017
NOTES:
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This
drawing is subject to change without notice.
3. The
package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
EXAMPLE BOARD LAYOUT
VQFN – 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A
08/2017
NOTES: (continued)
4. This
package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271)
.
5. Solder
mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
VQFN – 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X (
1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A
08/2017
NOTES: (continued)
6. Laser
cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
重要声明和免责声明
TI“
按原样
”
提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用
TI
产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：
(1)
针对您的应用选择合适的
TI
产品，
(2)
设计、验
证并测试您的应用，
(3)
确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。
TI
授权您仅可将这些资源用于研发本资源所述的
TI
产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他
TI
知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对
TI
及其代表造成的任何索赔、损害、成
本、损失和债务，
TI
对此概不负责。
TI
反对并拒绝您可能提出的任何其他或不同的条款。
IMPORTANT NOTICE
邮寄地址：
T
e
xas Instruments, Post Office Box 655303, Dallas,
T
e
xas 75265
Copyright © 202
3
，德州仪器
(TI)
公司
