tps2456a
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SLVSBI8
–
J
ULY 2012
Dual 12 V Protection and Blocking Controller
1
FEATURES
DESCRIPTION
The TPS2456A is a dual, 12 V, channel protection
(hotswap) and blocking (ORing) controller that
provides inrush control, current limiting, overload
protection, and reverse current blocking. The current
sense topology provides both accurate current limits
and independent setting of current limit and fast trip
thresholds.
2
•
TPS2456A Improves Supply Slew-rate
Immunity
•
•
•
•
•
•
•
Dual 12 V Protection and Blocking Control
Independent Current Limit and Fast Trip
Blocking Permits ORing of Multiple Inputs
Power Good and Fault Outputs
Analog Current Monitor Outputs
-40°C to 125°C Operating T
J
The ORing control uses an external MOSFET to
block reverse current when an input is shorted.
Systems with closely matched supply voltages and
feed networks can supply current from both supplies
simultaneously.
QFN36 Package
APPLICATIONS
The MONx output provides an accurate analog
indication of load current.
•
•
•
•
•
ATCA Carrier Boards
AdvancedMC™ Slots
Blade Servers
The protection circuits may be used without blocking,
and the blocking may be used without protection.
Internal connections prevent implementation of these
as four fully-independent functions.
Base Stations
Configurable for
The TPS2456 and TPS2456A have identical
Electrical Characteristics tables. The TPS2456A has
reduced sensitivity to input supply slew rate
variations. It is recommended for all new applications.
–
–
–
1 Source, 2 Loads
2 Sources, 1 Load
2 Sources, 2 Loads
Figure 1.
Two Sources, One Load Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
AdvancedMC is a trademark of PICMG.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
J
ULY 2012
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCT INFORMATION
(1)
DEVICE
TEMPERATURE
PACKAGE
MARKING
TPS2456ARHH
–40°C to 85°C
QFN36 (6mm × 6mm)
2456A
(1) For
package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at
THERMAL INFORMATION
TPS2456A
THERMAL METRIC
(1)
RHH
36 PINS
32
UNITS
θ
JA
Junction-to-ambient thermal resistance
(2)
(3)
θ
JC(top)
θ
JB
Junction-to-case(top) thermal resistance
23
(4)
Junction-to-board thermal resistance
11
°C/W
(5)
ψ
JT
Junction-to-top characterization parameter
0.5
(6)
ψ
JB
Junction-to-board characterization parameter
10
(7)
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
2.1
SPACER
(1) For
more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953
.
(2) The
junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The
junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The
junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The
junction-to-top characterization parameter,
ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The
junction-to-board characterization parameter,
ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
Spacer
(7) The
junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS
(1)
Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.
VALUE
PINS OR PIN GROUPS
UNITS
MIN
–0.3
–0.3
–0.3
MAX
30
20
5
GAT1x, GAT2x
V
V
INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx
CTx, MONx
V
FLTx, PGx current sinking
MONx current sourcing
VINT current
5
mA
mA
mA
kV
kV
°C
5
–1
1
Human Body Model
ESD
2
Charged Device Model
0.5
Junction Temperature
Internally Limited
(1) Stresses
beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
2
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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ULY 2012
RECOMMENDED OPERATING CONDITIONS
Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.
MIN
TYP
12
MAX UNIT
V
INx
8.5
15
1000
1
V
I
MONx
100
µA
µA
nF
°C
GAT1x, GAT2x board leakage current
(1)
VINT bypass capacitance
Operating junction temperature range, T
J
–1
1
100
250
125
–40
(1) This
condition applies to the PCB and is not a limit on the TPS2456A.
ELECTRICAL CHARACTERISTICS
Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB =
12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, R
MONA
= R
MONB
= 6.81k
Ω
, all other pins open,
–40°C
≤
T
J
≤
125°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Enable Input – ENx, ORENx
Threshold voltage
Hysteresis
V
INx
↑
1.25
20
5
1.35
50
8
1.45
80
V
mV
µA
µA
µs
Pullup current
ENx = ORENx = 0 V, current sourcing
15
Input bias current
Turn off time
(1) (2)
Power Good Output – PGx
Output low voltage
Leakage current
Threshold voltage
Hysteresis
ENx = ORENx = 17 V, current sinking
6
15
ENx deasserts to V
OUTx
< 1 V, C
OUT
= 0 µF, Q
GAT1x
= 33 nF
20
I
PGx
= 2 mA sinking
PGx = 17 V (sinking)
0.14
0.25
1
V
µA
V
PGx, V
OUTx
PGx, V
OUTx
PGx falling
↓
↑
10.2
50
10.5
130
(2)
100
10.8
mV
µs
Deglitch time
150
Fault Output – FLTx
Output low voltage
Leakage current
Bias Supply – VINT
Output voltage
I
FLTx
= 2 mA sinking
V
FLTx
= 17 V (sinking)
0.14
2.3
0.25
1
V
µA
0 < I
VINT
< 50 µA
2
2.8
V
Fault Timer – CTx
Sourcing current
Upper threshold voltage
Discharge pulldown
(2)
V
CTx
= 0 V, during fault
7
10
1.35
200
13
µA
V
1.30
1.40
Ω
(V
GAT1x
– V
INx
) when timer starts, with V
GAT1x
falling due to over
current
Timer start threshold
5
6
7
V
Channel Current Monitor – MONx
10.8 V
≤
V
SENMx
≤
13.2 V, V
SENPx
= V
SENMx
+ 50 mV,
measure V
SETx
– V
SENMx
Input referred offset
–1.5
0.66
1.5
mV
MONx threshold
Leakage current
V
GAT1x
= 15 V
0.675
0.69
1
V
V
SETx
= (V
SENMx
– 10 mV)
µA
(1) Tested
with HAT2156 MOSFET.
(2) These
parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2012, Texas Instruments Incorporated
3
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ULY 2012
ELECTRICAL CHARACTERISTICS (continued)
Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB =
12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, R
MONA
= R
MONB
= 6.81k
Ω
, all other pins open,
–40°C
≤
T
J
≤
125°C
PARAMETER
Current limit
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
SETx
= 500
Ω
, R
MONx
= 6800
Ω
, measure V
SENPx
– V
SENMx
when V
GAT1x
= 15 V
Current limit threshold
47.5
50
52.5
40
mV
µA
Sink current in current
limit
V
MONx
= 1 V, V
GAT1x
= 12 V, measure I
GAT1x
Measure V
SENPx
– V
SENMx
20
80
Fast trip threshold
Fast turn-off delay
Channel UVLO
UVLO
100
200
120
300
mV
ns
(3)
(V
SENP
– V
SENM
): 0 V
→
120 mV, t
P50-50
SENPx rising
SENPx falling
8.1
8.5
0.5
8.9
V
V
UVLO hysteresis
Blocking Comparator
Turn-on threshold
Turn-off threshold
Turn-off delay
0.44
0.59
Measure (V
SENPx
– V
OUTx
Measure (V
SENPx
– V
OUTx
20 mV overdrive, t
p50-50
)
)
5
10
–3
20
0
mV
mV
ns
–6
200
300
Gate Drivers – GAT1x, GAT2x
Output voltage
V
INx
= V
OUTx
= 10 V
21.5
20
0.5
6
23
30
1
24.5
40
V
µA
A
Sourcing current
V
INx
= V
OUTx
= 10 V, V
GAT1x
= V
GAT2x
= 17 V
Fast turnoff, V
GAT1x
= V
GAT2x
= 14 V, pulsed measurement
Sustained, 4 V
≤
(V
GAT1x
= V
GAT2x
)
≤
25 V
In thermal shutdown
Sinking current
14
20
10
20
26
mA
k
Ω
µs
µs
ms
Pulldown resistance
Fast turn-off duration
Disable delay
14
5
15
(4)
ENx pin to V
GATx1
and V
GAT2x
, t
P50-90
1
INx rising to GAT1x or GAT2x sourcing current
(ENx and ORENx high)
0.25
Startup Time
Supply Current (I
INx
+ I
SENPx
+ I
SENMx
+ I
SETx
+ I
OUTx
)
Both channels enabled
3.1
2
4
mA
mA
Both channels disabled
2.8
Thermal Shutdown
Shutdown temperature
Hysteresis
T
J
rising
140
150
10
(5)
°C
°C
(5)
These parameters
are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
V
GA
T
1x
,
V
GA
T
1x
,
90%
50%
50%
V
GA
T
2x
V
GA
T
2x
V
SENPx
–
V
ENx
V
T
V
SENMx
time
time
t
P50-90
t
P50-50
Figure 2. t
P50-90
Definition
Figure 3. t
P50-50
Definition
4
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
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ULY 2012
FUNCTIONAL BLOCK DIAGRAM
M
M
2
R
1
SENSEx
12 V Channel
Input Supply
R
SETx
R
R
G1x
GAT2x
G2x
OUTx
SENPx SETx
SENMx
GAT1x
V
CP
~25 V
V
CP
Fast
Trip
prgx
enx
100 mV
Charge
Pump
blx
INx
A
Control
& Fault
1
C
Tx
FLTx
VINT
200 k
W
C
Tx
ENx
8.5 V
/ 8 V
UVLO
6 V
INx
por
675 mV
A
2
R
FLT Tmr.
Gate Mon.
MONx
Current
Limit
prgx
60
m
A
MONx
PGx
Blocking
Control
10 mV
blx
OUTx
R
Q
100
m
s
OUTx
10.50 V /
10.63 V
S
Q
3 mV
Output
PG
ORENx
VINT
200 k
W
Figure 4.
TPS2456A Channel (2 Channels Per Device)
VINT
VINT
INA
en
por
C
VINT
2.2V
INB
+
Control
Logic
Pwr On
Reset
OUTA
OUTB
PREREG
GND
Figure 5.
TPS2456A Common Control Circuits
Copyright © 2012, Texas Instruments Incorporated
5
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PIN FUNCTIONS
PIN
TYPE A/B
(1)
DESCRIPTION
NAME
NO.
SENPA
1
I
I
A
A
Input voltage sense – connect to input supply. Connect to the source side of R
SENSEA
.
Connect R
SETA
from the input supply to SETA to program the current limit in conjunction with R
SENSEA
SETA
2
SENMA
VINT
3
4
I
A
–
Connect this pin to the load side of the R
SENSEA
. The fast-trip threshold equals 100 mV / R
SENSEA
.
I/O
Connect a bypass capacitor (e.g., 0.01µF) to GND for this internal supply.
Connect R
MONA
from MONA to GND to set the current limit in conjunction with R
SENSEA
and R
SETA
MONA
5
I/O
A
ORENA
GND
6
7
8
I
A
–
–
Blocking transistor enable, active high.
Connect pin to ground.
GND
GND
GND
Connect pin to ground
Connect R
MONB
from MONB to GND to set the current limit in conjunction with R
SENSEB
and R
SETB
MONB
9
I/O
B
CTB
10
11
12
13
I/O
O
B
B
B
B
B
B
B
Connect C
TB
from CTB to GND to set the fault timer period (see text).
Blocking transistor gate drive.
GAT2B
OUTB
GND
I/O
GND
I
Output voltage monitor and bias input.
Connect pin to ground.
ORENB 14
GAT1B 15
SENMB 16
Blocking transistor enable, active high.
Protection transistor gate drive.
O
I
Connect this pin to the load side of the R
SENSEB
. The fast-trip threshold equals 100 mV / R
SENSEB
.
Connect R
SETB
from input supply to SETB to program the current limit program the current limit in
SETB
17
I
B
SENPB
INB
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
–
I
PWR
–
B
B
–
Input voltage sense – connect to input supply. Connect to the source side of R
SENSEB
Control power input – connect to input supply.
No connection.
.
–
FLTB
PGB
GND
GND
GND
PGA
FLTA
GND
ENB
GAT1A
ENA
GND
OUTA
GAT2A
CTA
O
B
B
–
Fault output, active low, asserted when B fault timer runs out.
Power good output, active low, asserts when V
OUTB
> 10.63 V.
Connect pin to ground.
O
GND
GND
GND
O
–
Connect pin to ground.
–
Connect pin to ground.
A
A
–
Power good output, active low, asserts when V
OUTA
> 10.63 V.
Fault output, active low, asserted when A fault timer runs out.
Connect pin to ground.
O
GND
I
B
A
A
A
A
A
A
A
–
Enable, (active high).
O
Protection transistor gate drive.
I
Enable, (active high).
GND
I/O
O
Connect pin to ground.
Output voltage monitor and bias input.
Blocking transistor gate drive.
I/O
PWR
–
Control power input – connect to input supply.
INA
PAD
Solder pad to GND.
(1) Specifies
whether this pin is part of A channel, B channel, or is common to both (-).
6
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
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ULY 2012
DEVICE PINOUT
(TOP VIEW)
DETAILED PIN DESCRIPTIONS
The TPS2456A supports two 12-V protection (hotswap) and blocking (ORing) channels designated A and B.
Where there are separate pins for both A and B channels, the pin name is shown with an x in place of A or B to
describe the function. For example, references to CTx would be the same as CTA or CTB. Programming
CTx –
A capacitor from CTx to GND sets the period V
GAT1x
can be low ( V
GAT1x
< V
INx
+ 6 V) before it shuts the
channel down and declares a fault. V
GAT1x
will be low during startup and current limit. Low V
GAT1x
causes this pin
to source 10 µA into the external capacitor (C
Tx
). When V
CTx
reaches 1.35 V, the TPS2456A shuts the channel
off by pulling the GAT1x and GAT2x pins low, declares a fault by pulling the FLTx pin low, and latching off. A 200
Ω
internal pull down keeps this pin low during normal operation when not in current limit. It is normal to see a
sawtooth on this pin when the channel is latched off by a fault.
ENx –
Active high enable input. A low on ENx turns off the channel by pulling GAT1x and GAT2x low. An internal
200 k
Ω
resistor pulls this pin up to VINT. ENx may be left floating when the channel is to be permanently
enabled.
FLTx –
Active low open-drain output indicating that V
GAT1x
has been low ( V
GAT1x
< V
INx
+ 6 V) long enough trip
the fault timer and shut the channel down. FLTx may be left open if not used.
GAT1x –
Gate drive output for the protection MOSFET. This pin sources 30 µA to turn the MOSFET on. An
internal clamp prevents this pin from rising more than 14.5 V above INx.
Up to 30µA may be sunk while current limit is active. A fast trip (overcurrent), disable (from ENx), or fault timeout
enables a 10 µs, 1 A, discharge current and 14 mA pulldown. The pulldown will be released after 10 µs if only a
fast trip had occurred.
Setting ENx low holds GAT1x low. GAT1x may be left open if not used.
GAT2x –
Gate drive output for the blocking MOSFET. The blocking MOSFET prevents reverse channel current
when OUTx is higher than INx. This is often used when two input sources are ORed together. GAT2x sources 30
µA to turn the MOSFET on. GAT2x is low when ENx is low, ORENx is low, FLTx is low, a fast trip is active, or a
voltage reversal has occurred. A 10 µs, 1 A, discharge and 14 mA pulldown are applied when this occurs.
Copyright © 2012, Texas Instruments Incorporated
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An internal clamp prevents this pin from rising more than 14.5 V above OUTx. Setting the ORENx or ENx pins
low holds the GAT2x pin low.
GAT2x may be left open if not used.
INx –
Supply pin for the internal circuitry. A small bypass capacitor (e.g. 0.1 µF) is recommended for this pin.
MONx –
A resistor connected from this pin to ground forms part of the current limit programming. As the current
delivered to the load increases, so does the voltage on this pin. The current-limit circuit controls GAT1x to limit
channel current at a V
MONx
of 675 mV. The current limit circuit is inactive for lower values of V
MONx
.
Equation 1
through
Equation 4
define current limit and fast trip values using R
MONx
, R
SENSEx
, and R
SETx
. V
MONx
ORENx –
Active high input. Pulling this pin low disables the blocking function by pulling the GAT2x pin low.
Pulling this pin high (or allowing it to float high) allows the blocking function to operate normally. The M2x internal
diode may carry the load current when GAT2x is low and V
INX
> V
OUTX
.
An internal 200 k
Ω
resistor pulls this pin to VINT. ORENx may be left open when blocking is not used, or does
not require active control.
OUTx –
Senses the output voltage of the channel. This voltage is used by the biasing, blocking, and power good
circuits.
PGx –
Active low open-drain output. A low on PGx indicates that V
OUTx
has exceeded 10.63 V, and has not
fallen below 10.50 V. These thresholds are internally set, and modifying the OUTx connection may effect
blocking operation.
SENMx –
Senses the voltage on the load side of R
SENSEx
for use by the fast trip and current limiting circuits.
SENPx –
Senses the voltage on the source side of R
SENSEx
for use by the fast trip, UVLO and blocking circuits.
The fast trip overcurrent shutdown is activated at a V
SENP-SENM
of 0.1 V. UVLO trips when SENPx goes below 8.5
V for more than 440 ns (nominal), 295 ns (worst case).
SETx –
A resistor connected from this pin to SENPx sets the current limit level in conjunction with R
SENSEx
and
VINT –
This pin connects to the internal 2.35 V rail. A 0.1 µF capacitor must be connected from this pin to
ground. VINT is not designed to be a general-purpose bias rail.
8
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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ULY 2012
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs INPUT VOLTAGE
2.4
2.3
2.2
2.45
2.4
T
= 25°C
J
2.35
2.3
2.25
2.2
2.1
2
2.15
2.1
-40 -20
0
J
20
40
60
– Junction Temperature – °C
80
100 120
10 10.5
11 11.5
12 12.5
13 13.5
14
T
V
– Input Voltage – V
INx
Figure 6.
Figure 7.
CURRENT LIMIT THRESHOLD vs TEMPERATURE
BLOCKING TURNOFF THRESHOLD vs TEMPERATURE
-2.80
50.8
50.6
50.4
50.2
R
R
= 500
W
SETx
= 6800
W
-2.85
MONx
-2.90
-2.95
-3.00
-3.05
-3.10
-3.15
-40 -20
0
J
20
40
60
– Junction Temperature – °C
80
100 120
-40 -20
0
J
20
40
60
– Junction Temperature – °C
80
100 120
T
T
Figure 8.
Figure 9.
Copyright © 2012, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS (continued)
BLOCKING TURN ON THRESHOLD vs TEMPERATURE
12
11.5
11
10.5
10
9.5
9
-40 -20
0
J
20
40
60
– Junction Temperature – °C
80
100 120
T
Figure 10.
GAT1x,
10 V/div
GAT1x,
10 V/div
OUTx starting up into 1.8
W
(6.7 A, 80 W)
Output capacitance is 830
m
F
OUTx starting up into 500
W
(24 mA)
Output capacitance is 830
m
F
675 mV
675 mV
580 mV
MONx,
0.5 V/div
MONx,
0.5 V/div
40 mV
OUTx,
10 V/div
OUTx,
10 V/div
Time – 1 ms/div
Time – 1 ms/div
Figure 11. Startup into 500
Ω
, 830 µF Load
Figure 12. Startup into 80 Watt, 830 µF Load
10
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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ULY 2012
TYPICAL CHARACTERISTICS (continued)
GAT1x,
10 V/div
GAT1x,
10 V/div
OUTx shorted while driving 6.7 A load
Output capacitance is 47
m
F
OUTx shorted while driving 6.7 A load
Output capacitance is 47
m
F
MONx,
1 V/div
675 mV
620 mV
MONx,
1 V/div
620 mV
OUTx,
10 V/div
OUTx,
10 V/div
Time – 2 ms/div
Time – 1
m
s/div
Figure 13. Short Circuit Under Full Load (6.7 A) Wide
Figure 14. Short Circuit Under Full Load (6.7 A) Zoom View
OUTx overloaded while supplying 6.7 A
GAT1x,
10 V/div
2.9 V
GAT1x,
2 V/div
970 mV
675 mV
675 mV
OUTx starting into short circuit
MONx,
0.5 V/div
MONx,
0.5 V/div
OUTx,
10 V/div
OUTx,
20 mV/div
Time – 1 ms/div
Time – 1 ms/div
Figure 15. Startup into Short Circuit
Figure 16. Overloaded while Supplying 6.7 A
SYSTEM OPERATION
INTRODUCTION
The TPS2456A controls two 12-V channels, or power paths. The channels can draw from a single common
supply, or from two independent supplies. The following sections describe the TPS2456A operation and provide
guidance for designing systems around this device.
CONTROL LOGIC AND POWER-ON RESET
The TPS2456A circuitry draws bias power from any of the INx or OUTx pins through an internal preregulator that
generates VINT. A bypass capacitor from VINT to ground provides decoupling and output filtering for the internal
circuits. Bias supply ORing allows the internal circuitry to function regardless of which channels receive power or
are in a faulted state. The four external MOSFET drive pins (GAT1A, GAT1B, GAT2A, and GAT2B) are held low
during startup to ensure that the channels remain off. When the voltage on the internal VINT rail exceeds
approximately 1 V, the power-on reset (POR) circuit initializes the TPS2456A and allows normal operation.
Copyright © 2012, Texas Instruments Incorporated
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ENABLE FUNCTIONS
The TPS2456A has two external enable pins for each of the channels.
The GAT1x and GAT2x pins are held low when the ENx pin is low. A high on ENx enables GAT1x for normal
control by the startup and protection features. Toggling ENx low, then high, clears a latch-off condition after a
fault has occurred on the channel.
The GAT2x pin is held low when the ORENx or ENx pins are low. The reverse blocking comparator-driven state
machine controls GAT2x when ORENx and ENx pins are high.
ENx
ORENx
PROTECTION
(M1x, GAT1x)
BLOCKING
(M2x, GAT2x)
0
0
1
1
0
1
0
1
Disabled (low)
Disabled (low)
Enabled
Disabled (low)
Disabled (low)
Disabled (low)
Enabled
Enabled
Each of the four enable pins has an internal 200 k
Ω
pullup resistor to VINT.
POWER GOOD (PGx) OUTPUTS
The TPS2456A provides an active-low open-drain Power Good (PGx) output for each channel. PGx goes low
(output good indication) for rising V
OUTx
exceeding 10.63 V and PGx goes high for falling V
OUTx
below 10.5 V. A
100 µs deglitch filter aids in avoiding false indications due to noise.
FAULT (FLTx) OUTPUTS
The TPS2456A provides an active-low open-drain fault output for each channel. The FLTx output pulls low when
the channel has remained in current limit long enough for the fault timer to expire (V
CTx
> 1.35 V). A channel
experiencing a fault timeout shuts down and latches off. Toggle the faulted channel’s ENx low and high to clear
the fault and re-enable the channel.
CURRENT LIMIT AND FAST TRIP THRESHOLDS
Load current is monitored by sensing the voltage across R
SENSEx
, whose values typically lie in the range of 4 m
Ω
to 10 m
Ω
. Each channel features two distinct thresholds, a current-limit threshold and a fast-trip threshold.
The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel
exceeds the current limit threshold, V
GAT1x
is reduced, forcing the MOSFET into linear operation. This causes the
current flowing through the channel to settle to the value determined by the current limit threshold. For example,
when a module first powers up, it draws an inrush current to charge its load capacitance. The current-limit loop
ensures that this inrush current does not exceed the current limit threshold. M1 will dissipate much more power
in current limit than during normal operation. The fault timer circuit limits the interval M1 operates in this
condition.
There is a delay before channel current is regulated following the onset of an overload during normal operation.
The current limit circuit is able to sink 30 µA from the protection MOSFET gate. The delay is the result of the
MOSFET’s C
ISS
discharge from (V
INx
+ 13 V) to ( V
INx
+ V
T_M1x
) where V
T_M1x
is the protection MOSFET’s
threshold voltage. Overloads between the current limit and the fast trip threshold will be permitted for this period.
This is demonstrated by
Figure 16
. Currents above the fast trip threshold are handled by rapidly turning the
protection MOSFET off
with a strong
gate pulldown that is driven by a 10 µs oneshot. The fault timer starts and
the gate is allowed to rise after the oneshot completes in what resembles a normal startup.
The fast trip threshold protects the MOSFET and channel components against a severe short that creates a high
current faster than the current-limit loop can control. If (V
SENPx
– V
SENMx
) exceeds the 100 mV fast trip threshold,
GAT1x and GAT2x are immediately pulled to GND for a minimum of 10µs. The channel turns back on slowly,
allowing the current limit feedback loop time to take over. The fault timer period limits the duration the MOSFET
12
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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When the TPS2456A protects a supply output in configurations that allow the loads to hotplug, pay special
attention to coordinating load surges (due to input capacitance) and the fast trip threshold. The fast trip threshold
may need to be set 2–5 times higher than the current limit to accommodate this. Care must also be taken if the
INx voltages can have fast rising transients. The resulting charge current to capacitors on OUTx can potentially
exceed the fast trip threshold.
FAST TRIP AND CURRENT LIMITING
Figure 17
shows a simplified block diagram of the fast trip and current limit circuitry. Each channel requires an
external
N-channel protection MOSFET and three external resistors. These resistors allow the user to
independently set the fast trip threshold and the current limit threshold, as described below.
The fast trip function is designed to protect the channel against short-circuit events. If the voltage across R
SENSEx
exceeds 100 mV, the TPS2456A immediately turns off the protection MOSFET, M1x. The nominal fast trip limit
100 mV
I
F
T
x
=
R
SENSEx
(1)
The current limit circuit regulates V
GAT1x
to control the channel current from exceeding I
LIMITx
. The current limit
circuitry includes two amplifiers, A
1
and A
2
, as shown in
Figure 17
and
Figure 4
. Amplifier A
1
forces the voltage
across external resistor R
SETx
to equal the voltage
across external
resistor R
SENSEx
. The current that flows
through R
SETx
also flows through external resistor R
MONx
, generating a voltage on the MONx pin per
Equation 2
.
æ
ç
è
ö
÷
ø
R
SENSEx
´
I
SENSEx
V
MONx
=
´
R
MONx
R
SETx
(2)
Amplifier A
2
implements a slow-reacting current limit. As long as V
MONx
is less than 0.675 V, GAT1x operates
normally. When V
MONx
exceeds 0.675 V, amplifier A
2
causes a small current to be drawn from GAT1x. The gate-
to-source voltage of M1x drops until load current is reduced and the two inputs of amplifier A
2
balance. The
æ
ç
è
ö
÷
R
SETx
I
LIMITx
=
´
0.675 V
R
MONx
´
R
SENSEx
ø
(3)
(4)
I
´
R
´
R
LI
M
I
Tx
MONx SENSEx
R
=
SETx
0.675 V
The recommended value of R
MONx
is 6.81 k
Ω
. This resistor should be greater than 675
Ω
to prevent excessive
currents from flowing through the internal circuitry.
Copyright © 2012, Texas Instruments Incorporated
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I
FT,LIMIT
100
R
SENSEx
R
SETx
SETx
SENPx
SENMx
100mV
GA
T
1x
+
Fast Trip
Comparator
Current
Limit Amp
A1
675mV
+
A2
V
CP
MONx
R
MONx
Figure 17.
Overcurrent Protection Circuitry
TURN ON AND INRUSH SLEW RATE CONTROL
One of the main functions of a protection device is to provide a method of hot-plugging and starting up a unit in a
low-stress and controlled manner. Starting includes the ability to charge the output capacitance (on OUTx)
without overburdening the input power bus while minimizing the stress on the protection MOSFET. Two possible
charge-rate control methods are possible with the TPS2456A, current limited and gate dv/dt controlled.
I
dV
GAT1x(sourcing)
GAT1x
@
dt
C
Gate-M1x
(5)
where I
GAT1x(SOURCING)
equals the current sourced by the GAT1x pin (nominally 30 µA) and C
Gate-M1x
is the
reverse transfer capacitance, C
RSS
. Average C
RSS
may be approximated using the MOSFET V
GATE
vs. Q
g
graph
as C
RSS
=
Δ
Q
g
/ V
T
where
Δ
Q
g
is the width of the plateau region and V
T
is the gate plateau voltage. To simplify
the calculation, the MOSFET gate capacitances are assumed to be fixed, while in reality, there is a voltage
dependency. The output voltage tracks V
GATE_M1x
once it has exceeded the MOSFET threshold voltage if current
limit is not active. The inrush current is defined by the following equation for a purely capacitive load. Startup of a
switching converter load during inrush should be avoided by use of PGx to control the converter.
dV
dV
GAT1x
OUTx
I
=
´
C
=
´
C
O
U
T
x
INx_INRUSH
O
U
T
x
dt
dt
(6)
The actual inrush current is the lesser of the current limit (
Equation 3
) or dv/dt-limited inrush current.
To reduce the slew rate, increase C
Gate-M1x
by connecting additional capacitance from GAT1x to ground. Place a
resistor of at least 1000
Ω
in series with the additional capacitance to prevent it from interfering with the fast turn
off of the MOSFET.
14
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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FAULT TIMER PROGRAMMING
Each channel requires an external capacitor C
Tx
connected between the CTx pin and ground. The TPS2456A
sources 10 µA into C
Tx
when the gate voltage is low ((V
GAT1x
– V
INx
) < 6 V). The timer circuit interprets a low
V
GAT1x
as an indication that current limit is active. The TPS2456A pulls GAT1x and GAT2x to ground and latches
the channel off if current limit persists long enough for V
CTx
to reach 1.35 V. C
Tx
is discharged through a nominal
200
Ω
pull-down resistor when (V
GAT1x
– V
INx
) > 6 V) and FLTx is not active. The nominal fault time t
fx
is defined
1.35 V
t
fx
=
´
C
Tx
10 μA
OR
C
Tx
t
fx
´
10 μA
=
= t
f
x
´
7.4
´
10
-6
1.35 V
(7)
Converter startup typically sets the minimum t
fx
. There are three important intervals to consider when calculating
the time to set t
fx
, initial charge of the MOSFET gate to the threshold voltage, the interval as V
OUTx
rises to V
INx
,
and the interval for V
GAT1x
to exceed V
INx
by 6 V. Assume that a constant C
ISS
is charged in the first and third
periods since the MOSFET drain and source voltages do not change. The middle period may be controlled by
either current limit or gate dv/dt limit as previously discussed. Let V
TM1x
be the MOSFET gate voltage to sustain
the inrush current.
Gate dv/dt Limited
Inrush
C
ISS_M1x
´
6 V
–
V
T_M1x
C
ISS_M1x
´
V
TM1x
C
RSS_M1x
´
V
+
(
I
GAT1x
)
IN1x
t
INRUSH
=
+
I
GAT1x
I
GAT1x
Current Limited Inrush
C
ISS_M1x
´
6 V
–
V
C
ISS_M1x
´
V
TM1x
(
I
GAT1x
)
C
OUTx
´
V
T_M1x
IN1x
t
INRUSH
=
+
+
I
GAT1x
I
LIMITx
(8)
Many of these parameters have wide tolerance, thus, the above approximation provides an initial estimate.
Provide sufficient margin in the C
Tx
selection to assure the channel starts reliably while not becoming overly long.
Shorter fault times reduce the stresses imposed on the protection MOSFET under fault conditions, permitting the
use of smaller, less expensive protection MOSFETs.
ENx RESET PERIOD
The TPS2456A will latch off after a current limit that persists long enough to trip the fault timer. The TPS2456A
may be re-enabled by cycling the ENx false (low), then high. There is a minimum low period required to fully
reset C
CTx
that is determined by the R x C period where R is the internal discharge resistance. Calculate the
minimum period as t
ENx_LOW_MIN
= C
CTx_MAX
x 400
Ω
x 3. Assuming C
CTx_MAX
is 22 nF at 20% tolerance,
t
ENx_LOW_MIN
= (22 nF x 1.2) x 400 x 3 = 31.7 µs. t
ENx_LOW_MIN
should always be greater than 100 ns.
BLOCKING OPERATION
Each channel may use an external MOSFET (M2x) to provide reverse blocking. This feature is often used where
two inputs are ORed together to a common output for redundancy. Blocking protects the common output from
being drawn down if an input is shorted, and maintains the independence of both inputs. Blocking may not be
required in all system topologies. The TPS2456A pulls the GAT2x pin high when V
(INx–OUTx)
exceeds 10 mV, and
it pulls the pin low when this differential falls below –3 mV (V
OUTx
is greater than V
INx
). These thresholds provide
13 mV of hysteresis to help prevent false triggering as shown in
Figure 18
. This technique will allow some
The blocking MOSFET is oriented so its body diode conducts forward current and blocks reverse current. The
body diode does not normally conduct current because the MOSFET turns on when the voltage differential
across it exceeds 10 mV.
Copyright © 2012, Texas Instruments Incorporated
15
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V
INx
+ 13V
GND
(V
INx
-V
OUTx
)
Figure 18.
Blocking Thresholds
APPLICATION INFORMATION
SYSTEM DESIGN CONSIDERATIONS
The TPS2456A has two independent 12 V sections which provide protection and blocking (ORing). These
sections may be used in multiple configurations.
•
TPS2456A on the power input of a system
–
–
–
Blocking protects output when one of the inputs is shorted
Two independent loads powered by two separate or one common input rail
Blocking not required
Two redundant input rails ORed (no protection) to one common output
–
–
•
TPS2456A on the power output of a system
–
Up to two output rails with protection
–
–
Protection isolates faulted output bus
Enable can be used to turn output on and off
–
Up to two output power rails with protection and blocking
Used where multiple outputs are tied together
–
The system power architecture drives the topology that best suits a particular design.
DESIGN EXAMPLE: CURRENT LIMITED START-UP
The following example is for a single channel protection circuit using current-limited inrush control. The design of
the second channel would follow the same procedure and is not shown since it is redundant.
For this design example, a system board with 1000 µF of capacitance and a dc load of 1.6
Ω
(or 7.5 A) must be
able to be hot plugged into a 12 V main bus supply. The main bus supply has a peak fault current capability of
20 A. Operating above 20 A of current draw runs the risk of opening a circuit breaker and shutting the system
down. The average current budgeted for the system board is 7.5 A under normal conditions. The main bus can
supply up to 10.1 A peak for up to 10 ms during start-up or transient conditions. This procedure assumes that the
inrush current is not limited by the gate charge rate. The basic system block diagram is shown in
Figure 19
.
16
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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ULY 2012
Figure 19.
12 V Main Bus
Select R
SENSEx
The first step is to calculate R
SENSEx
which sets the fast current trip point, I
FTx
. This is the maximum current that
can pass through M1x and is meant to protect against short circuits. Calculate R
SENSEx
using
Equation 9
for a
peak fault current (I
FTx
) of 20 A.
100mV 100mV
=
R
SENSEx
=
= 5mΩ
I
FTx
20A
(9)
The R
SENSEx
resistor is in series with the main power path and should have a power rating sufficient to support
the full load current. The 12 V main bus has budgeted 10.1 A for this board, so this is the value of limit used for
further calculations including the power dissipated in R
SENSEx
. The power dissipated by R
SENSE
is calculated using
Equation 10
. A higher wattage rating should be used based on local derating practice (for example 50%).
P
RSENSEx
=
I
LIMITx
2
×
R
SENSEx
=
1
0.
1
2
×
5m
W
= 0.51Watts
(10)
Select R
SETx
Next, R
SETx
is calculated to set the channel current limit (I
LIMITx
) to 10.1 A. R
MONx
is also a variable in the
calculation of R
SETx
. Use the recommended 6.81 k
Ω
for R
MONx
(although other values can be used) and 10.1 A
for I
LIMITx
to calculate R
SETx
.
I
LIMITx
×R
MONx
×R
SENSEx
10.1
A
×
6
.81k
W
×
0.005
W
R
SETx
=
=
= 509
W
0.675V
0.675V
(11)
Choose R
SETx
as the closest standard value, 511
Ω
.
Estimate Output Charge Time
The system can provide 10.1 A of peak current for 10 ms. This current can be used for start-up of the system
board as long as the output capacitance can be charged up to 12 V in less than 10 ms while also supplying
current to the load resistance connected in parallel to the output capacitor. The charge time is estimated using
Equation 12
. For this equation, V
OUTx
is the final nominal voltage for the board (12 V), R
LOAD
is the dc load of the
board (1.6
Ω
), and there is a small amount of time for the pass transistor’s gate capacitance to charge to the
threshold voltage. This time, typically around 100 µs, is added to the end of the equation to provide a better
estimate of the total start-up time.
Copyright © 2012, Texas Instruments Incorporated
17
SLVSBI8
–
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ULY 2012
æ
ç
ç
ö
I
LIMITx
×R
LOADx
– V
OUTx
÷
÷
÷
÷
ø
t
CHG
»
-R
LOADx
×
C
LOADx
×ln
+100
m
s
ç
ç
è
I
LIMITx
×R
LOADx
(12)
æ
ç
è
ö
10.1
A
×
1.6
W
-12V
10.1
A
×
1.6
W
÷
÷
÷
ø
ç
t
CHG
»
-1.6
W
×1000
m
F×ln
t
CHG
»
2.27ms
+100
m
s
ç
(13)
(14)
The estimated time to charge the output is 2.27 ms. It is safe to allow the board to power up using the peak
current limit because t
CHG
is below the 10ms target.
Equation 12
assumes there is a resistive load on the output during the ramp up so the output voltage has an
“RC” shape.
The output capacitance charges linearly if the load is purely capacitive, simplifying the charge time
equation to the following.
C
LOADx
×
V
OUTx
t
CHG
=
+100
m
s
I
LIMIT_M1x
(15)
Select M1x
The next design step is to select M1x. The TPS2456A is designed to use N channel MOSFETs as protection
devices. The maximum MOSFET gate to source voltage rating, V
GS-MAX
, must be high enough to support the
highest of the gate drive (14.5 V) or input voltage.
The next factor to consider is the drain to source voltage rating, V
DS-MAX
, of the MOSFET. From a dc perspective,
the MOSFET needs to withstand the input power supply voltage of 12 V for this example. However; the MOSFET
can be exposed to high voltage spikes during fault conditions. For this reason, a MOSFET with a substantially
higher V
DS-MAX
rating improves the system reliability and provides voltage headroom for transient protection
(snubber, TVS, diodes, and so on). Look for a V
DS-MAX
rating with a minimum of twice of the input power supply
voltage.
Next, the dc power loss of the MOSFET must be considered. The power dissipation of the MOSFET is directly
related to the R
DS(on)
of the MOSFET. The dc power dissipation for the MOSFET can be calculated using
2
P
Dx
= R
DS(on)_M1x
×
I
LIMITx
(16)
Taking these factors into consideration, the TI CSD16403Q5A was selected for this example. The
CSD16403Q5A has a V
GS-MAX
rating of 16 V, V
DS-MAX
rating of 25 V, an R
DS(on)
of 2.2 m
Ω
, and an R
θ
JA-MAX
of 51
°C/W.
During normal circuit operation, the MOSFET can have up to 10.1 A flowing through, which equates to 0.22 W
(I
2
xR) and an 11°C rise in junction temperature (P x R
θ
JA-MAX
). This is well within the data sheets limits for the
MOSFET. The power dissipated during a fault (e.g. output short) is substantially larger than the steady-state
power. The power handling capability of the MOSFET needs to be checked during fault conditions.
Most MOSFET data sheets provide a Safe Operating Area (SOA) plot. This plot can be used to check if the
QSD16403Q5A. The maximum fault current is set to 20 A for the 12
V input bus.
This point can be located on
Figure 20
. The diagonal lines tell the length of time this transient can be safely applied to the QSD16403Q5A.
The transistor
can survive a 12 V, 20 A transient for approximately 9 ms.
18
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
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ULY 2012
1k
100
10
1ms
10ms
100ms
1
Area Limited
by R
DS(on)
1s
0.1
0.01
Single Pulse
= 94
o
C/W (min Cu)
DC
R
q
JA
0.01
0.1
1
10
100
12
− Drain
T
o
S
ource Voltage − V
V
DS
Figure 20.
Drain To Source Voltage
The turn off time of the TPS2456A and MOSFET should be taken into account. The TPS2456A detects the fault
condition as soon as the current through the sense resistor reaches 20 A. There is a 300 ns maximum
propagation delay for the TPS2456A to start discharging the MOSFET gate. The MOSFET has an additional
turn-off delay due to gate discharge (see the Electrical Characteristics table, Sinking current – Fast turnoff). The
total delay for the TPS2456A and the CSD16403Q5A is approximately 310 ns. The fault current continues to rise
above 20 A for this period. The rise of the fault current is determined by any inductance and resistance in the
power path as well as the impedance of the input voltage source. Continuing to follow the 12 V line up on the
SOA curve, it can be seen that the CSD16403Q5A could handle peak currents up to 180 A for 1 ms, giving
substantial margin in this design. This makes this transistor a good choice for this application.
Output Charge Time Refinement
A more accurate charge time can be calculated using
Equation 17
, now that the MOSFET has been chosen. This
is the same as
Equation 15
, but the 100 µs term is
replaced with the
variables that determine the time it takes to
charge the
gate of the MOSFET
up to the threshold voltage. The threshold voltage used in this equation should
be the voltage where the Mosfet starts to conduct higher currents. This can be found in the MOSFET data sheet
from graphs showing I
D
vs. V
GS
. For the CSD16403Q5A, the V
T_M1x
is 1.6 V, and C
ISS
is 2040 pF. The term I
G
in
Equation 17
is the GAT1x sourcing current, typically 30 µA. Using these values,
Equation 17
gives a charge time
æ
ç
ç
ö
V
T_M1x
×
C
ISS_M1x
I
LIMITx
×R
LOADx
– V
OUTx
÷
÷
÷
÷
ø
t
CHG
= -R
LOADx
×
C
LOADx
×ln
+
ç
ç
è
I
LIMITx
×R
LOADx
I
G
(17)
Select C
Tx
The next step is to determine the minimum fault timer period. In the previous section, the change time calculation
yielded 2.28 ms. This is the amount of time it takes to charge the output capacitor up to the final output voltage.
However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the
TPS2456A is in current limit. The fault timer continues to run until V
GATE_M1x
is 6 V above the input voltage. Some
additional time must be added to the charge time to account for this additional gate voltage rise. The minimum
æ
ç
ç
ö
(6 V + V
TM1x
)
×
C
ISS_M1x
I
LIMITx
×R
LOADx
– V
OUTx
÷
÷
÷
÷
ø
t
TMR_MIN
= -R
LOADx
×
C
LOADx
×ln
+
ç
ç
è
I
LIMITx
×R
LOAD
I
G
(18)
Copyright © 2012, Texas Instruments Incorporated
19
SLVSBI8
–
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ULY 2012
Using the example numbers in the above equation leads to a minimum fault timer time of 2.688 ms. The fault
timer must be set to a value higher than 2.688 ms to avoid turning off during start-up but lower than any
maximum time limit. There is a maximum time limit set by the SOA curve of the MOSFET. Referring back to
Figure 20
, the CSD16403Q5A SOA curve, the MOSFET can tolerate 10.1 A with 12 V across it for approximately
20 ms. However;
the input power supply can only supply the 10.1 A for 10 ms. Therefore, the fault timer should
be set to between 2.688 ms and 10 ms. For this example, select 8 ms to allow for variation of system parameters
such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in
Equation 19
as 59 nF. Select a the next highest standard value, 62 nF, yielding an 8.37 ms fault time.
t
FAULT
×10
m
A
0.008s×10
m
A
C
Tx
=
=
= 59nF
1.35V
1.35V
(19)
Blocking Device, M2x
Since this example uses a single channel, there is no need for the blocking MOSFET, and it can be left out of the
circuit. No connection needs to be made to the GAT2x or ORENx pins.
DESIGN EXAMPLE: GATE RAMP LIMITED STARTUP
In the first example, the output capacitance is charged in current limit. In some applications, the current limit is
the absolute maximum that the circuit should see, so charging the output up in current limit is not an option. In
this case, it is necessary to slow down the output voltage ramp so that the current limit is not reached. This can
be done by adding additional capacitance to M1x’s gate.
The gate of the pass transistor is driven by a 30 µA (typical) current source. The current charges the gate to
source and gate to drain (C
rss
) capacitance, producing a voltage ramp at the gate. The time of the ramp can be
lengthened by adding a capacitor, C
ADD
, between the gate and ground. A 1 k
Ω
resistor should be placed in
Figure 21.
With C
ADD
, the output voltage ramp is equal to:
dV
GATE_M1x
dV
OUTx
dt
I
G
=
=
dt
C
RSS_M1x
+
C
ADD
(20)
(21)
The peak current, I
INX-PEAK
, that is reached with the new ramp rate is:
V
OUTx
C
OUTx
×
I
G
R
LOADx
(C
RSS
+
C
ADD
I
=
+
INx_PEAK
)
20
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
J
ULY 2012
C
ADD
can be adjusted so that I
INx_PEAK
is less than I
LIMITx
avoiding current limit start-up. Using a controlled gate
ramp requires lower peak current, but takes longer to charge the output capacitance. The length of the fault time
needs to be selected to accommodate this longer ramp up time. The minimum time the fault timer should be set
V
T_M1x
C
ISS
+
C
ADD
( )
V
OUTx
× C
RSS
+
C
ADD
6
×
C
ISS
+
C
ADD
)
(
)
(
t
TMR_MIN
=
+
+
I
G
I
G
I
G
(22)
BYPASS CAPACITORS
It is a good practice to provide low-impedance ceramic capacitor bypassing of INx and OUTx. Values in the
range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and prefer to minimize the value of the bypass capacitor.
Input capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low
impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems. In
systems with little or no bus hold up capacitance on the backplane, it is common to have no capacitance at the
board input. This helps minimize transients at plug in.
Filter capacitors at the output of a redundant plug-in board are useful for controlling voltage transients, but they
may can cause problems when the board is inserted into an active bus. If the output capacitor charge from an
active bus is not limited, the inrush surge might engage the active supply’s fast-trip shutdown. One possible
solution is to put a few Ohms of resistance in series with the capacitor to limit inrush below the fast trip level.
TRANSIENT PROTECTION
If the TPS2456A is used in applications which have large input and output capacitors, voltage transients during
load steps or short circuits are controlled and pose no problems.
TPS2456A devices are sometimes deployed systems that may have long, inductive feed or load
interconnections. The effect of the inductance, with little local capacitance, gives rise to potential voltage
transient issues. A simplified model of this is shown in
Figure 22
. Channel current transients may be caused by
events such as hot-plug, output shorts with fast
turnoff, or abrupt
load changes. The combination of input
inductance and an abrupt load decrease causes a positive voltage spike on the TPS2456A INPUT pins. The
combination of output inductance and an abrupt load decrease will cause a negative voltage spike on the
TPS2456A OUTPUT. These transients have the potential to exceed the Absolute Maximum Ratings, either
damaging the TPS2456A or causing undesired operation.
NOTE: L
P
= Parasitic Inductance (not all instances equal)
R
P
= Parasitic Resistance (not all instances equal)
Figure 22.
System Transient Model
Copyright © 2012, Texas Instruments Incorporated
21
SLVSBI8
–
J
ULY 2012
An analysis must be performed to determine the need for transient protection.
Equation 23
allows the designer to
estimate the voltage spike due to current interruptions.
L
V
SPIKE
= V
+ I
LOAD
INIT
C
(23)
Where:
V
INIT
= initial voltage at terminal being analyzed before the current is interrupted
L = combined inductance of feed and RTN lines in series with interrupted current
C = capacitance at point of computation
I
LOAD
= current immediately before circuit is opened
An approximation for the inductance of a straight wire is:
L
≈
[0.2 × length_in_meters × (In(4 × length/diameter) – 0.75)] nH
The capacitance in
Equation 23
, at INPUT, consists of parasitic capacitance and any intentional bypass
capacitance. This
implies that the
transients can be controlled by the addition of sufficient capacitance.
Equation 24
can be used to calculate the capacitance required to limit the voltage spike to a desired level above
the nominal
voltage.
2
L
´
I
L
O
A
D
C =
2
V
(
–
V
NOM
)
SPIKE
(24)
TRANSIENT PROTECTION SOLUTIONS
Typical protection solutions involve capacitors, TVSs ( Transient Voltage Suppressors ) and/or a Schottky diode.
A TVS and small bypass capacitor at INPUT (see
Figure 22
) are the most likely solutions to solve input voltage
overshoot. The TVS must be selected so that its
clamping is
below the Absolute Maximum Rating (17 V) at the
anticipated fault current. For example, the SMCJ13A data sheet specifies a maximum clamping voltage of 21.5 V
(which exceeds the Absolute Maximum voltage) at 69.7 A. The actual clamping voltage at the fault current (I
FT
)
may be within the Absolute Maximum; however, the clamp voltage at lower currents must be estimated to verify.
By modeling the TVS as a perfect voltage clamp in series with a resistor, the clamping voltage may be estimated
V
CL_MAX
–
V
BR
_
M
IN
21.5 V
–
14.4 V
69.7 A
–
1 mA
R
SERIES
=
=
= 0.102
W
I
PEAK_PULSE
–
I
TEST
(25)
The maximum permitted clamping current for this device is found in
Equation 26
. This is a worst case (low)
number.
V
–
V
BR_MAX
17 V
–
15.9 V
ABS_MAX
I
=
=
= 10.8 A
CL_MAX
R
0.102
SERIES
(26)
A Schottky diode and capacitor across the OUTPUT (
Figure 22
) are the most likely solutions to clamp the
transient energy and limit the negative voltage
excursion. Although
the Schottky diode absorbs most of the
energy, the extremely fast di/dt at shutoff allows some of the leading edge energy to couple through the parasitic
capacitances of the protection and blocking MOSFET (C
DS
, C
GS
, C
GD
) to the GAT1x and GAT2x pins. Protection
for these pins is provided by 100
Ω
resistors which have little effect on normal operation but provide good
isolation during transient events.
Equation 24
gives insight into selection of transient protection capacitors for both INPUT and OUTPUT; however,
there are concerns
with adding a lot of capacitance in some situations. See the
BYPASS CAPACITORS
section
regarding considerations and limitations
PCB layout of the protection is critical to its performance. The layout should minimize the impedance between
the TPS2456A and the protection in order to provide the best clamping.
22
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
J
ULY 2012
OUTPUT BLEED RESISTANCE
The OUTx pin sources a small amount of current when the channel input is powered, but disabled in non-
redundant configurations (output is unpowered). The leakage can be modeled as a 6 V source in series with a
280 k
Ω
resistor, allowing approximately 21.4 µA into a short. This leakage can charge a high-impedance load to
approximately 6 V. If this is unacceptable, control the output voltage in this state by adding a load resistor from
V
BLEED
R
=
´
280 k
W
BLEED
(6 V
–
V
)
BLEED
(27)
CONTROLLING FAULT CURRENT in REDUNDANT POWER TOPOLOGIES
System topologies such as
Figure 1
are often used to provide power source redundancy. This permits the load to
run from either source, or
potentially
both in parallel. Blocking permits the load to operate uninterrupted in the
event of either source failing open or shorting to GND. However, this topology permits the load to draw twice the
channel fault current (I
LIMITx
) for two closely matched sources.
The simple configuration of
Figure 23
programs the total load fault current to a fixed value independent of the
number of channel feeds to
the load. The
current limit thresholds now apply to the sum of the currents delivered
by the redundant channels. When implementing this redundant mode, it is recommended that all of the channels
use the same R
SENSEx
and R
SETx
values. This configuration does not foster sharing or smooth transitions
between sources, it simply permits the power to flow from the higher source, but limits the maximum load current
to a fixed value.
Figure 23.
Fixed Fault Current Application
CURRENT FEEDBACK TO A SHELF CONTROLLER
A shelf controller can monitor channel currents by observing V
MONx
, which is proportional to the current through
R
SENSEx
. The voltage on MONx can be directly sampled with an analog circuit (e.g. a comparator) or sampled
with an Analog to Digital Converter (ADC) to provide a digital representation of the current.
Figure 24
shows a
typical system configuration using a multiplexer and ADC (analog to digital converter) to
monitor the current
in
both channels of the TPS2456A. It has been assumed that the normal 0 V to 0.675 V range of V
MONx
is suitable
for the ADC input. If this is not the case, operational amplifier circuits should be used to buffer and scale these
signals. It is not advisable to add capacitance to the MONx pins as this effects the current-limit loop.
Copyright © 2012, Texas Instruments Incorporated
23
SLVSBI8
–
J
ULY 2012
Figure 24.
The output of the MONx pin is a current proportional to the current passing through the pass transistor as defined
in
Equation 2
. The current flowing out of the MONx pin is converted to a voltage by R
MONx
which is typically 6.81
k
Ω
. Any circuitry
connected to the MONx pin should either have an input impedance much higher that R
MONx
to
reduce measurement and limiting error, or the value of the parallel combination must be adjusted. The output of
the MONx pin can also be buffered using a unity gain, non-inverting operational amplifier if necessary.
LAYOUT CONSIDERATIONS
TPS2456A applications require layout attention to ensure proper performance and minimize susceptibility to
transients and noise. In general, all runs should be as short as possible, but the following list deserves first
consideration.
1. When
used, decoupling capacitors on INA and INB should have minimal length to the pin and to GND
2. SENMx
and SENPx runs must be short and run side-by-side to maximize common mode rejection. Kelvin
Figure 25.
Recommended R
SENSE
Layout
3. SETx
runs need to be short on both sides of R
SETx
.
4. Power
path connections should be as short as possible and sized to carry at least twice the full load current,
more if possible.
24
Copyright © 2012, Texas Instruments Incorporated
SLVSBI8
–
J
ULY 2012
5. Connections
to GND and MONx pins should be minimized after the connections above have been placed.
6. The
device dissipates low power so soldering the powerpad to the board is not a requirement. However,
doing so improves thermal performance and reduces susceptibility to noise.
7. The
board should use a single point ground scheme. The current return path for both channels should be
isolated from each other as much as possible and tie together at a single point. This helps to reduce ground
bounce and false turn offs in one channel when there is a fault in the other channel. Also, sensitive analog
grounds (such as the ground connections of R
MON
x and C
Tx
) should be run separate from the power path
grounds. This analog ground must also tie to the two power path grounds at a single point.
Figure 26
shows
path, the analog ground, and the single point tying them together is highlighted in the figure.
Figure 26.
8. Protection
devices such as snubbers, TVS, capacitors or diodes should be placed physically close to the
device they are intended to protect, and routed with short trances to reduce inductance. For example, the
protection Schottky diode shown in
Figure 1
should be physically close to the source of the pass transistor
Copyright © 2012, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2456ARHHR
TPS2456ARHHT
ACTIVE
ACTIVE
VQFN
VQFN
RHH
RHH
36
36
2500 RoHS
& Green
250 RoHS
& Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
2456A
2456A
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
18-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
TPS2456ARHHR
TPS2456ARHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
18-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2456ARHHR
TPS2456ARHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHH 36
6 x 6, 0.5 mm pitch
VQFN – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225440/A
PACKAGE OUTLINE
RHH0036B
VQFN – 1 mm max height
S
C
A
L
E
2
.
3
0
0
PLASTIC QUAD FLATPACK – NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
6.1
5.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
4.1 0.1
2X 4
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
18
10
9
19
SYMM
37
2X 4
32X 0.5
1
27
0.30
36X
PIN 1 ID
0.18
36
28
0.1
C A B
0.65
0.45
36X
0.05
4225414/A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
EXAMPLE BOARD LAYOUT
RHH0036B
VQFN – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
(
4.1)
SYMM
SEE SOLDER MASK
DETAIL
36
28
36X (0.75)
1
27
36X (0.24)
(1.8)
TYP
32X (0.5)
(0.68)
TYP
37
SYMM
(5.65)
(R0.05) TYP
(
0.2) TYP
VIA
19
9
10
18
(0.68)
TYP
(1.8) TYP
(5.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225414/A 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE STENCIL DESIGN
RHH0036B
VQFN – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
9X (
1.16)
(1.36)
TYP
36
28
36X (0.75)
27
1
36X (0.24)
32X (0.5)
(1.36) TYP
37
SYMM
(5.65)
(R0.05) TYP
19
9
18
10
SYMM
(5.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 37
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4225414/A 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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