tps2521
| Part # | tps2521 |
Download  | tps2521 |
TPS2521xx
具有输入反极性保护功能
的
2.7V
至
5.7V
、
4A
、
31 mΩ
真反向电流阻
断电子保险丝
输出电流限制级别可通过单个外部电阻设定。还可能通
过测量整个电流限制电阻的压降实现对输出负载电流的
准确感应。
1
特性
• 宽工作输入电压范围
：
2.7V
至
5.7V
• 绝对最大值
为
28V
• 可耐受高
达
–
15V
的负电压
• 具有低导通电阻的集成式背对
背
FET
：
R
ON
= 31
m
Ω
（
典型值
）
浪涌电流有特别要求的应用可以通过单个外部电容器设
定输出转换率。通过将输出钳制到安全的固定最大电压
（
可通过引脚选择
），
可以保护负载免受输入过压情况
的影响。
• 具有真反向电流阻断功能的理想二极管运行状态
• 快速过压钳
位
(OVC)
，
可通过引脚选择阈值
（
3.8V
、
5.7V
），
响应时间
为
5
μ
s
（
典型值
）
• 过流保护
，
具有负载电流监控器输
出
(ILM)
器件采用
2mm × 2mm 10
引脚
HotRod QFN
封装
，
旨
在改善热性能并减小系统尺寸。
这些器件的额定工作结温范围
为
-40°C
至
+125°C
。
– 有效电流限制响应
– 可调节阈
值
(I
LIM
)
：
0.5A
至
4.44A
器件信息
封装尺寸
（
标称值
）
器件型号
•
I
LIM
> 1A
时精度
为
±10%
– 可调瞬态消隐计时
器
(ITIMER)
，
支持高
达
2 x
I
LIM
的峰值电流
TPS2521xxRPW
QFN (10)
2mm × 2mm
(1)
如需了解所有可用封装
，
请参阅数据表末尾的可订购产品附
录。
– 输出负载电流监控精度
：
±6% (I
OUT
≥
1A)
• 通过快速跳变响应实现短路保护
– 响应时间
为
500 ns
（
典型值
）
– 可调
节
(2 × I
LIM
)
阈值和固定阈值
• 带有可调节欠压锁定阈
值
(UVLO)
的高电平有效使
能输入
V
O
U
T
V
IN
= 2.7 to 5.7 V
IN
OUT
C
O
U
T
PGTH
EN/U
V
L
O
V
L
O
G
I
C
TPS2
5
2
10x
• 可调节的输出压摆率控
制
(dVdt)
• 过温保护
OVCS
E
L
PG
I
T
I
MER
dV
d
t
GND
ILM
• 具有可调节阈
值
(PGTH)
的电源正常状态指
示
(PG)
•
UL 2367
认证
R
I
L
M
C
I
T
I
MER
C
DV
D
T
– 文件编
号
E169910
–
R
ILM
≥
750
Ω
简化版原理图
• 获
得
IEC 62368-1 CB
认证
• 小尺寸
：
QFN 2mm × 2mm
，
0.45mm
间距
2
应用
• 适配器输入保护
• 企业级存
储
– RAID/HBA/SAN/eSSD
•
USB PD
端口保护
• 服务器、
PC
主板、附加卡
• 显示器和扩展坞
3
说明
TPS2521x
系列电子保险丝是采用小型封装的高度集成
电路保护和电源管理解决方案。此类器件只需很少的外
部元件即可提供多种保护模式
，
能够非常有效地抵御过
载、短路、电压浪涌、反极性和过多浪涌电流。借助集
成的背对背
FET
，
始终可以阻止从输出端到输入端的
反向电流流动
，
从而使该器件非常适合需要负载侧能量
保持存储解决方案以防输入电源发生故障的系统。
本文档旨在为方便起见
，
提供有
关
TI
产品中文版本的信息
，
以确认产品的概要。有关适用的官方英文版本的最新信息
，
请访问
Table of Contents
4 Revision History
注
：
以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2021) to Revision A (March 2022)
Page
Copyright © 2022
T
e
xas Instruments Incorporated
2
5 Device Comparison Table
Part Number
TPS25210A
TPS25210L
Overvoltage Response
Overcurrent Response
Active Current Limit
Response to Fault
Auto-Retry
Pin Selectable OVC (3.8 V/5.7 V)
Latch-Off
Copyright © 2022
T
e
xas Instruments Incorporated
3
6 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
ITIMER
ILM
OVCSEL
9
8
2
3
5
6
PG
GND
DVDT
PGTH
7
4
图
6-1. TPS2521x RPW Package 10-Pin QFN Top View
表
6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
8.3.2
for details.
Analog
Input
EN/UVLO
1
Analog
Input
OVCSEL
PG
2
3
4
Power Good indication. This pin is an Open Drain signal which is asserted High when the
internal power path is fully turned ON and PGTH input exceeds a certain threshold. Refer
Digital
Output
Analog
Input
PGTH
IN
5
6
Power Power
input
Power Power
output
OUT
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
Analog
Output
DVDT
GND
7
8
This pin is the ground reference for all internal circuits and must be connected to system
GND.
Ground
This pin is a dual function pin used to limit and monitor the output current. An external
resistor from this pin to GND sets the output current limit threshold during start-up as well
as steady state. The pin voltage can also be used as analog output load current monitor
Analog
Output
ILM
9
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
output current can temporarily exceed set current limit (but lower than fast-trip threshold)
before the device overcurrent response takes action. Leave this pin open for fastest
Analog
Output
ITIMER
10
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4
7 Specifications
7.1 Absolute Maximum Ratings
Parameter
Pin
MIN
MAX UNIT
max(
–
15, V
OUT
–
28
28
V
V
Maximum Input Voltage Range,
–
40
℃
≤
T
J
≤
125
℃
21)
V
IN
IN
max(
–
15, V
OUT
–
Maximum Input Voltage Range,
–
10
℃
≤
T
J
≤
125
℃
22)
min (28, V
IN
+ 21)
min (28, V
IN
+ 22)
Maximum Output Voltage Range,
–
40
℃
≤
T
J
≤
125
℃
Maximum Output Voltage Range,
–
10
℃
≤
T
J
≤
125
℃
Minimum Output Voltage Pulse (< 1 µs)
–
0.3
–
0.3
–
0.8
–
0.3
V
OUT
OUT
OUT
V
OU
T
,
PLS
EN/UVLO
OVCSEL
dVdt
6.5
V
V
V
OVCSEL
V
dVdT
V
ITIMER
V
PGTH
V
PG
Maximum OVCSEL Pin Voltage Range
Maximum dVdT Pin Voltage Range
Maximum ITIMER Pin Voltage Range
Maximum PG Pin Voltage Range
Maximum ILM Pin Voltage Range
Maximum Continuous Switch Current
Junction temperature
Internally Limited
Internally Limited
Internally Limited
–
0.3
V
ITIMER
PGTH
PG
V
6.5
6.5
V
V
–
0.3
V
ILM
ILM
Internally Limited
Internally Limited
Internally Limited
V
I
MAX
IN to OUT
A
T
J
°C
°C
°C
T
LEAD
T
STG
Maximum Lead
T
e
mperature
300
150
Storage temperature
–
65
(1) Operation
outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions
. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) If
this pin has a pull-up up to V
IN
, it is recommended to use a resistance of 350 k
Ω
or higher to limit the current under conditions where
IN can be exposed to reverse polarity.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
V
(ESD)
Electrostatic discharge
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2022
T
e
xas Instruments Incorporated
5
MAX UNIT
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
V
IN
Input Voltage Range
Output Voltage Range
IN
2.7
min (23, V
IN
+ 20)
V
V
V
V
V
V
V
V
OUT
OUT
V
EN/UVLO
Enable Pin Voltage Range
EN/UVLO
dVdt
V
dVdT
V
PGTH
V
PG
dVdT Capacitor Voltage Rating
PGTH Pin Voltage Range
PG Pin Voltage Range
V
IN
+ 5 V
PGTH
PG
V
ITIMER
R
ILM
I
MAX
ITIMER Pin Capacitor Voltage Rating
ILM Pin Resistance
ITIMER
ILM
4
750
6650
4
Ω
IN to OUT
A
Continuous Switch Current, T
J
≤
125
℃
Junction temperature
T
J
125
°C
–
40
(1) The
input operating voltage should be limited to the selected Output Voltage Clamp threshold as listed in the Electrical Characteristics
section
(2) For
supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 k
Ω
.
(3) For
systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 k
Ω
to limit the current through the pin.
7.4 Thermal Information
TPS2521xx
RPW (QFN)
10 PINS
1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
R
θ
JA
Ψ
JT
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Ψ
JB
(1) For
more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report.
(2) Based
on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based
on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
Copyright © 2022
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6
7.5 Electrical Characteristics
(
T
e
st conditions unless otherwise noted)
–
40°C
≤
T
J
≤
125°C, V
IN
= 5
V
,
O
UT = Open, V
EN/UVLO
= 2
V
,
O
VCSEL = Open,
R
ILM
= 750
Ω
, dVdT = Open, ITIMER = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPP
L
Y
(
IN)
V
UVP(R)
V
UVP(F)
I
Q(ON)
IN Supply UVP Rising Threshold
IN Supply UVP Falling Threshold
2.44
2.35
2.53
2.42
411
2.64
2.55
593
620
V
V
IN Supply Quiescent Current
µA
µA
µA
µA
µA
µA
I
Q(ON)
IN Supply Current during OVC
426
I
Q(ON)
IN Supply Quiescent Current during RCB, V
OUT
= V
IN
+ 1 V
186
I
Q(OFF)
I
SD
IN Supply OFF State Current (V
SD(F)
< V
EN
< V
UVLO(F)
IN Supply Shutdown Current (V
EN
< V
SD(F)
IN Supply Leakage Current (V
IN
=
–
14 V, V
OUT
= 0 V)
)
67
130
)
1.62
–
3.7
28.7
I
INLKG(IRPP)
ON RESISTANCE (IN – OUT)
V
IN
= 5
V
,
I
OUT
= 3 A, T
J
= 25
℃
2.7
≤
V
IN
≤
5.7
V
,
–
40
℃
≤
T
J
≤
125
℃
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
31
m
Ω
m
Ω
R
ON
50.2
V
UVLO(R)
V
UVLO(F)
V
SD(F)
EN/UVLO Rising Threshold
1.183
1.076
0.45
1.2
1.1
1.223
1.116
V
V
EN/UVLO Falling Threshold
EN/UVLO Falling Threshold for lowest shutdown current
EN/UVLO Leakage Current
0.73
V
I
ENLKG
0.1
µA
–
0.1
OUTPUT VOLTAGE CLAMP (OUT)
Overvoltage Clamp Threshold, OVCSEL = Shorted to GND
3.65
5.25
3.88
5.74
4.1
6.2
V
V
V
OVC
Overvoltage Clamp Threshold, OVCSEL = Open
Output Voltage During Clamping, OVCSEL = Shorted to
GND, I
OUT
= 10 mA
3.2
5
3.82
5.58
4.2
6.1
V
V
V
CLAMP
Output Voltage During Clamping, OVCSEL = Open, I
OUT
10 mA
=
OVERCURRENT PROTECTION (OUT)
Current Limit Threshold, R
ILM
= 6.65 k
Ω
0.425
0.85
1.8
0.5
1.0
0.575
1.15
2.2
A
A
A
A
Current Limit Threshold, R
ILM
= 3.32 k
Ω
Current Limit Threshold, R
ILM
= 1.65 k
Ω
Current Limit Threshold, R
ILM
= 750
Ω
I
LIM
2.02
4.44
3.96
4.84
Circuit Breaker Threshold, ILM Pin Open (Single point
failure)
0.1
1.1
A
A
I
FLT
Circuit Breaker Threshold, ILM Pin Short to GND (Single
point failure)
2.1
I
SCGain
I
FT
Scalable Fast Trip Threshold (I
SC
) : I
LIM
Ratio
Fixed Fast-trip Current Threshold
201
22
%
A
V
V
V
FB
V
OUT
threshold to exit Current Limit Foldback
ITIMER pin internal pull-up voltage
1.9
V
INT
2.3
1.2
2.52
2.72
2.5
OVERCURRENT FAULT TIMER (ITIMER)
I
ITIMER
ITIMER pin internal discharge current, I
OUT
> I
LIM
1.81
15
µA
k
Ω
V
R
ITIMER
Δ
V
ITIMER
ITIMER pin internal pull-up resistance
ITIMER discharge voltage
1.28
1.51
1.74
OUTPUT LOAD CURRENT MONITOR (ILM)
Copyright © 2022
T
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xas Instruments Incorporated
7
7.5 Electrical Characteristics (continued)
(
T
e
st conditions unless otherwise noted)
–
40°C
≤
T
J
≤
125°C, V
IN
= 5
V
,
O
UT = Open, V
EN/UVLO
= 2
V
,
O
VCSEL = Open,
R
ILM
= 750
Ω
, dVdT = Open, ITIMER = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
165
165
TYP
182
182
MAX
UNITS
µA/A
Analog Load Current Monitor Gain (I
MON
: I
OUT
), I
OUT
= 0.5 A
to 1 A, I
OUT
< I
LIM
200
G
IMON
Analog Load Current Monitor Gain (I
MON
: I
OUT
), I
OUT
= 1 A to
4 A, I
OUT
< I
LIM
200
µA/A
REVERSE CURRENT BLOCKING (IN – OUT)
V
FWD
5
17.4
mV
mV
V
IN
–
V
OUT
Forward regulation voltage, I
OUT
= 10 mA
V
IN
–
V
OUT
threshold for fast BFET turn off (enter reverse
current blocking)
V
REVTH
–
36.5
–
29.1
–
22.3
V
IN
–
V
OUT
threshold for fast BFET turn on (exit reverse
current blocking)
V
FWDTH
83
102.2
270
125
mV
µA
µA
OUT Leakage Current during ON state with RCB, V
OUT
V
IN
+ 1 V
=
I
OUTLKG(RCB)
I
REVLKG(OFF)
Reverse Leakage Current during unpowered condition, V
OUT
= 12 V, V
IN
= 0 V
4.8
POWER GOOD INDICATION (PG)
PG pin voltage while de-asserted, V
IN
< V
UVP(F)
, V
EN
V
SD(F)
, Weak pull-up (I
PG
= 26 µA)
<
<
0.67
0.78
1
1
V
V
V
PGD
PG pin voltage while de-asserted, V
IN
< V
UVP(F)
, V
EN
V
SD(F)
, Strong pull-up (I
PG
= 242 µA)
PG pin voltage while de-asserted, V
IN
> V
UVP(R)
PG Pin Leakage Current, PG asserted
0
V
I
PGLKG
0.9
3
µA
POWERGOOD THRESHOLD (PGTH)
V
PGTH(R)
V
PGTH(F)
I
PGTHLKG
PGTH Rising Threshold
PGTH Falling Threshold
PGTH Leakage Current
1.183
1.076
–
0.1
1.2
1.223
1.116
0.3
V
V
1.09
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
154
10
°C
°C
Thermal Shutdown Rising Threshold, T
J
↑
Thermal Shutdown Hysteresis, T
J
↓
TSD
HYS
DVDT
I
dVdt
dVdt Pin Charging Current
0.78
1.97
3.3
µA
Copyright © 2022
T
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xas Instruments Incorporated
8
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
t
OVC
t
LIM
Overvoltage clamp response time
5
µs
V
IN
> V
OVC
to V
OUT
↓
I
OUT
> 1.2 × I
LIM
& ITIMER expired to I
OUT
settling to within 5 % of I
LIM
Current limit response time
400
µs
t
SC
Scalable fast-trip response time
500
500
110
50
ns
ns
I
OUT
> 3 × I
LIM
to I
OUT
I
OUT
> I
FT
to I
OUT
↓
t
FT
Fixed fast-trip response time
↓
t
RST
t
SWRCB
Auto-Retry Interval after fault (TPS25210A)
Reverse Current Blocking recovery time
ms
µs
(V
IN
–
V
OUT
) > V
FWDTH
to V
OUT
↑
Reverse Current Blocking comparator
response time
t
RCB
1
µs
(V
OUT
–
V
IN
) > 1.3 × V
REVTH
to BFET OFF
t
PGA
t
PGD
PG Assertion de-glitch
12
12
µs
µs
PG De-assertion de-glitch
7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As C
dVdt
is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load
capacitance (C
OUT
) and Load Resistance (R
L
). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled.Typical Values are taken at T
J
= 25°C unless specifically noted otherwise. V
IN
= 2.7
V
,
R
L
= 100
Ω
, C
OUT
1 µF
=
C
dVdt
= 3300
PARAMETER
C
dVdt
= Open
12.14
C
dVdt
= 1800 pF
0.87
UNIT
pF
SR
ON
t
D,ON
t
R
Output Rising slew rate
Turn on delay
Rise time
0.5
V/ms
ms
0.09
0.17
0.27
64.44
0.6
0.97
4.33
5.31
2.51
3.11
64.44
ms
t
ON
Turn on time
ms
t
D,OFF
Turn off delay
64.44
µs
V
EN/UVLO
V
UVLO(R)
V
UVLO(F)
EN/UVLO
0
t
ON
t
D,OFF
90%
V
IN
SR
ON
OUT
10%
0V
t
R
t
D,ON
t
F
Time
图
7-1. TPS2521xx Switching Times
Copyright © 2022
T
e
xas Instruments Incorporated
9
7.8 Typical Characteristics
31
0.16
0.14
0.12
0.1
I
OUT
(A)
-40
25
125
1
3
4
30.5
30
29.5
29
0.08
0.06
0.04
0.02
0
28.5
28
0
0.5
1
1.5
2
2.5
3
3.5
4
2.7
3.2
3.7
V
IN
(V)
4.2
4.7
5
I
OUT
(A)
图
7-2. ON-Resistance vs Supply Voltage
图
7-3. Forward Voltage Drop vs Load Current
435
430
425
420
415
410
405
400
395
390
385
80
V
IN
(V)
3.3
V
IN
(V)
2.7
77.5
75
5
5
72.5
70
67.5
65
62.5
60
57.5
55
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
图
7-5. IN OFF State (UVLO) Current vs Temperature
图
7-4. IN Quiescent Current vs Temperature
5
4.5
4
2.54
T
A
(
C)
-40
2.52
25
85
105
125
2.5
3.5
3
Rising
Falling
2.48
2.46
2.44
2.42
2.4
2.5
2
1.5
1
0.5
2.7
-40
-20
0
20
40
60
80
100 120 140
3.2
3.7
V
IN
(V)
4.2
4.7
5
T
A
(
C)
图
7-7. IN Undervoltage Threshold vs Temperature
图
7-6. IN Shutdown Current vs Supply Voltage
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7.8 Typical Characteristics (continued)
1.206
1.099
1.098
1.097
1.096
1.095
1.094
1.093
V
IN
(V)
2.7
V
IN
(V)
2.7
1.205
1.204
1.203
1.202
1.201
1.2
5
5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
T
A
(
C)
图
7-8. EN/UVLO Rising Threshold vs Temperature
图
7-9. EN/UVLO Falling Threshold vs Temperature
0.8
4500
4200
3900
3600
3300
3000
2700
2400
2100
1800
1500
1200
900
V
IN
(V)
2.7
0.775
5
0.75
0.725
0.7
0.675
0.65
0.625
0.6
0.575
0.55
600
300
0.5
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
R
ILM
(k
)
图
7-10. EN/UVLO Shutdown Falling Threshold vs Temperature
图
7-11. Overcurrent Protection Threshold vs ILM Resistor
18
10
Min
Max
12
Min
Max
7.5
5
6
0
2.5
0
-2.5
-5
-6
-12
-18
-7.5
-10
0
500 1000
1500 2000 2500 3000 3500 4000 4500
I
LIM
(mA)
0.5
1
1.5
2
2.5
3
3.5
4
I
OUT
(A)
图
7-12. Overcurrent Protection Threshold Accuracy (Across
图
7-13. Analog Current Monitor Gain Accuracy
Process, Voltage, and Temperature)
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7.8 Typical Characteristics (continued)
206
24
23
22
21
20
19
18
17
V
IN
(V)
V
IN
(V)
2.7
2.7
5
205
5
204
203
202
201
200
199
198
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
图
7-14. Scalable Fast-Trip Threshold:Current Limit Threshold
图
7-15. Steady State Fixed Fast-Trip Current Threshold vs
(I
LIM
) Ratio vs Temperature
Temperature
19.8
-29
V
IN
(V)
V
IN
(V)
19.5
2.7
5
2.7
5
-29.05
19.2
-29.1
18.9
18.6
18.3
18
-29.15
-29.2
-29.25
-29.3
17.7
17.4
17.1
16.8
-29.35
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
T
A
(
C)
图
7-17. RCB – Reverse Comparator Threshold vs Temperature
图
7-16. RCB – Forward Regulation Voltage vs Temperature
107
V
IN
(V)
106.5
2.7
5
106
105.5
105
104.5
104
103.5
103
102.5
102
101.5
101
100.5
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
图
7-18. RCB – Forward Comparator Threshold vs Temperature
图
7-19. Reverse Leakage Current During OFF State
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7.8 Typical Characteristics (continued)
5.8
5.6
5.4
5.2
4
3.95
3.9
T
A
(
C)
-40
25
85
105
125
OVCSEL
3.85
3.8
GND
OPEN
5
4.8
4.6
4.4
4.2
4
3.75
3.7
3.65
3.6
3.8
-40
0
100 200 300 400 500 600 700 800 900
1000
I
OUT
(mA)
-20
0
20
40
T
A
(
C)
60
80
100 120 140
图
7-21. OVC Clamping Voltage (OVCSEL = GND) vs Load
图
7-20. OVC Threshold vs Temperature
Current
5.85
5.8
1.518
T
A
(
C)
-40
V
IN
(V)
2.7
5
1.516
25
85
105
125
1.514
5.75
5.7
1.512
1.51
5.65
5.6
1.508
1.506
1.504
1.502
5.55
5.5
5.45
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
0
100 200 300 400 500 600 700 800 900
1000
I
OUT
(mA)
图
7-23. ITIMER Discharge Differential Voltage Threshold vs
图
7-22. OVC Clamping Voltage (OVCSEL = Open) vs Load
Temperature
Current
1.83
2.7
18.5
V
IN
(V)
18
5
2.7
1.825
5
17.5
17
1.82
1.815
1.81
16.5
16
15.5
15
1.805
1.8
14.5
14
1.795
1.79
13.5
13
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
图
7-24. ITIMER Discharge Current vs Temperature
图
7-25. ITIMER Internal Pullup Resistance vs Temperature
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7.8 Typical Characteristics (continued)
2.6
2.1
2.08
2.06
2.04
2.02
2
V
IN
(V)
V
IN
(V)
2.7
2.575
2.7
5
2.55
2.525
2.5
5
2.475
2.45
2.425
2.4
1.98
1.96
1.94
2.375
2.35
2.325
-40
-20
0
20
40
T
A
(
C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
图
7-26. ITIMER Internal Pullup Voltage vs Temperature
图
7-27. DVDT Charging Current vs Temperature
0.9
0.85
0.8
I
PG
(
A)
26
242
0.75
0.7
0.65
0.6
0.55
0.5
-40
-20
0
20
40
60
80
100 120 140
T
A
(
C)
图
7-28. PGTH Threshold vs Temperature
图
7-29. PG Low Voltage Without Input Supply vs Temperature
图
7-30. Time to Thermal Shut-Down During Inrush State
图
7-31. Time to Thermal Shut-Down During Steady State
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7.8 Typical Characteristics (continued)
VIN
VIN
VOUT
EN
VOUT
EN
IIN
IIN
V
IN
= 5
V
,
C
OUT
= 220
μ
F
,
C
dVdt
= Open, V
EN/UVLO
stepped up
V
EN/UVLO
= 1.5
V
,
C
OUT
= 220
μ
F
,
C
dVdt
= Open, V
IN
ramped
to 1.4 V
up to 5 V
图
7-32. Start-Up with Enable
图
7-33. Start-Up with Supply
VIN
VIN
VOUT
PG
VOUT
EN
IIN
IIN
V
IN
= 5
V
,
C
OUT
= 690
μ
F
,
C
dVdt
= 3300 p
F
,
V
EN/UVLO
stepped
V
IN
= 5
V
,
C
OUT
= 690
μ
F
,
R
OUT
= 4
Ω
, C
dVdt
= 3300 p
F
,
V
EN/
up to 1.4 V
UVLO
stepped up to 1.4 V
图
7-34. Inrush Current with Capacitive Load
图
7-35. Inrush Current with Resistive and Capacitive Load
VIN
VIN
VOUT
VOUT
PG
PG
C
OUT
= 220
μ
F
,
P
G pulled up to 3
V
,
–
15 V hot-plugged to IN
图
7-36. Input Reverse Polarity Protection – Fast Ramp
C
OUT
= 220
μ
F
,
P
G pulled up to 3
V
,
V
IN
ramped down from 0
V to
–
15 V and then ramped up to 0 V
图
7-37. Input Reverse Polarity Protection – Slow Ramp
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7.8 Typical Characteristics (continued)
VIN
VOUT
VIN
VOUT
PG
PG
R
OVCSEL
= GND, C
OUT
= 220
μ
F
,
I
OUT
= 120 mA, V
IN
ramped
R
OVCSEL
= Open, C
OUT
= 220
μ
F
,
I
OUT
= 150 mA, V
IN
ramped
up from 3.3 V to 6 V
up from 5 V to 8 V
图
7-38. Overvoltage Clamp Response
图
7-39. Overvoltage Clamp Response
VIN
VIN
VOUT
VOUT
VITIMER
VITIMER
IIN
IIN
A.
V
IN
= 5
V
,
C
ITIMER
= 2.2 n
F
,
C
OUT
= 220
μ
F
,
R
ILM
= 750
Ω
,
I
OUT
stepped from 0 A
→
6.7 A
V
IN
= 5
V
,
C
ITIMER
= 2.2 n
F
,
C
OUT
= 220
μ
F
,
R
ILM
= 750
Ω
,
I
OUT
stepped from 2 A
→
6 A
→
2 A within 1 ms
图
7-41. Active Current Limit Response
图
7-40. Transient Overcurrent Blanking Timer Response
VIN
VIN
VOUT
VOUT
IOUT
IOUT
V
IN
= 5
V
,
R
ILM
= 750
Ω
, V
EN/UVLO
= 1.4
V
,
O
UT stepped from
Open
→
Short-circuit to GND
V
IN
= 5
V
,
R
ILM
= 750
Ω
, V
EN/UVLO
= 1.4
V
,
O
UT stepped from
Open
→
Short-circuit to GND
图
7-42. Output Short-Circuit During Steady State
图
7-43. Output Short-Circuit During Steady State (Zoomed In)
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7.8 Typical Characteristics (continued)
VIN
VOUT
PG
IIN
V
IN
= 5
V
,
C
OUT
= Open, OUT short-circuit to GND, R
ILM
= 750
Ω
, V
EN/UVLO
stepped from 0 V to 1.4 V
图
7-44. Power Up into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS2521xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN bus. When the input supply voltage (V
IN
) exceeds the
Undervoltage Protection threshold (V
UVP
), the device samples the EN/UVLO pin. A high level (> V
UVLO
) on this
pin enables the internal power path (BFET + HFET) to start conducting and allow current to flow from IN to OU
T
.
When EN/UVLO is held low (< V
UVLO
), the internal power path is turned off. In case of reverse voltages
appearing at the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (I
LIM
) is not exceeded
and overvoltage spikes are either safely clamped to the selected threshold voltage (V
OVC
). The device also
provides fast protection against severe overcurrent during short-circuit events. This keeps the system safe from
harmful levels of voltage and current. At the same time, a user adjustable overcurrent blanking timer allows the
system to pass moderate transient peaks in the load current profile without tripping the eFuse. This ensures a
robust protection solution against real faults which is also immune to transients, thereby ensuring maximum
system uptime.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is
linearly regulated to maintain a small constant forward drop (V
FWD
) in forward conduction mode and turned off
completely to block reverse current if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (T
J
) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
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8.3 Feature Description
The TPS2521xx eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Input Reverse Polarity Protection
The TPS2521xx device is internally protected against steady state negative voltages applied at the input supply
pin. The device blocks the negative voltage from appearing at the output, thereby protecting the load circuits.
There
’
s no reverse current flowing from output to the input in this condition. The lowest negative voltage the
device can handle at the input is limited to
–
15 V or VOUT
–
21
V
,
w
hichever is higher. TI also recommends
that all signal pins (for example, EN/UVLO, PGTH) which are connected to input supply should have a
sufficiently large pullup resistor to limit the current flowing out of these pins during reverse polarity conditions.
8.3.2 Undervoltage Lockout (UVLO and UVP)
The TPS2521x implements Undervoltage Protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The Undervoltage Protection has a default lockout threshold of V
UVP
which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage Protection threshold
used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R
1
EN/UVLO
R
2
GND
图
8-1. Adjustable Undervoltage Protection
V
UVLO(R) ×
(R1 + R2 )
V
IN(UV)
=
(1)
8.3.3 Overvoltage Clamp (OVC)
The TPS2521xx implements a voltage clamp on the output to protect the system in the event of input
overvoltage. When the device detects the input has exceeded the Overvoltage Clamp Threshold (V
OVC
), it
quickly responds within t
OVC
and stops the output from rising further and then regulates the HFET linearly to
clamp the output voltage below V
CLAMP
as long as an overvoltage condition is present on the input.
If the part stays in clamping state for an extended period of time, there is higher power dissipation inside the part
which can eventually lead to thermal shut-down (TSD). After the part shuts down due to TSD fault, it either stays
latched off (TPS2521xL variant) or restarts automatically after a fixed delay (TPS2521xA variant). See
Overtemperature Protection (OTP)
for more details on device response to overtemperature.
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Input Overvoltage Event
Input Overvoltage Removed
V
OVC
IN
Thermal
Shutdown
Retry Timer Expired
(1)
0
t
OVC
t
RST
V
CLAMP
OUT
PG
T
J
dVdt Limited Start-up
t
PGA
0
t
PGD
V
PG
0
TSD
TSD
HYS
Time
(1)
Applicable only for TPS25210A (Auto-retry variant)
图
8-2. TPS2521xA Overvoltage Response (Auto-Retry)
There are two available overvoltage clamp threshold options which can be configured using the OVCSEL pin.
表
8-1. TPS2521xx Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Overvoltage Clamp Threshold
Shorted to GND
Open
3.8 V
5.7 V
8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
TPS2521xx incorporates four levels of protection against overcurrent:
1. Adjustable
slew rate (dVdt) for inrush current control
2. Adjustable
threshold (I
LIM
) for overcurrent protection during start-up or steady-state
3. Adjustable
threshold (I
SC
) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed
threshold (I
FT
) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate.
方程式
2
can be used to find
the slew rate (SR) required to limit the inrush current (I
INRUSH
) for a given load capacitance (C
OUT
):
I
INRUSH
(mA)
SR (V/ms) =
C
OUT
(µF)
(2)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
2000
C
dVdt
(pF) =
SR (V/ms)
(3)
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The fastest output slew rate is achieved by leaving the dVdt pin open.
备注
For C
dVdt
> 10 n
F
, Ti recommends to add a 100-
Ω
resistor in series with the capacitor on the dVdt pin.
8.3.4.2 Active Current Limiting
The TPS2521xx responds to output overcurrent conditions by actively limiting the current after a user adjustable
transient fault blanking interval. When the load current exceeds the set overcurrent threshold (I
LIM
) set by the
ILM pin resistor (R
ILM
), but stays lower than the short-circuit threshold (2 × I
LIM
), the device starts discharging the
ITIMER pin capacitor using an internal 1.8-
μ
A pulldown current. If the load current drops below the overcurrent
threshold before the ITIMER capacitor (C
ITIMER
) discharges by
Δ
V
ITIMER
, the ITIMER is reset by pulling it up to
V
INT
internally and the current limit action is not engaged. This allows short load transient pulses to pass through
the device without getting current limited. If the overcurrent condition persists, the C
ITIMER
continues to discharge
and after it discharges by
Δ
V
ITIMER
, the current limit starts regulating the HFET to actively limit the current to the
set overcurrent threshold (I
LIM
). At the same time, the C
ITIMER
is charged up to V
INT
again so that it is at its
default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every
3334
: ;
R
ILM
À
=
: ;
A
I
LIM
(4)
备注
1. Leaving
the ILM pin open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The
current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < V
OUT
< V
FB
) is lower than the steady state current limit threshold (I
LIM
).
3. Shorting
the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There is a minimum current (I
FLT
) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The C
ITIMER
value needed to set the desired transient overcurrent blanking interval can be
¿
V
ITIMER
(V)
×
C
ITIMER
(nF)
t
ITIMER
(ms) =
I
ITIMER
(µA)
(5)
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Overload Removed
Persistent Output Overload
Transient Overcurrent
Persistent Output Overload
ITIMER expired
ITIMER expired
t
LIM
Thermal shutdown
2 × I
LIM
t
LIM
I
OUT
I
LIM
Current limiting
operation
Current limiting
operation
0
t
ITIMER
t
ITIMER
V
INT
V
ITIMER
ITIMER
0
V
IN
OUT
0
1.2 V
0
PGTH
t
PGD
t
PGD
t
PGA
V
PG
PG
0
TSD
TSD
HYS
T
J
T
J
Time
图
8-3. TPS2521xx Active Current Limit Response
备注
1. Leave
the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting
the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Active
current limiting based on R
ILM
is active during start-up. In case the start-up current exceeds
I
LIM
, the device regulates the current to the set limit. However, during start-up the current limit is
engaged without waiting for the ITIMER delay.
4. During
overvoltage clamp condition, if an overcurrent event occurs, the current limit is engaged
without waiting for the ITIMER delay.
5. Increasing
the C
ITIMER
value extends the overcurrent blanking interval, but it also extends the time
needed for the C
ITIMER
to recharge up to V
INT
. If the next overcurrent event occurs before the
C
ITIMER
is recharged fully, it takes lesser time to discharge to the ITIMER expiry threshold, thereby
providing a shorter blanking interval than intended.
During active current limit, the output voltage drops resulting in increased device power dissipation across the
HFE
T
.
I
f the device internal temperature (T
J
) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. After the part shuts down due to TSD fault, it either stays latched off (TPS252x1L variant) or restarts
automatically after a fixed delay (TPS2521xA variant). See
Overtemperature Protection (OTP)
for more details
on device response to overtemperature.
8.3.4.3 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The
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internal fast-trip comparator employs a scalable threshold (I
SC
) which is equal to 2 × I
LIM
. This enables the user
to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low current
systems. The device also employs a fixed fast-trip threshold (I
FT
) to protect fast protection against hard short-
circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user
adjustable scalable fast-trip threshold. After the current exceeds I
SC
or I
FT
, the HFET is turned off completely
within t
FT
. Thereafter, the devices tries to turn the HFET back ON after a short de-glitch interval (30
μ
s) in a
current limited manner instead of a dVdt limited manner. This ensures that the HFET has a faster recovery after
a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the
device stays in current limit causing the junction temperature to rise and eventually enter thermal shutdown. See
Overtemperature Protection (OTP)
section for details on the device response to overtemperature.
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed
(1)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed
(1)
V
IN
IN
0
t
FT
t
SC
t
SC
I
FT
2 × I
LIM
I
OUT
I
LIM
0
V
IN
OUT
PG
T
J
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
t
PGD
t
PGD
t
PGD
V
PG
0
t
RST
t
RST
TSD
TSD
HYS
(1)
Applicable only for TPS25210A variant
Time
图
8-4. TPS2521xx Short-Circuit Response
8.3.5 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the ILM pin which is proportional to the current through the FE
T
.
T
he user can sense the voltage (V
ILM
across the R
ILM
to get a measure of the output load current.
)
V
ILM
(µV)
I
OUT
(A) =
R
ILM
:
À
;
×
G
IMON
(µA/A)
(6)
The waveform below shows the ILM signal response to a load step at the output.
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VIN
VOUT
VILM
IIN
V
IN
= 5
V
,
C
OUT
= 220
μ
F
,
R
ILM
= 750
Ω
, I
OUT
stepped up from 0 A to 4 A
图
8-5. Analog Load Current Monitor Response
备注
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.6 Reverse Current Protection
The device functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The
device has integrated back-to-back MOSFE
T
s
c
onnected in a common drain configuration. The voltage drop
between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted
as needed to regulate the forward voltage drop at V
FWD
. This closed loop regulation scheme (linear ORing
control) enables graceful turn off of the MOSFET during a reverse current event and ensures there is no DC
reverse current flow.
The device also uses a conventional comparator (V
REVTH
) based reverse blocking mechanism to provide fast
response (t
RCB
) to transient reverse currents. After the device enters reverse current blocking condition, it waits
for the (V
IN
–
V
OUT
) forward drop to exceed the V
FWDTH
before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (t
SWRCB
). This ensures
minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap
(FRS).
V
FWD
IN
OUT
OUT
IN
BFET operating state
BFET turned OFF
BFET regulation
BFET fast disable
Linear ORing loop response
BFET full conduction
BFET fast enable
(RCB exit)
RCB fast comparator response
(RCB entry)
V
IN
– V
OUT
I
IN
0 V
0 A
V
FWD
V
REVTH
Reverse
V
FWTH
Forward
图
8-6. Reverse Current Blocking Response
The waveforms below illustrate the reverse current blocking performance in various scenarios.
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During fast voltage step at output (for examp-le. hot-plug), the fast comparator based reverse blocking
mechanism ensures minimum jump/glitch on the input rail.
VIN
VBUS
IIN
图
8-7. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there is no DC
current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
VIN
VBUS
IIN
图
8-8. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (capacitor bank or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
VIN
VOUT
PG
图
8-9. Reverse Current Blocking Performance During Input Supply Failure
8.3.7 Overtemperature Protection (OTP)
The device monitors the internal die temperature (T
J
) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device does
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD
–
TSD
HYS
).
When the TPS2521xL (latch-off variant) detects thermal overload, it shuts down and remains latched-off until the
device is power cycled or re-enabled. When the TPS2521xA (auto-retry variant) detects thermal overload, it
remains off until it has cooled down by TSD
HYS
. Thereafter, the device remains off for an additional delay of t
RST
after which it automatically retries to turn on if it is still enabled.
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表
8-2. Thermal Shutdown
Device
Enter TSD
Exit TSD
T
J
< TSD
–
TSD
HYS
V
IN
cycled to 0 V and then above V
UVP(R)
OR
TPS2521xL (Latch-Off)
TPS2521xA (Auto-Retry)
8.3.8 Fault Response
T
J
≥
TSD
EN/UVLO toggled below V
SD(F)
T
J
< TSD
–
TSD
HYS
V
IN
cycled to 0 V and then above V
UVP(R)
OR
T
J
≥
TSD
EN/UVLO toggled below V
SD(F)
OR t
RST
timer
expired
The following table summarizes the device response to various fault conditions.
表
8-3. Fault Summary
Event
Protection Response
Fault Latched Internally
Overtemperature
Shutdown
Shutdown
Shutdown
Y
N
N
N
N
N
N
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Input Overvoltage
Voltage Clamp
Transient Overcurrent (I
LIM
< I
OUT
< 2 × I
LIM
)
None
Persistent Overcurrent
Current Limit
Output Short-Circuit to GND
Fast-trip followed by Current Limit
ILM Pin Open
(During Steady State)
Shutdown
N
ILM Pin Shorted to GND
Shutdown
Y
N
Reverse Current Blocking
Reverse Current ((V
OUT
–
V
IN
) > V
REVTH
)
Faults which are latched internally can be cleared either by power cycling the part (pulling V
IN
to 0 V) or by
pulling the EN/UVLO pin voltage below V
SD
. This also resets the t
RST
timer for the TPS2521xA (auto-retry)
variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is
true for both TPS2521xL (latch-off) and TPS2521xA (auto-retry) variants.
For TPS2521xA (auto-retry) variant, on expiry of the t
RST
timer after a fault, the device restarts automatically.
8.3.9 Power Good Indication (PG)
The TPS2521xx provides an active high digital output (PG) which serves as a power good indication signal and
is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an
open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on
in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above V
PGTH(R)
, the PG is asserted after a de-glitch time
(t
PGA
).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below V
PGTH(F)
, or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is t
PGD
.
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Overload Event
Overcurrent blanking timer expired
Overload Removed
Device Enabled
V
UVLO(R)
EN/UVLO
0
V
IN
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
Active Current
limiting
V
IN
OUT
0
V
PGTH(R)
V
PGTH(F)
PGTH
PG
0
V
PG
t
PGA
t
PGD
t
PGA
0
V
IN
dVdt
0
V
OUT
+ 2.8V
V
HGate
0
t
ITIMER
I
LIM
I
INRUSH
I
OUT
0
Time
图
8-10. TPS2521xx PG Timing Diagram
表
8-4. TPS2521xx PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Shutdown
L
L
Shutdown
Clamp
H (If PGTH pin voltage >
V
PGTH(R)
L (If PGTH pin voltage <
V
PGTH(F)
)
t
PGA
t
PGD
Overvoltage (OVC)
)
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表
8-4. TPS2521xx PG Indication Summary (continued)
Event
Protection Response
PG Pin
PG Delay
H (If PGTH pin voltage >
V
PGTH(R)
L (If PGTH pin voltage <
V
PGTH(F)
)
t
PGA
t
PGD
Steady State
NA
NA
)
H (If PGTH pin voltage >
V
PGTH(R)
L (If PGTH pin voltage <
V
PGTH(F)
)
t
PGA
t
PGD
Transient Overcurrent
Persistent Overload
)
H (If PGTH pin voltage >
V
PGTH(R)
L (If PGTH pin voltage <
V
PGTH(F)
)
t
PGA
t
PGD
Current Limiting
)
H (If PGTH pin voltage >
Fast trip followed by Current Limit
V
PGTH(R)
L (If PGTH < V
PGTH(F)
t
PGA
t
PGD
Output Short-Circuit to GND
ILM Pin Open
)
)
L (If PGTH pin voltage <
V
PGTH(F)
Shutdown
t
PGD
t
PGD
t
PGD
)
ILM Pin Shorted to GND
Shutdown
L (If PGTH < V
PGTH(F)
)
Reverse Current ((V
OUT
–
V
IN
) >
Reverse Current Blocking
Shutdown
L
L
V
REVTH
)
Overtemperature
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown
in this condition to drive this pin all the way down to 0
V
.
I
f the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.4 Device Functional Modes
表
8-5. TPS2521xx Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Overvoltage Clamp Threshold
Shorted to GND
Open
3.8 V
5.7 V
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9 Application and Implementation
备注
以下应用部分中的信息不属
于
TI
器件规格的范围
，
TI
不担保其准确性和完整性。
TI
的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计
，
以确保系统功能。
9.1 Application Information
The TPS2521xx is a 2.7-V to 5.7-
V
, 4-A eFuse that is typically used for power rail protection applications. The
device can withstand maximum input voltage of 28 V with adjustable undervoltage lockout and fast overvoltage
clamp protection. The device provides ability to control inrush current and protection against input reverse
polarity as well as reverse current conditions. The device can be used in a variety of systems such as adapter
input protection, storage
–
eSSD/cSSD, e-meters, smart speakers, headphones, USB power accessories. The
design procedure explained in the subsequent sections can be used to select the supporting component values
based on the application requirement. Additionally, a spreadsheet design tool,
TPS2521x Design Calculator
, is
available in the web product folder.
9.2 Single Device, Self-Controlled
V
IN
= 2.7 to 5.7 V
V
O
U
T
IN
OUT
C
O
U
T
V
L
O
G
I
C
PGTH
EN/U
V
L
O
TPS2
5
2
10x
OVCS
E
L
PG
I
T
I
MER dVdt
ILM
GND
图
9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVCSEL can also be driven from the host GPIO to control/
configure the device operation.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
备注
TI recommends to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
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Either V
IN
or V
OUT
can be used to drive the PGTH resistor divider depending on which supply needs to be
monitored for power good indication.
9.3 Typical Application
End equipments like PC, notebooks, docking stations, monitors, and so on have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source + Sink). TPS2521xx can be used independently or in
conjunction with LM73100 to handle the power path protection requirements of USB PD ports as shown in
图
9-2
below.
TPS2521xx provides overcurrent and short-circuit protection in the source path, while blocking any reverse
current from the port to the internal source power rail. The fast recovery (t
SWRCB
) from reverse current blocking
ensures minimum supply droop during Fast Role Swap (FRS) events.
The LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink
rail to the port.
The linear ORing mechanism in TPS2521xx and LM73100 ensures that there is no reverse current flowing from
one power source to the other during fast or slow ramp of either supply.
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V
OUT
= 5 V to 20 V
IN
OUT
OVLO
IMON
LM73100
PGTH
dVdt
PG
EN/UVLO
GND
V
BUS
= 5 V to 20V
C
DVDT
PD Controller
EN/UVLO
PG
IN
OUT
V
IN
= 5 V
TPS25210L
PGTH
OVCSEL
ITIMER dVdt
ILM
GND
R
ILM
C
DVDT
C
ITIMER
图
9-2. USB PD Port Protection
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9.3.1 Application
USB DATA
V
IN
= 5V
IN
OUT
V
BUS
C
O
U
T
R3
R1
100 k
ꢀ
470 k
ꢀ
10
u
F
PGTH
EN/U
V
L
O
TPS2
5
2
10L
R4
3.3V
R2
36.5 k
ꢀ
205 k
ꢀ
OVCS
E
L
47 k
ꢀ
PG
I
T
I
MER
dV
d
t
GND
ILM
C
DV
D
T
1 nF
R
I
L
M
C
I
T
I
MER
2.2 nF
953
ꢀ
图
9-3. TPS2521xx Application Circuit for USB PD Source Path Protection
9.3.2 Design Requirements
表
9-1. Design Parameters
PARAMETER
VALUE
5 V
Input supply voltage (V
IN
)
Undervoltage threshold (V
IN(UV)
)
4 V
Overvoltage clamp (V
IN(OVC)
)
5.7 V
4.5 V
10
μ
F
2 V/ms
3 A
Output Power Good threshold (V
PG
)
Output capacitance (C
OUT
Output Slew Rate (SR)
Max continuous current
)
Overcurrent response
Current limit
3.5 A
Current limit threshold (I
LIM
)
Load transient blanking interval (t
ITIMER
)
2 ms
Fault response
Latch-off
9.3.3 Detailed Design Procedure
9.3.3.1 Device Selection
Because the application requires current limit response to overcurrent with latch-off response after a fault, the
9.3.3.2 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage threshold is set using the resistors R1, R2 and can be calculated using
方程
式
7
:
V
UVLO(R) ×
(R1 + R2 )
V
IN(UV)
=
(7)
V
UVLO(R)
is the UVLO rising threshold. Because R1 and R2 leak the current from input supply V
IN
, these resistors
must be selected based on the acceptable leakage current from input power supply V
IN
. The current drawn by
R1 and R2 from the power supply is IR12 = V
IN
/ (R1 + R2 ). However, leakage currents due to external active
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components connected to the resistor string can add error to these calculations. So, the resistor string current,
IR12 must be chosen to be 20 times greater than the leakage current expected on the EN/UVLO pin.
From the device electrical specifications, the EN/UVLO leakage current is 0.1
μ
A (maximum), and V
UVLO(R)
=
1.2
V
.
F
rom design requirements,V
IN(UV)
= 4
V
. To
s
olve the equation, first choose the value of R1 = 470 k
Ω
and
use the above equation to solve for R2 = 201.4 k
Ω
.
Using the closest standard 1% resistor values, we get R1 = 470 k
Ω
and R2 = 205 k
Ω
.
9.3.3.3 Setting Output Voltage Rise Time (t
R
)
The slew rate (SR) needed to meet the target specification is:
SR (V/ms) = 2 V/ms
(8)
(9)
The C
dVdt
needed to achieve this slew rate can be calculated as:
2000
2000
2
:
;
C
dVdt
pF =
=
;
= 1000 pF
:
SR V/ms
Choose the nearest standard capacitor value as 1 n
F
.
For this slew rate, the inrush current can be calculated as:
:
;
:
I
INRUSH
mA =
SR (V/ms)
×
C
OUT
µF =
2
×
10 = 20 mA
;
(10)
(11)
The average power dissipation inside the part during inrush can be calculated as:
: ;
A
: ;
V
I
INRUSH
×
V
IN
0.02
×
5
: ;
PD
INRUSH
W =
=
= 0.05 W
The power dissipation is below the allowed limit for a successful start-up without hitting thermal shut-down within
图
9-4. Thermal Shut-Down Plot During Inrush
9.3.3.4 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R3 and R4 connected to the PGTH pin
whose values can be calculated as:
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V
PGTH(R) ×
(R3 + R4)
V
PG
=
R4
(12)
Because R3 and R4 leak the current from the output rail V
OUT
, these resistors must be selected to minimize the
leakage current. The current drawn by R3and R4 from the power supply is IR34 = V
OUT
/ (R3 + R4). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR34 must be chosen to be 20 times greater than the PGTH leakage
current expected.
From the device electrical specifications, PGTH leakage current is 1
μ
A (maximum), V
PGTH(R)
= 1.2 V and from
design requirements, V
PG
= 4.5
V
. To
s
olve the equation, first choose the value of R3 = 100 k
Ω
and calculate R4
= 36.4 k
Ω
. Choose nearest 1% standard resistor value as R4 = 36.5 k
Ω
.
9.3.3.5 Setting Overcurrent Threshold (I
LIM
)
The overcurrent protection (Current limit) threshold can be set using the R
ILM
resistor whose value can be
calculated as:
3334
3334
3.5 A
: ;
R
ILM
À
=
=
= 952.57
À
: ;
A
I
LIM
(13)
Choose nearest 1% standard resistor value as 953
Ω
.
9.3.3.6 Setting Overcurrent Blanking Interval (t
ITIMER
)
The overcurrent blanking timer interval can be set using the C
ITIMER
capacitor whose value can be calculated as:
t
ITIMER
(ms) ×
I
ITIMER
(µA)
V
ITIMER
(V)
2 x 1.8
1.5
C
ITIMER
(nF) =
=
= 2.4 nF
(14)
Choose nearest standard capacitor value as 2.2 n
F
.
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9.3.4 Application Curves
VIN
VIN
VBUS
VBUS
IIN
IIN
图
9-5. VBUS 20-V Hot-Plug
图
9-6. VBUS 20-V Slow Ramp Up
VIN
VBUS
IIN
V
IN
= 5
V
,
C
OUT
= 10
μ
F
,
R
OUT
= 8
Ω
, V
BUS
= 20 V initially and then disconnected
图
9-7. Fast Role Swap
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10 Power Supply Recommendations
The TPS2521xx devices are designed for a supply voltage range of 2.7 V
≤
V
IN
≤
5.7
V
.
T
I recommends an
input ceramic bypass capacitor higher than 0.1
μ
F if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
The lowest negative voltage the device can handle at the input is limited to
–
15 V or V
OUT
–
21 V, whichever is
higher. Any low voltage signals (for example. EN/UVLO, PGTH) derived from the input supply must have a
sufficiently large pullup resistor to limit the current through those pins to < 10
μ
A during reverse polarity
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
Minimize lead length and inductance into and out of the device.
•
Use a large PCB GND plane.
•
Use a Schottky diode across the output to absorb negative spikes.
•
Connect a low ESR capacitor of value greater than 1
μ
F at the OUT pin very close to the device.
•
Use a low-value ceramic capacitor C
IN
= 1
μ
F to absorb the energy and dampen the transients. The
capacitor voltage rating must be at least twice the input supply voltage to be able to withstand the positive
voltage excursion during inductive ringing.
L
IN
V
SPIKE (Absolute)
= V
+ I
LOAD
×
IN
C
IN
(15)
where
•
V
IN
is the nominal supply voltage.
•
I
LOAD
is the load current.
•
L
IN
equals the effective inductance seen looking into the source.
•
C
IN
is the capacitance present at the input.
Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the
transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy
dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple
to the internal control circuits and cause unexpected behavior.
备注
If there is a likelihood of input reverse polarity in the system, TI recommends to use a bi-directional
TVS, or a reverse blocking diode in series with the TVS.
For applications such as USB-C ports where a powered cable can be plugged to the output of the device, there
can be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the device. TI
recommends to add a TVS diode from OUT to IN to clamp the voltage to a safe level.
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D3
D4
V
O
U
T
V
IN
= 2.7 to 5.7 V
IN
OUT
R1
C
O
U
T
D2
PGTH
EN/U
V
L
O
V
L
O
G
I
C
TPS2
5
2
10x
R2
C
IN
D1
OVCS
E
L
PG
I
T
I
MER
dV
d
t
GND
ILM
R
I
L
M
C
I
T
I
MER
C
DV
D
T
图
10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
Obtain repeatable and similar short-circuit testing results is difficult. The following contribute to variation in
results:
•
Source bypassing
•
Input leads
•
Circuit layout
•
Component selection
•
Output shorting method
•
Relative location of the short
•
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
Copyright © 2022
T
e
xas Instruments Incorporated
38
11 Layout
11.1 Layout Guidelines
•
For all applications, TI recommends a ceramic decoupling capacitor of 0.1
μ
F or greater between the IN
terminal and GND terminal.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
•
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. It’s recommended to have a separate
ground plane island for the eFuse. This plane doesn’t carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane should be connected to the
system power ground plane using a star connection.
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible. Adding thermal vias on the under the device further helps to minimize the voltage
gradient across the IN and OUT pads and distribute current uniformly through the device, which improves the
on-resistance and current sense accuracy.
•
Locate the following support components close to their connection pins:
–
R
ILM
–
C
dVdT
–
C
ITIMER
–
Resistors for the EN/UVLO, OVCSEL and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the R
ILM
, C
ITIMER
and C
dVdt
components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. TI recommends to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the
PCB routing of this node must be kept away from any noisy (switching) signals.
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1
μ
F or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND
terminal of the IC.
Copyright © 2022
T
e
xas Instruments Incorporated
39
11.2 Layout Example
Bottom Signal/GND layer
Top Power layer
6
5
OUT
IN
OUT
IN
图
11-1. Layout Example
Copyright © 2022
T
e
xas Instruments Incorporated
40
12 Device and Documentation Support
TI offers an extensive line of development tools.
T
o
ols and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
12.2
接收文档更新通知
改摘要。有关更改的详细信息
，
请查看任何已修订文档中包含的修订历史记录。
12.3
支持资源
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成
TI
技术规范
，
并且不一定反映
TI
的观点
；
请参阅
12.4 Trademarks
TI E2E
™
is a trademark of
T
e
xas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD.
T
e
xas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6
术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022
T
e
xas Instruments Incorporated
41
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022
T
e
xas Instruments Incorporated
42
PACKAGE OPTION ADDENDUM
7-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25210ARPWR
TPS25210LRPWR
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RPW
RPW
10
10
3000 RoHS
& Green
3000 RoHS
& Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
2AJH
2AIH
Call TI | NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
7-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
TPS25210ARPWR
TPS25210LRPWR
VQFN-
HR
RPW
RPW
10
10
3000
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
7-Dec-2021
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25210ARPWR
TPS25210LRPWR
VQFN-HR
VQFN-HR
RPW
RPW
10
10
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This
drawing is subject to change without notice.
EXAMPLE BOARD LAYOUT
VQFN-HR – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
4. Solder
mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
VQFN-HR – 1 mm max height
PLASTIC QUAD FLATPACK – NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
重要声明和免责声明
TI“
按原样
”
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用
TI
产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：
(1)
针对您的应用选择合适的
TI
产品，
(2)
设计、验
证并测试您的应用，
(3)
确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。
TI
授权您仅可将这些资源用于研发本资源所述的
TI
产品的应用。严禁对这些资源进行其他复制或展示。
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TI
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TI
对此概不负责。
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反对并拒绝您可能提出的任何其他或不同的条款。
IMPORTANT NOTICE
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T
e
xas Instruments, Post Office Box 655303, Dallas,
T
e
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Copyright © 202
2
，德州仪器
(TI)
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