tps2592ba

ZHCSD51

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ECEMBER 2014

9.4 Device

Functional Modes………………………………….

10 Application

and Implementation

……………………

10.1 Application

Information……………………………………

10.2 Typical

Applications ………………………………………

特性

………………………………………………………………..

应用

………………………………………………………………..

说明

………………………………………………………………..

应用电路原理图

………………………………………………..

修订历史记录

…………………………………………………..

Device Comparison Table

……………………………….

Pin Configuration and Function

…………………….

Specifications

…………………………………………………

8.1 Absolute

Maximum Ratings ……………………………….

8.2 ESD

Ratings ……………………………………………………

8.3 Recommended

Operating Conditions………………….

8.4 Thermal

Information ………………………………………….

8.5 Electrical

Characteristics……………………………………

8.6 Timing

Requirements ………………………………………..

8.7 Typical

Characteristic

………………………………………

Detailed Description

……………………………………..

9.1 Overview

………………………………………………………..

9.2 Functional

Block Diagram …………………………………

9.3 Feature

Description………………………………………….

10.3 Maximum

Device Power Dissipation

Considerations …………………………………………………

11 Power

Supply Recommendations

…………………

11.1 Transient

Protectio

………………………………………

11.2 Output

Short-Circuit Measurements …………………

12 Layout

………………………………………………………….

12.1 Layout

Guidelines ………………………………………….

12.2 Layout

Example …………………………………………….

器件和文档支持

……………………………………………..

13.1

器件支持

………………………………………………………

13.2

相关链接

……………………………………………………….

13.3

商

标

……………………………………………………………..

13.4

静电放电警告

…………………………………………………

13.5

术语表

………………………………………………………….

机械封装和可订购信息

……………………………………

修订历史记录

日期

修订版本

注释

2014

年

月

最初发布版本

ZHCSD51

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ECEMBER 2014

6 Device

Comparison Table

PART NUMBER

TPS2592BA

OV CLAMP

6.1 V

FAULT RESPONSE

Auto Retry

STATUS

Active

4.3 V

TPS2592BL

6.1 V

Latched

Active

7 Pin

Configuration and Functions

10-Pin VSON

DRC Package

(Top View)

dV/dT

ILIM

EN/UVLO

BFET

OUT

GND

VIN

OUT

Pin Functions

NUMBER

DESCRIPTION

NAME

BFET

Connect this pin to the gate of a blocking NFET. See the

Feature Description

dV/dT

Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.

EN/UVLO

This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal

pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.

As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.

GND

ILIM

OUT

VIN

PowerPAD™

GND

6-8

3-5

A resistor from this pin to GND will set the overload and short circuit limit.

Output of the device

Input supply voltage

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ECEMBER 2014

Maximum Device Power Dissipation Considerations

8 Specifications

8.1 Absolute

Maximum Ratings

over operating temperature range (unless otherwise noted)

(1) (2)

MIN

MAX

UNIT

VIN

Supply voltage range

(1)

–0.3

VIN (10 ms Transient)

OUT

Output voltage

–0.3

VIN + 0.3

OUT (Transient < 1 µs)

-1.2

ILIM

–0.3

EN/UVLO

Voltage

dV/dT

BFET

Continuous power dissipation

= –40°C to +85°C

See the Thermal Information

Maximum power dissipation

(3)

= (V

-V

OUT

)*I

LIMIT

°C

= 0°C to +85°C

Storage temperature range, T

stg

-65

150

(1) Stresses

beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All

voltage values, except differential voltages, are with respect to network ground terminal.

(3) Refer

to detailed explanation in the application section

8.2 ESD

Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

Charged device model (CDM), per JEDEC specification JESD22-C101

(2)

(ESD)

Electrostatic discharge

(1) JEDEC

document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC

document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended

Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP

MAX UNIT

VIN

4.5

5.5

BFET

VIN+6

Input voltage range

dV/dT, EN/UVLO

ILIM

OUT

3.3

Continuous output current

Resistance

162

ILIM

OUT

dV/dT

0.1

100

µF

°C

1000

125

External capacitance

Operating junction temperature range, T

Operating Ambient temperature range, T

–40

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8.4 Thermal

Information

(1)

over operating free-air temperature range (unless otherwise noted)

TPS2592Bx

UNIT

THERMAL METRIC

DRC (10) PINS

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

45.9

JCtop

21.2

°C/W

1.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

21.4

5.9

JCbot

(1) For

more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,

SPRA953

8.5 Electrical

Characteristics

–40°C

≤

125°C, VIN = 5 V, V

EN /UVLO

= 2 V, R

ILIM

= 100 k

, C

dVdT

= OPEN. All voltages referenced to GND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

4.15

0.4

TYP

MAX

UNIT

VIN (INPUT SUPPLY)

UVR

UVLO threshold, rising

UVLO hysteresis

(1)

4.3

5.4%

0.62

0.1

4.45

UVhyst

Enabled: EN/UVLO = 2 V

0.80

0.25

Supply current

OFF

EN/UVLO = 0 V

VIN > 6.75 V, I

OUT

= 10 mA,

–40

℃

≤

℃

5.5

6.1

6.75

OVC

Over-voltage clamp

VIN > 6.75 V, I

OUT

= 10 mA,

–40

℃

≤

125

℃

5.25

EN/UVLO (ENABLE/UVLO INPUT)

ENR

ENF

EN Threshold voltage, rising

1.37

1.32

–100

1.4

1.35

1.44

1.39

100

EN Threshold voltage, falling

EN Input leakage current

0 V

≤

5 V

dV/dT (OUTPUT RAMP CONTROL)

dVdT

dV/dT Charging current

(1)

dVdT

= 0 V

220

dVdT_disch

dVdTmax

GAIN

dVdT

dV/dT Discharging resistance

dV/dT Max capacitor voltage

(1)

dV/dT to OUT gain

(1)

EN/UVLO = 0 V, I

dVdT

= 10 mA sinking

100

5.5

dVdT

4.85

V/V

ILIM (CURRENT LIMIT PROGRAMMING)

ILIM

ILIM Bias current

(1)

2.10

3.75

5.2

µA

ILIM

= 45.3 k

, V

VIN-OUT

= 1 V

ILIM

= 100 k

, V

VIN-OUT

= 1 V

ILIM

= 150 k

, V

VIN-OUT

= 1 V

1.79

3.46

4.4

2.42

4.03

Overload current limit

(2)

ILIM

= 0

, Shorted Resistor Current Limit (Single Point

OL-R-Short

OL-R-Open

0.7

Failure Test: UL60950)

(1)

ILIM

= OPEN, Open Resistor Current Limit (Single Point

Failure Test: UL60950)

(1)

0.55

ILIM

= 45.3 k

, V

VIN-OUT

= 5 V

ILIM

= 100 k

, V

VIN-OUT

= 5 V

ILIM

= 150 k

, V

VIN-OUT

= 5 V

1.72

3.14

4.12

2.05

3.56

4.86

2.38

3.98

5.60

SCL

Short-circuit current limit

(2)

Fast-Trip comparator level w.r.t.

overload current limit

(1)

RATIO

FASTRIP

OpenILIM

FASTRIP

: I

160%

3.1

ILIM Open resistor detect

threshold

(1)

ILIM

Rising, R

ILIM

= OPEN

(1) These

parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s

product warranty.

(2) Pulsed

testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.

ZHCSD51

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Electrical Characteristics (continued)

–40°C

≤

125°C, VIN = 5 V, V

EN /UVLO

= 2 V, R

ILIM

= 100 k

, C

dVdT

= OPEN. All voltages referenced to GND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUT (PASS FET OUTPUT)

= 25°C

DS(on)

FET ON resistance

= 125°C

OUT-OFF-LKG

OUT-OFF-SINK

EN/UVLO

= 0 V, V

OUT

= 0 V (Sourcing)

EN/UVLO

= 0V, V

OUT

= 300 mV (Sinking)

–5

OUT Bias current in off state

µA

BFET (BLOCKING FET GATE DRIVER)

BFET

BFET Charging current

(1)

BFET

= V

OUT

µA

VIN

6.4

BFETmax

BFET Clamp voltage

(1)

BFET Discharging resistance to

GND

BFETdisch

EN/UVLO

= 0 V, I

BFET

= 100 mA

TSD (THERMAL SHUT DOWN)

SHDN

TSD Threshold, rising

(1)

TSD Hysteresis

(1)

160

°C

SHDNhyst

TPS2592BL

TPS2592BA

LATCHED

AUTO-RETRY

Thermal fault: latched or autoretry

8.6 Timing

Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

220

0.4

MAX UNIT

EN/UVLO

→

H to I

VIN

= 100 mA, 1-A resistive load at

Turn-on delay

(1)

Turn Off delay

(2)

µs

OUT

OFFdly

↓

to BFET

↓

, C

BFET

= 0

dV/dT (OUTPUT RAMP CONTROL)

EN/UVLO

→

H to OUT = 4.9 V, C

dVdT

= 0

0.28

0.4

0.52

dVdT

Output ramp time

EN/UVLO

→

H to OUT = 4.9 V,

dVdT

= 1 nF

(2)

ILIM (CURRENT LIMIT PROGRAMMING)

FastOffDly

Fast-Trip comparator delay

(2)

BFET (BLOCKING FET GATE DRIVER)

OUT

> I

FASTRIP

to I

OUT

= 0 (Switch Off)

µs

EN/UVLO

→

H to V

BFET

= 12 V, C

BFET

= 1 nF

EN/UVLO

→

H to VB

FET

= 12 V, C

BFET

= 10 nF

EN/UVLO

→

L to

VBFET

= 1 V, C

BFET

= 1 nF

EN/UVLO

→

L to V

BFET

= 1 V, C

BFET

= 10 nF

4.2

BFET-ON

BFET Turn-On duration

(2)

BFET Turn-Off duratio

(2)

µs

0.4

1.4

BFET-OFF

(1) These

parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s

product warranty.

(2) These

parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s

product warranty.

ZHCSD51

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8.7 Typical

Characteristics

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

4.35

4.3

0.25

0.2

0.15

0.1

0.05

4.25

4.2

4.15

4.1

125

-40

4.05

-50

100

150

C001

C002

Temperature (

(V)

Figure 1. Input UVLO vs Temperature

Figure 2. IQ

OFF

vs V

0.8

0.6

0.4

0.2

6.6

6.4

6.2

5.8

5.6

5.4

125

-40

10 mA

C004

(V)

-50

100

150

TPS2592Bx

Temperature (

TPS2592Bx

Figure 4. V

OVC

vs Temperature

Figure 3. I

VIN-ON

vs V

250

230

210

190

170

150

VIN

VOUT

-50

100

150

Temperature (

TPS2592Bx

Figure 6. T

vs Temperature

Figure 5. Transient: Over Voltage Clamp

ZHCSD51

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Typical Characteristics (continued)

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

230

225

220

215

210

205

125

-40

-50

100

150

C010

C014

Temperature (

dVdT

(nF)

TPS2592Bx

Figure 7. I

dVdT

vs Temperature

Figure 8. T

dVdT

vs C

dVdT

1.41

1.4

100

1.39

1.38

1.37

1.36

1.35

1.34

Rising

Falling

125

-40

0.1

-50

Temperature (

100

150

(V)

Figure 9. V

EN_VIH

, V

EN_VIL

vs Temperature

Figure 10. I

(Leakage Current) vs V

VIN

VOUT

I_IN

I-IN

TPS2592Bx, C

dVdT

= OPEN, C

OUT

= 4.7 µF

TPS2592Bx, C

dVdT

= 1 nF, C

OUT

=10 µF, R

OUT

= 2.5

Figure 11. Transient: Output Ramp

Figure 12. Transient Output Ramp

ZHCSD51

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Typical Characteristics (continued)

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

VOUT

BFET

I_OUT

↓

Figure 14. Turn Off Delay to BFET

Figure 13. Transient: Turn Off Delay

VIN

VOUT

BFET

-50

100

150

Temperature (

VIN

↓

Figure 16. R

DSON

vs Temperature

Figure 15. Turn Off Delay to BFET

= 150 k

ILIM

3.5

2.5

= 100 k

ILIM

125

1.5

-40

0.5

1.5

0.5

1.5

(V)

VIN-OUT

150 k

100 k

Figure 17. I

OUT

vs V

VIN-OUT

Figure 18. I

OUT

vs V

VIN-OUT

ZHCSD51

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Typical Characteristics (continued)

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

2.2

-2

1.8

1.6

1.4

1.2

-4

= 45.3 k

ILIM

-6

IOL-150k

-8

ISC-150K-92B_

ISC-150K-92A_

-10

-12

-14

-16

125

-40

0.5

1.5

-50

100

150

Temperature (

(V)

VIN-OUT

150 k

45.3 k

Figure 20. I

, I

vs Temperature

Figure 19. I

OUT

vs V

VIN-OUT

-2

-4

-6

-8

-1

-2

-3

-4

-5

-6

IOL-45.3k

ISC-45.3K-92B_

ISC-45.3K-92A_

IOL-100K

ISC-100K-92B_

ISC-100K-92A_

-10

-12

-50

100

150

-50

100

150

Temperature (

100 k

45.3 k

Figure 21. I

, I

vs Temperature

Figure 22. I

, I

vs Temperature

0.9

0.58

0.85

0.8

0.57

0.56

0.55

0.54

0.53

0.52

0.51

0.5

0.75

0.7

0.65

0.6

0.55

0.5

-50

100

150

-50

100

150

Temperature (

ILIM

= 0

ILIM

= OPEN

Figure 23. I

OL-R-Short

vs Temperature

Figure 24. I

OL-R-Open

vs Temperature

ZHCSD51

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Typical Characteristics (continued)

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

3.1

VIN

3.09

VOUT

3.08

3.07

3.06

I_OJT

3.05

-50

100

150

Temperature (

Figure 26. Transient: Output Short Circuit

Figure 25. V

OpenILIM

vs Temperature

VIN

VOUT

I_IN

I_OUT

Figure 28. Transient: Recovery From Short Circuit / Over

Current

Figure 27. Short Circuit (Zoom): Fast-Trip Comparator

VIN

VOUT

I_IN

LOAD

Stepped From 50% to 120%, back to 50%

Figure 30. Transient: Overload Current Limit

Figure 29. Transient: Wake Up to Short Circuit

ZHCSD51

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Typical Characteristics (continued)

= 25°C, V

VIN

= 5 V, V

EN/UVLO

= 2 V, R

ILIM

= 100 k

, C

VIN

= 0.1 µF, C

OUT

= 1 µF, C

dVdT

= OPEN (unless stated otherwise)

VIN

VOUT

I_OUT

TPS2592BL

TPS2592BA

Figure 32. Transient: Thermal Fault Latched

Figure 31. Transient: Thermal Fault Auto-Retry

100

120

140

160

RILIM Resistor (k

)

Overload Current Limit (A)

D001

Figure 34. Overload Current Limit vs R

ILIM

Figure 33. Accuracy vs Overload Current Limit

ZHCSD51

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9 Detailed

Description

9.1 Overview

The TPS2592xx is an e-fuse with integrated power switch that is used to manage current/voltage/start-up voltage

ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the

undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables

the internal MOSFET. As VIN rises, the internal MOSFET of the device will start conducting and allow current to

flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has

the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.

After a successful start-up sequence, the device now actively monitors its load current and input voltage,

ensuring that the adjustable overload current limit I

is not exceeded and input voltage spikes are safely

clamped to V

OVC

level at the output. This keeps the output device safe from harmful voltage and current

transients. The device also has built-in thermal sensor. In the event device temperature (T

) exceeds T

SHDN

typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the

load from the supply. In TPS2592xL, the output will remain disconnected (MOSFET open) until power to device

is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain off during a

cooling period until device temperature falls below T

SHDN

– 10°C, after which it will attempt to restart. This ON

and OFF cycle will continue until fault is cleared.

9.2 Functional

Block Diagram

OUT

VIN

Current

Sense

28m

UVLO

4.3V

Charge

Pump

4.08V

EN/

UVLO

BFET

1.4V

Over

Voltage

1.35V

SWEN

GATE

CONTROL

SWEN

Thermal

Shutdown

TSD

VIN

220nA

ILIMIT

dV/dT

GND

ILIM

4.8x

70pF

SWEN

Fast Trip

Comp

1.6*ILIMIT

9.3 Feature

Description

9.3.1 GND

This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless

otherwise specified.

ZHCSD51

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ECEMBER 2014

Feature Description (continued)

9.3.2 VIN

Input voltage to the TPS2592Bx. A ceramic bypass capacitor close to the device from VIN to GND is

recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 5.5 V for

TPS2592Bx. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the

recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the

output voltage to V

OVC

. The power dissipation in OVP mode is P

D_OVP

= (V

VIN

– V

OVC

) x I

OUT

, which can

potentially heat up the device and cause thermal shutdown.

9.3.3 dV/dT

Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can

be left floating to obtain a predetermined slew rate (minimum T

dVdT

) on the output. Equation governing slew rate

at start-up is shown below:

OUT

dVdT

GAIN

dVdT

INT

(1)

Where:

dVdT

= 220 nA (TYP)

INT

= 70 pF (TYP)

GAIN

dVdT

= 4.85

OUT

Desired output slew rate

The total ramp time (T

dVdT

) for 0 to VIN can be calculated using the following equation:

dVdT

= 10

70 pF

dVdT

(

)

(2)

For details on how to select an appropriate charging time/rate, refer to the applications section:

9.3.4 BFET

Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the

event of power failure at VIN. The BFET pin is controlled by either UVLO event or EN/UVLO (see

Table 1

). BFET

can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the external FET via a

26-

Ω

internal discharge resistor to initiate fast turn-off, typically <1 µs. Due to 2 µA charging current, it is

recommended to use >10 M

impedance when probing the BFET node.

Table 1.

EN/UVLO > V

ENR

VIN>V

UVR

BFET MODE

Charge

Discharge

9.3.5 EN/UVLO

As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET.

In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this

pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge

resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also

used to clear a thermal shutdown latch in the TPS2592xL by toggling this pin (H

→

L).

The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of

power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on

EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current (see typical

application diagram,

Figure 42

). For applications where a higher de-glitch delay on EN/UVLO is desired, or when

the supply is

particularly noisy,

it is recommended to use an external bypass capacitor from EN/UVLO to GND.

ZHCSD51

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ECEMBER 2014

9.3.6 ILIM

The device continuously monitors the load current and keeps it limited to the value programmed by R

ILIM

. After

start-up event and during normal operation, current limit is set to I

(over-load current limit).

0.7

–

ILIM

(

)

(3)

When power dissipation in the internal MOSFET [P

= (V

VIN

– V

OUT

) × I

OUT

] exceeds 10 W, there is a 2% – 12%

thermal foldback in the current limit value so that I

drops to I

. In each of the two modes, MOSFET gate

voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts

down due to over temperature.

-2

-4

-6

-8

-10

-12

-14

Power (W)

Figure 35.

Thermal Foldback in Current Limit

During a transient short circuit event, the current through the device increases very rapidly. The current-limit

amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592

incorporates a fast-trip comparator, which shuts down the pass device very quickly when I

OUT

> I

FASTRIP

, and

terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-

load current limit (I

FASTRIP

= 1.6 x I

). After the transient short-circuit peak current has been terminated by the

fast-trip comparator, the current limit amplifier smoothly regulates the output current to I

(see figure below).

VIN

VOUT

I_OUT

Figure 37. Fast-Trip and Current Limit Amplifier Response

for Short Circuit

Figure 36. Fast-Trip Current

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9.4 Device

Functional Modes

The TPS2592xx is

a hot-swap controller with integrated power switch that is used to manage

current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN

bus. When V

VIN

exceeds the undervoltage-lockout threshold (V

UVR

), the device samples the EN/UVLO pin. A high

level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if

connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)

will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below V

ENF

the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to

OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT

pin and GND.

Having successfully completed its start-up sequence, the device now actively monitors its load current and input

voltage, ensuring that the adjustable overload current limit I

is not exceeded and input voltage spikes are safely

clamped to V

OVC

level at the output. This keeps the output device safe from harmful voltage and current

transients. The device also has built-in thermal sensor. In the event device temperature (T

) exceeds T

SHDN

typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the

load from the supply. In the TPS2592xL, the output will remain disconnected (MOSFET open) until power to

device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain off

during a cooling period until device temperature falls below T

SHDN

– 10°C, after which it will attempt to restart.

This ON and OFF cycle will continue until fault is cleared.

TPS2592 Design Calculator (SLUC571)

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10 Application

and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application

Information

The TPA2592xx is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It

operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in

controlling the in-rush current and provides precise current limiting during overload conditions for systems such

as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust

protection for multiple faults on the sub-system rail.

The following design procedure can be used to select component values for the device. Alternatively, the

WEBENCH

software may be used to generate a complete design. The WEBENCH

software uses an iterative

design procedure and accesses a comprehensive database of components when generating a design.

Additionally, a spreadsheet design tool

is available on web folder. This

section presents a simplified discussion

of the design process.

10.2 Typical

Applications

10.2.1 Simple

3.7-A eFuse Protection for Set Top Boxes

= 4.5 to 18 V

OUT,

OUT

< 3.4A

OUT

VIN

0.1µF

ꢀ

OUT

1µF

28m

ꢀ

EN/UVLO

BFET

ILIM

dVdT

GND

TPS2592x

ILIM

100k

**Optional & only needed for external UVLO

*Optional & only for noise suppression

Figure 38.

Typical Application Schematic: Simple 3.7-A e-Fuse for STBs

10.2.1.1 Design

Requirements

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range, V

EXAMPLE VALUE

5 V

Undervoltage lockout set point, V

(UV)

Overvoltage protection set point , V

(OV)

Load at Start-Up , R

L(SU)

Default: V

UVR

= 4.3 V

Default: V

OVC

= 6.1 V

3.7 A

1 µF

85°C

Current limit, I

= I

ILIM

Load capacitance , C

OUT

Maximum ambient temperatures , T

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10.2.1.2 Detailed

Design Procedure

The following design procedure can be used to select component values for the TPS2592xx.

10.2.1.2.1 Step

by Step Design Procedure

This design procedure below seeks to control the junction temperature of device under both static and transient

conditions by proper selection of output ramp-up time and associated support components. The designer can

adjust this procedure to fit the application and design criteria.

10.2.1.2.2 Programming

the Current-Limit Threshold: R

ILIM

Selection

The R

ILIM

resistor at the ILIM pin sets the over load current limit, this can be set using

Equation 4

– 0.7

ILIM

-5

3 x 10

(4)

For I

= I

ILIM

= 3.7 A, from equation 4, R

ILIM

= 100 k

. Choose closest standard value resistor with 1%

tolerance.

10.2.1.2.3 Undervoltage

Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R

and R

connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage

are calculated solving

Equation 5

ENR

(UV)

(5)

Where V

ENR

= 1.4 V, is enable voltage rising threshold.

Since R

and R

will leak the current from input supply (VIN), these resistors should be selected based on the

acceptable leakage current from input power supply (VIN). The current drawnby R

and R

from the power

supply {I

R12

= V

/(R

+ R

)}.

However, leakage currents due to external active components connected to the resistor string can add error to

these calculations. So, the resistor string current, I

R12

must be chosen to be 20x greater than the leakage current

expected.

For default UVLO of V

UVR

= 4.3 V, select R

= OPEN, and R

= 1 M

. Since EN/UVLO pin is rated only to 7 V, it

cannot be connected directly to V

> 7 V. It has to be connected through R

= 1 M

only, so that the pull-up

current for EN/UVLO pin is limited to < 20 µA.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the

rising threshold, V

UVR

. This is calculated using

Equation 6

(PFAIL)

= 0.96 x V

UVR

(6)

Where V

UVR

is 4.3V, Power fail threshold set is : V

(PFAIL)

= 4.1 V

10.2.1.2.4 Setting

Output Voltage Ramp Time (T

dVdT

)

For a successful design, the junction temperature of device should be kept below the absolute-maximum rating

during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of

magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush

current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor C

dVdT

needed is calculated considering the two possible cases:

10.2.1.2.4.1 Case

1: Start-up without Load: Only Output Capacitance C

OUT

Draws Current During Start-up

During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across

the internal FET decreases. The average power dissipated in the device during start-up is calculated using

For TPS2592xx, the inrush current is determined as,

(IN)

C x

(OUT)

(INRUSH)

dVdT

(7)

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Power dissipation during start-up is:

0.5 x V

x I

(IN) (INRUSH)

D(INRUSH)

(8)

assumes that load does not draw any current until the output voltage has reached its final value.

10.2.1.2.4.2 Case

2: Start-up with Load: Output Capacitance C

OUT

and Load Draws Current During Start-up

When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a

resistive load during start-up (R

L(SU)

), load current ramps up proportionally with increase in output voltage during

dVdT

time. The average power dissipation in the internal FET during charging time due to resistive load is given

by:

(IN)

D(LOAD)

L(SU)

(9)

(10)

(11)

Total power dissipated in the device during startup is:

P +

D(INRUSH) D(LOAD)

D(STARTUP)

Total current during startup is given by:

+ I

(t)

(STARTUP)

(INRUSH) L

If I

(STARTUP)

> I

, the device limits the current to I

and the current limited charging time is determined by:

(INRUSH)

x R

L(SU)

–

dVdT(Current-Limited)

OUT

(IN)

(INRUSH)

–

L(SU)

(12)

The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as

shown in

Figure 39

10000

= -40

= 25

= 85

1000

= 125

100

0.1

100

Power Dissipation (W)

D001

Figure 39.

Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor C

dVdT

= OPEN. Then, using

Equation 2

= 10

x 5 x

0 + 70 pF

350

)

(

dVdT

(13)

The inrush current drawn by the load capacitance (C

OUT

) during ramp-up using

Equation 7

= 1

F x

= 14.3 mA

(INRUSH)

350

(14)

(15)

The inrush Power dissipation is calculated, using

= 0.5 x 5 x 14.3 m = 36 mW

D(INRUSH)

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For 36 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time

dVdT

to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph

Figure 39

= 85°C, for 36 mW of power, the shutdown time is infinite. So it is safe to use 350 µs as start-up

time without

any load on output.

Considering the start-up with load 2

, the additional power dissipation, when load is present during start up is

calculated, using

Equation 9

5 x 5

= 2.08 W

D(LOAD)

(16)

The total device power dissipation during start up, using

Equation 10

is:

= 2.08

36 m = 2.44 W

D(STARTUP)

(17)

From thermal shutdown limit graph at T

= 85°C, the thermal shutdown time for 2.44 W is more than 100 ms. So

it is well within acceptable limits to use no external capacitor (C

dV/dT

) with start-up load of 2

If, due to large C

OUT

, there is a need to decrease the power loss during start-up, it can be done with increase of

dVdT

capacitor.

10.2.1.3 Support

Component Selection – C

VIN

is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where

acceptable, a value in the range of 0.001

F to 0.1

F is recommended for C

VIN

10.2.1.4 Application

Curves

Figure 40.

Output Ramp without Load on Output

Figure 41. Output Ramp with 2-

Load at Start Up

10.2.2 Inrush

and Reverse Current Protection for Hold-Up Capacitor Application (e.g., SSD)

Blocking FET

OUT

, I

OUT

< 2.7A

VIN

HOLD-UP

4700

VIN

0.1

28m

CSD16411

FLTb

EN/UVLO

dVdT

BFET

ILIM

453k

ZXM61P03F

ILIM

76.8k

dVdT

22nF

GND

TPS2592xx

*Optional & only for noise suppression

Figure 42.

Inrush and Reverse Current Protection for Hold-Up Capacitor Application (e.g., SSD)

(TPS2592 UVLO is used as power fail comparator)

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10.2.2.1 Design

Requirements

Table 3. Design Parameters

DESIGN PARAMETER

Input voltage range, V

EXAMPLE VALUE

5 V

4.5 V

Undervoltage lockout set point, V

(UV)

Overvoltage protection set point , V

(OV)

Load at Start-Up , R

L(SU)

Default: V

OVC

= 6.1 V

1000

Current limit, I

= I

ILIM

3 A

Load capacitance , C

OUT

4700 µF

85°C

Maximum ambient temperatures , T

10.2.2.2 Detailed

Design Procedure

10.2.2.2.1 Programming

the Current-Limit Threshold: R

ILIM

Selection

The R

ILIM

resistor at the ILIM pin sets the over load current limit, this can be set using

Equation 4

For I

= I

ILIM

= 3 A, from equation 4, R

ILIM

= 76.8 k

, choose closest standard value resistor with 1% tolerance.

10.2.2.2.2 Undervoltage

Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R

and R

connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage

are calculated solving

Equation 5

For UVLO of V

(UV)

= 4.5 V, select R

= 453 k

, and R

= 1 M

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the

rising threshold, V

(UV)

. This is calculated using

Equation 6

Where V

(UV)

= 4.5 V, Power fail threshold set is : V

(PFAIL)

= 4.33 V

10.2.2.2.3 Setting

Output Voltage Ramp Time (T

dVdT

)

For a successful design, the junction temperature of device should be kept below the absolute-maximum rating

during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of

magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush

current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

For the design example under discussion, select ramp-up capacitor C

dVdT

= 22 nF. Then, using

Equation 2

= 10

x 5 x

22 nF + 70 pF

110 ms

)

(

dVdT

(18)

The inrush current drawn by the load capacitance (C

OUT

) during ramp-up using

Equation 7

= 4700

F x

= 213 mA

(INRUSH)

110 ms

(19)

(20)

The inrush Power dissipation is calculated, using

= 0.5 x 5 x 213 m = 533 mW

D(INRUSH)

Considering the start-up with load 1000

, the additional power dissipation, when load is present during start up

is calculated, using

Equation 9

5 x 5

= 4.2 mW

D(LOAD)

1000

(21)

The total device power dissipation during start up is:

= 533

4.2 = 537 mW

D(STARTUP)

(22)

From thermal shutdown limit graph at T

= 85°C, the thermal shutdown time for 537 mW is more than 300 ms.

So the device will start safely.

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10.2.2.3 Support

Component Selection – C

VIN

is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where

acceptable, a value in the range of 0.001

F to 0.1

F is recommended for C

VIN

10.2.2.4 Application

Curves

OUT

= C

HOLD-UP

dVdT

= 22 nF

OUT

= C

HOLD-UP

(PFAIL)

= 4.33 V

LOAD

= 5

4700 µF

Figure 43.

Output Ramp Up

Figure 44. Hold-Up Power when VIN fails

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10.3 Maximum

Device Power Dissipation Considerations

To prevent damage to the TPS2592x, it is necessary to keep internal power dissipation (P

) below the levels

specified in below Table. The power dissipation is defined as (P

= (V

– V

OUT

) x I

OUT

MIN

MAX

UNIT

–40°C

≤

+85°C

0°C

≤

+85°C

Maximum Power Dissipation

During normal operation P

is low ( typically < ½ Watt) because the FET is fully on with low (V

– V

OUT

However, during short circuit and surge protection the FET may be only partially on and (V

– V

OUT

) can be high.

Example 1: Short Circuit on Output

→

= 5 V, I

LIMIT

= 5 A. T

= –40°C

•

= 5 V x 5 A = 25 W

→

= 25 W) < (P

D_MAX

= 40 W)

Example 2: Surge Clamp

→

= 5 V, I

LIMIT

= 3.7 A. T

= 0°C, V

SURGE

= 19 V, V

CLAMP

= 6.1 V

•

= (19 – 6.1) x 3 A = 47.7 Watt

OK at T

= 0°C

→

= 47.7 W) < (P

D_MAX

at 0°C = 50 W)

NOT OK at –40°C

→

= 47.7 W) > (P

D_MAX

at –40°C = 40 W)

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11 Power

Supply Recommendations

The device is designed for supply voltage range of 4.5 V

≤

18 V. If the input supply is located more than a

few inches from the device an input ceramic bypass capacitor higher than 0.1

F is recommended. Power supply

should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit

conditions.

11.1 Transient

Protection

In case of short circuit and over load current limit, when the device interrupts current flow, input inductance

generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the

output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the

input or output of the device. Such transients can exceed the

Absolute Maximum Ratings

of the device if steps

are not taken to address the issue.

Typical methods for addressing transients include

•

Minimizing lead length and inductance into and out of the device

Using large PCB GND plane

Schottky diode across the output to absorb negative spikes

A low value ceramic capacitor (C

(IN)

= 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.

The approximate value of input capacitance can be estimated with

Equation 23

(IN)

V x

I x

(IN) (LOAD)

SPIKE(Absolute)

(IN)

(23)

Where:

•

(IN)

is the nominal supply voltage

(LOAD)

is the load current,

(IN)

equals the effective inductance seen looking into the source

(IN)

is the capacitance present at the input

Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from

exceeding the

Absolute Maximum Ratings

of the device.

The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is

shown in

Figure 45

OUT

VIN

0.1µF

28m

ꢀ

OUT

EN/UVLO

dVdT

BFET

ILIM

dVdT

GND

TPS2592x

*Optional components for

transient suppression

ILIM

Figure 45.

Circuit Implementation with Optional Protection Components

11.2 Output

Short-Circuit Measurements

It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit

layout and component selection, output shorting method, relative location of the short, and instrumentation all

contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it

microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do

not expect to see waveforms exactly like those in the data sheet; every setup differs.

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12 Layout

12.1 Layout

Guidelines

•

For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal

and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be

eliminated/minimized.

•

The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care

must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the

GND terminal of the IC. See

Figure 46

for a PCB layout example.

•

High current carrying power path connections should be as short as possible and should be sized to carry at

least twice the full-load current.

The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be

a copper plane or island on the board.

Locate all support components: R

ILIM

, C

dVdT

and resistors for EN/UVLO, close to their connection pin. Connect

the other end of the component to the GND pin of the device with shortest trace length. The trace routing for

the R

ILIM

and C

dVdT

components to the device should be as short as possible to reduce parasitic effects on

the current limit and soft start timing. These traces should not have any coupling to switching signals on the

board.

•

Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the

device they are intended to protect, and routed with short traces to reduce inductance. For example, a

protection Schottky diode is recommended to address negative transients due to switching of inductive loads,

and it should be physically close to the OUT pins.

Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been

shown to produce good results and is intended as a guideline.

12.2 Layout

Example

Top layer

Bottom layer signal ground plane

Via to signal ground plane

Ground –

Bottom

layer

dV/dT

EN/UVLO

VIN

ILIM

BFET

OUT

VIN

VOUT

VIN

High Frequency

Bypass Capacitor

* Optional: Needed only to suppress the transients caused by inductive load switching

Figure 46.

Layout Example

版权

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