tps2592za
| Part # | tps2592za |
Download  | tps2592za |
ZHCSD52
–
D
ECEMBER 2014
TPS2592Zx
具有阻断
FET
控制功能的
4.5V
至
18V
电子熔丝
1
特性
3
说明
1
•
4.5V
至
18V
电压保护
TPS2592xx
系列电子熔丝是小型封装内高度集成电路
的保护和电源管理解决方案。 该器件使用极少的外部
组件并可提供多重保护模式。 它们能够有效地防止过
载、短路、电压浪涌、过高浪涌电流和反向电流。
•
集成
28m
Ω
导通金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
•
•
•
最大绝对电压
20V
1A
至
2.1A
可调电流
I
LIMIT
支持反向电流阻断
电流限制级别可通过一个外部电阻设定。 具有特殊电
压斜坡要求的应用可以使用单个电容来设定
dV/dT
引
脚，以确保达到适当的输出斜坡速率。
可编程
OUT
（输出）转换率，欠压闭锁
(UVLO)
内置热关断
许多系统（例如
SSD
）禁止将储存的电容能量通过
FET
二极管倒流到降压或短路输入总线。
BFET
引脚
专用于这类系统。 外部
NFET
可与
TPS2592
输出形
成
“
背靠背
(B2B)”
连接，而由
BFET
驱动的栅极可防止
电流从负载流回电源。
单点故障测试期间安全
(UL60950)
小型封装尺寸
– 10L (3mm x 3mm)
超薄小外形尺寸
无引线封装
(VSON)
2
应用
•
•
•
•
•
•
硬盘
(HDD)
和固态硬盘
(SSD)
机顶盒
器件型号
TPS2592ZA
TPS2592ZL
封装
封装尺寸（标称值）
服务器
/
辅助
(AUX)
电源
风扇控制
VSON (10)
3.00mm × 3.00mm
PCI/PCIe
卡
(1)
如需了解所有可用封装，请见数据表末尾的可订购产品附录。
适配器供电器件
瞬态：输出短路
4
应用电路原理图
OUT
OUT
VIN
VIN
R
1
VIN
28m
:
VOUT
C
OUT
EN/UVLO
dV/dT
BFET
ILIM
C2
C3
R
2
RLIM
C
dVdT
GND
TPS2592xx
I_OUT
C1
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
ZHCSD52
–
D
ECEMBER 2014
目录
1
2
3
4
5
6
7
8
10.3 Maximum
Device Power Dissipation
9
5
修订历史记录
日期
修订版本
注释
2014
年
12
月
*
最初发布版本
2
Copyright © 2014, Texas Instruments Incorporated
ZHCSD52
–
D
ECEMBER 2014
6 Device
Comparison Table
PART NUMBER
TPS2592ZA
UV
OV CLAMP
FAULT RESPONSE
Auto-retry
STATUS
Active
4.3 V
4.3 V
—
—
TPS2592ZL
Latched
Preview
7 Pin
Configuration and Functions
10-Pin VSON
DRC Package
(Top View)
1
dV/dT
10
ILIM
EN/UVLO
BFET
OUT
OUT
GND
VIN
VIN
VIN
6
5
OUT
Pin Functions
PIN
NUMBER
DESCRIPTION
NAME
BFET
9
1
2
dV/dT
Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.
EN/UVLO
This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal
pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.
GND
ILIM
OUT
VIN
PowerPAD™
GND
10
6-8
3-5
A resistor from this pin to GND will set the overload and short circuit limit.
Output of the device
Input supply voltage
Copyright © 2014, Texas Instruments Incorporated
3
ZHCSD52
–
D
ECEMBER 2014
8 Specifications
8.1 Absolute
Maximum Ratings
over operating temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
20
UNIT
VIN
Supply voltage range
(1)
–0.3
V
VIN (10 ms Transient)
22
OUT
Output voltage
–0.3
VIN + 0.3
V
V
OUT (Transient < 1 µs)
-1.2
7
ILIM
–0.3
–0.3
–0.3
–0.3
EN/UVLO
7
Voltage
V
dV/dT
7
BFET
Continuous power dissipation
T
A
= –40°C to +85°C
30
See the Thermal Information
Maximum power dissipation
(3)
P
D
= (V
VIN
-V
OUT
)*I
LIMIT
,
40
W
°C
T
A
= 0°C to +85°C
50
Storage temperature range, T
stg
-65
150
(1) Stresses
beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All
voltage values, except differential voltages, are with respect to network ground terminal.
(3) Refer
detailed explanation in the application section
Maximum Device Power Dissipation Considerations
.
8.2 ESD
Ratings
MAX
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101
(2)
V
(ESD)
Electrostatic discharge
V
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
VIN
4.5
0
18
(1)
BFET
VIN+6
Input voltage range
V
6
dV/dT, EN/UVLO
0
ILIM
I
OUT
0
3.3
Continuous output current
Resistance
0
1.7
45.3
1000
1000
125
A
ILIM
OUT
dV/dT
10
0.1
k
Ω
µF
nF
°C
°C
1
1
External capacitance
Operating junction temperature range, T
J
Operating Ambient temperature range, T
A
–40
–40
25
25
85
(1) Maximum
voltage (including input transients) at VIN pin should not exceed absolute maximum rating as specified in
Absolute Maximum
4
Copyright © 2014, Texas Instruments Incorporated
ZHCSD52
–
D
ECEMBER 2014
8.4 Thermal
Information
(1)
over operating free-air temperature range (unless otherwise noted)
TPS2592Zx
UNIT
THERMAL METRIC
DRC (10) PINS
R
θ
JA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45.9
53
R
θ
JCtop
R
θ
JB
21.2
°C/W
1.2
ψ
JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψ
JB
21.4
5.9
R
θ
JCbot
(1) For
more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,
SPRA953
.
8.5 Electrical
Characteristics
–40°C
≤
T
J
≤
125°C, VIN = 12 V, V
EN /UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
dVdT
= OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.15
0.2
TYP
MAX
UNIT
VIN (INPUT SUPPLY)
V
UVR
UVLO threshold, rising
UVLO hysteresis
(1)
4.3
5.4%
0.42
0.1
4.45
V
V
UVhyst
IQ
ON
Enabled: EN/UVLO = 2 V
0.65
0.25
mA
mA
Supply current
IQ
OFF
EN/UVLO = 0 V
EN/UVLO (ENABLE/UVLO INPUT)
V
ENR
V
ENF
I
EN
EN Threshold voltage, rising
1.37
1.32
–100
1.4
1.35
0
1.44
1.39
100
V
V
EN Threshold voltage, falling
EN Input leakage current
0 V
≤
V
EN
≤
5V
nA
dV/dT (OUTPUT RAMP CONTROL)
I
dVdT
dV/dT Charging current
(1)
V
dVdT
= 0 V
220
73
nA
Ω
R
dVdT_disch
V
dVdTmax
GAIN
dVdT
dV/dT Discharging resistance
dV/dT Max capacitor voltage
(1)
dV/dT to OUT gain
(1)
EN/UVLO = 0 V, I
dVdT
= 10 mA sinking
50
100
5.5
V
Δ
V
dVdT
4.85
V/V
ILIM (CURRENT LIMIT PROGRAMMING)
I
ILIM
I
OL
ILIM Bias current
(1)
10
µA
A
R
ILIM
= 45.3 k
Ω
, V
VIN-OUT
= 1 V
1.79
1.66
2.10
2.42
2.29
R
ILIM
= 0
Ω
, Shorted Resistor Current Limit (Single Point
I
OL-R-Short
0.7
A
Overload current limit
(2)
Short-circuit current limit
(2)
Failure Test: UL60950)
(1)
R
ILIM
= OPEN, Open Resistor Current Limit (Single Point
Failure Test: UL60950)
(1)
I
OL-R-Open
I
SCL
0.55
1.98
A
A
R
ILIM
= 45.3 k
Ω
, V
VIN-OUT
= 12 V
Fast-Trip comparator level w.r.t.
overload current limit
(1)
RATIO
FASTRIP
I
FASTRIP
: I
OL
160%
ILIM Open resistor detect
threshold
(1)
V
OpenILIM
V
ILIM
Rising, R
ILIM
= OPEN
3.1
V
OUT (PASS FET OUTPUT)
T
J
= 25°C
21
28
39
0
33
46
1
R
DS(on)
FET ON resistance
m
Ω
T
J
= 125°C
I
OUT-OFF-LKG
I
OUT-OFF-SINK
V
EN/UVLO
= 0 V, V
OUT
= 0 V (Sourcing)
V
EN/UVLO
= 0V, V
OUT
= 300 mV (Sinking)
–5
10
OUT Bias current in off state
µA
15
20
(1) These
parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
(2) Pulsed
testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
Copyright © 2014, Texas Instruments Incorporated
5
ZHCSD52
–
D
ECEMBER 2014
Electrical Characteristics (continued)
–40°C
≤
T
J
≤
125°C, VIN = 12 V, V
EN /UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
dVdT
= OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BFET (BLOCKING FET GATE DRIVER)
I
BFET
BFET Charging current
(1)
V
BFET
= V
OUT
2
µA
V
V
VIN
+
6.4
V
BFETmax
BFET Clamp voltage
(1)
BFET Discharging resistance to
GND
R
BFETdisch
V
EN/UVLO
= 0 V, I
BFET
= 100 mA
15
26
36
Ω
TSD (THERMAL SHUT DOWN)
T
SHDN
TSD Threshold, rising
(1)
TSD Hysteresis
(1)
160
10
°C
°C
T
SHDNhyst
TPS2592ZL
TPS2592ZA
LATCHED
AUTO-RETRY
Thermal fault: latched or autoretry
8.6 Timing
Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
220
0.4
MAX UNIT
EN/UVLO
→
H to I
VIN
= 100 mA, 1-A resistive load at
T
ON
Turn-on delay
(1)
Turn Off delay
(2)
µs
µs
OUT
t
OFFdly
EN
↓
to BFET
↓
, C
BFET
= 0
dV/dT (OUTPUT RAMP CONTROL)
EN/UVLO
→
H to OUT = 11.7 V, C
dVdT
= 0
0.7
1
1.3
ms
t
dVdT
Output ramp time
EN/UVLO
→
H to OUT = 11.7 V,
12
C
dVdT
= 1 nF
(2)
ILIM (CURRENT LIMIT PROGRAMMING)
t
FastOffDly
Fast-Trip comparator delay
(2)
BFET (BLOCKING FET GATE DRIVER)
I
OUT
> I
FASTRIP
to I
OUT
= 0 (Switch Off)
3
µs
EN/UVLO
→
H to V
BFET
= 12 V, C
BFET
= 1 nF
EN/UVLO
→
H to VB
FET
= 12 V, C
BFET
= 10 nF
EN/UVLO
→
L to
VBFET
= 1 V, C
BFET
= 1 nF
EN/UVLO
→
L to V
BFET
= 1 V, C
BFET
= 10 nF
4.2
42
t
BFET-ON
BFET Turn-On duration
(2)
BFET Turn-off duration
(2)
ms
µs
0.4
1.4
t
BFET-OFF
(1) These
parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
(2) These
parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
6
Copyright © 2014, Texas Instruments Incorporated
ZHCSD52
–
D
ECEMBER 2014
8.7 Typical
Characteristics
T
J
= 25°C, V
VIN
= 12 V, V
EN/UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
VIN
= 0.1 µF, C
OUT
= 1 µF, C
dVdT
= OPEN (unless stated otherwise)
4.35
4.3
0.25
0.2
0.15
0.1
0.05
0
4.25
4.2
4.15
4.1
125
C
85
C
25
C
-40
C
4.05
4
-50
0
50
100
150
0
5
10
15
20
C001
C002
Temperature (
C)
V
IN
(V)
Figure 1. Input UVLO vs Temperature
Figure 2. IQ
OFF
vs V
IN
0.6
0.5
0.4
0.3
0.2
0.1
0
250
230
210
190
170
150
125
°
C
85
°
C
25
°
C
-40
°
C
0
5
10
15
20
C003
V
IN
(V)
-50
0
50
100
150
TPS2592Zx
Temperature (
o
C)
Figure 4. T
ON
vs Temperature
Figure 3. I
VIN-ON
vs V
IN
230
225
220
215
210
150
100
50
125
C
85
C
25
C
-40
C
205
-50
0
0
50
100
150
0
2
4
6
8
10
C010
C013
Temperature (
C)
C
dVdT
(nF)
TPS2592Zx
Figure 5. I
dVdT
vs Temperature
Figure 6. T
dVdT
vs C
dVdT
Copyright © 2014, Texas Instruments Incorporated
7
ZHCSD52
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Typical Characteristics (continued)
T
J
= 25°C, V
VIN
= 12 V, V
EN/UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
VIN
= 0.1 µF, C
OUT
= 1 µF, C
dVdT
= OPEN (unless stated otherwise)
1.41
100
10
1
1.4
1.39
1.38
1.37
1.36
1.35
1.34
Rising
Falling
125
C
85
C
25
C
-40
C
0.1
-50
0
50
Temperature (
o
C)
100
150
0
1
2
3
4
5
V
(V)
EN
Figure 8. I
EN
(Leakage Current) vs V
EN
Figure 7. V
EN_VIH
, V
EN_VIL
vs Temperature
EN
EN
C
1
VIN
C
1
2
VOUT
C
2
C3
VOUT
I_IN
C3
C4
I_OUT
C4
TPS2592Zx, C
dVdT
= OPEN, C
OUT
= 4.7 µF
EN
↓
Figure 9. Transient: Output Ramp:
Figure 10. Transient: Turn Off Delay
EN
VIN
C
1
VOUT
VOUT
BFET
C
1
BFET
C3
C2
C3
C2
EN
↓
VIN
↓
Figure 11. Turn Off Delay to BFET
Figure 12. Turn Off Delay to BFET
8
Copyright © 2014, Texas Instruments Incorporated
ZHCSD52
–
D
ECEMBER 2014
Typical Characteristics (continued)
T
J
= 25°C, V
VIN
= 12 V, V
EN/UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
VIN
= 0.1 µF, C
OUT
= 1 µF, C
dVdT
= OPEN (unless stated otherwise)
2.2
45
40
35
30
25
20
2
1.8
1.6
1.4
1.2
1
R
= 45.3 k
W
ILIM
125
o
C
85
o
C
25
o
C
-40
o
C
0
0.5
1
1.5
2
-50
0
50
100
150
Temperature (
o
C)
V
(V)
VIN-OUT
45.3 k
Ω
Figure 13. R
DSON
vs Temperature
Figure 14. I
OUT
vs V
VIN-OUT
1
0
0.9
0.85
0.8
-1
-2
-3
-4
-5
-6
0.75
0.7
IOL-45.3k
ISC-45.3K-92B_
ISC-45.3K-92A_
0.65
0.6
0.55
0.5
-50
0
50
100
150
-50
0
50
100
150
Temperature (
o
C)
Temperature (
o
C)
45.3 k
Ω
R
ILIM
= 0
Figure 15. I
OL
, I
SC
vs Temperature
Figure 16. I
OL-R-Short
vs Temperature
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.5
3.1
3.09
3.08
3.07
3.06
3.05
-50
0
50
100
150
-50
0
50
100
150
Temperature (
o
C)
Temperature (
o
C)
R
ILIM
= OPEN
Figure 17. I
OL-R-Open
vs Temperature
Figure 18. V
OpenILIM
vs Temperature
Copyright © 2014, Texas Instruments Incorporated
9
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Typical Characteristics (continued)
T
J
= 25°C, V
VIN
= 12 V, V
EN/UVLO
= 2 V, R
ILIM
= 45.3 k
Ω
, C
VIN
= 0.1 µF, C
OUT
= 1 µF, C
dVdT
= OPEN (unless stated otherwise)
VIN
VIN
VOUT
VOUT
C2
C3
C2
C3
I_OJT
I_OUT
C
1
C
C
1
Figure 19. Transient: Output Short Circuit
Figure 20. Short Circuit (Zoom): Fast-trip Comparator
EN
VIN
VIN
C1
C
VOUT
VOUT
C2
C3
C2
C3
I_IN
I_OUT
C4
C1
I
LOAD
Stepped From 50% to 120%, back to 50%
TPS2592ZA
Figure 21. Transient: Overload Current Limit
Figure 22. Transient: Thermal Fault Auto-Retry
EN
C
1
VIN
C
2
C3
VOUT
I_IN
C4
TPS2592ZL
TPS2592Zx, C
dVdT
= OPEN, C
OUT
= 10 µF
Figure 23. Transient: Thermal Fault Latched
Figure 24. Transient: Output Ramp
10
Copyright © 2014, Texas Instruments Incorporated
ZHCSD52
–
D
ECEMBER 2014
9 Detailed
Description
9.1 Overview
The TPS2592xx is an e-fuse with integrated power switch that is used to manage current/voltage/start-up voltage
ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the
undervoltage-lockout threshold (V
UVR
), the device samples the EN/UVLO pin. A high level on this pin enables the
internal MOSFET. As VIN rises, the internal MOSFET of the device will start conducting and allow current to flow
from VIN to OUT. When EN/UVLO is held low (below V
ENF
), internal MOSFET is turned off. User also has the
ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current, ensuring that the
adjustable overload current limit I
OL
is not exceeded. The device also has built-in thermal sensor. In the event
device temperature (T
J
) exceeds T
SHDN
, typically 160°C, the thermal shutdown circuitry will shut down the
internal MOSFET thereby disconnecting the load from the supply. In TPS2592xL, the output will remain
disconnected (MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then
high). The TPS2592xA device will remain off during a cooling period until device temperature falls below T
SHDN
10°C, after which it will attempt to restart. This ON and OFF cycle will continue until fault is cleared.
–
9.2 Functional
Block Diagram
OUT
VIN
6,
7,
8
3,
4,
5
Current
Sense
28m
W
+
UVLO
4.3V
Charge
Pump
4.08V
EN/
2
m
A
2
+
UVLO
EN
BFET
1.4V
Over
Voltage
9
1.35V
SWEN
6V
GATE
CONTROL
SWEN
22
W
Thermal
Shutdown
6V
TSD
VIN
220nA
10
m
A
+
ILIMIT
dV/dT
GND
ILIM
1
4.8x
10
+
+
70pF
SWEN
Fast Trip
Comp
80
W
EP
1.6*ILIMIT
9.3 Feature
Description
9.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
9.3.2 VIN
Input voltage to the TPS2592Zx. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 18 V for
TPS2592Zx. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the
output voltage to V
OVC
. The power dissipation in OVP mode is P
D_OVP
= (V
VIN
– V
OVC
) x I
OUT
, which can
potentially heat up the device and cause thermal shutdown.
Copyright © 2014, Texas Instruments Incorporated
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Feature Description (continued)
9.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum T
dVdT
) on the output. Equation governing slew rate
at start-up is shown below:
dV
OUT
I
dVdT
´
GAIN
dVdT
=
dt
C
dVdT
+
C
INT
(1)
Where:
I
dVdT
= 220 nA (TYP)
C
INT
= 70 pF (TYP)
GAIN
dVdT
= 4.85
dV
OUT
=
Desired output slew rate
dT
The total ramp time (T
dVdT
) for 0 to VIN can be calculated using the following equation:
T
dVdT
= 10
6
´
V
´
C
+
70 pF
dVdT
(
)
IN
(2)
For details on how to select an appropriate charging time/rate, refer to the applications section:
Setting Output
9.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either UVLO event or EN/UVLO (see
Table 1
). BFET
can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the external FET via a
26-
Ω
internal discharge resistor to initiate fast turn-off, typically <1 µs. Due to 2 µA charging current, it is
recommended to use >10 M
Ω
impedance when probing the BFET node.
Table 1.
EN/UVLO > V
ENR
VIN>V
UVR
BFET MODE
Charge
H
X
L
H
L
Discharge
Discharge
X
9.3.5 EN/UVLO
As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET.
In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this
pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS2592xL by toggling this pin (H
→
L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current. For applications
where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO to GND.
9.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by R
ILIM
. After
start-up event and during normal operation, current limit is set to I
OL
(over-load current limit).
I
OL
=
0.7
+
3
´
10
–
5
´
R
ILIM
(
)
(3)
12
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When power dissipation in the internal MOSFET [P
D
= (V
VIN
-V
OUT
) × I
OUT
] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that I
OL
drops to I
SC
. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature.
0
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
40
50
60
Power (W)
Figure 25.
Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592
incorporates a fast-trip comparator, which shuts down the pass device very quickly when I
OUT
> I
FASTRIP
, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-
load current limit (I
FASTRIP
= 1.6 x I
OL
). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to I
OL
(see figure below).
VIN
VOUT
C2
C3
I_OUT
C1
C
Figure 27. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
Figure 26. Fast-Trip Current
Copyright © 2014, Texas Instruments Incorporated
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9.4 Device
Functional Modes
The TPS2592xx is
a hot-swap controller with integrated power switch that is used to manage
current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN
bus. When V
VIN
exceeds the undervoltage-lockout threshold (V
UVR
), the device samples the EN/UVLO pin. A high
level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if
connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)
will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below V
ENF
),
the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to
OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT
pin and GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current and input
voltage, ensuring that the adjustable overload current limit I
OL
is not exceeded and input voltage spikes are safely
clamped to V
OVC
level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (T
J
) exceeds T
SHDN
,
typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the
load from the supply. In the TPS2592xL, the output will remain disconnected (MOSFET open) until power to
device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain off
during a cooling period until device temperature falls below T
SHDN
– 10°C, after which it will attempt to restart.
This ON and OFF cycle will continue until fault is cleared.
14
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10 Application
and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application
Information
The TPA2592xx is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH
®
software may be used to generate a complete design. The WEBENCH
®
software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool
TPS2592 Design Calculator (SLUC571)
is available on web folder. This
10.2 Typical
Applications
10.2.1 Simple
2.1-A eFuse Protection for Set Top Boxes
V
IN
= 4.5 to 18 V
V
OUT,
I
OUT
< 1.7A
IN
OUT
*
C
VIN
0.1µF
R
1
1M
O
ꢀ
C
OUT
1µF
28m
O
ꢀ
EN/UVLO
**
BFET
ILIM
R2
dVdT
GND
TPS2592x
R
ILIM
45.3k
O
**Optional & only needed for external UVLO
*Optional & only for noise suppression
Figure 28.
Typical Application Schematic: Simple e-Fuse for STBs
10.2.1.1 Design
Requirements
Table 2. Design Parameters
DESIGN PARAMETER
Input voltage range, V
IN
EXAMPLE VALUE
12 V
Undervoltage lockout set point, V
(UV)
Load at Start-Up , R
L(SU)
Default: V
UVR
= 4.3 V
4
Ω
2.1 A
1 µF
85°C
Current limit, I
OL
= I
ILIM
Load capacitance , C
OUT
Maximum ambient temperatures , T
A
Copyright © 2014, Texas Instruments Incorporated
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10.2.1.2 Detailed
Design Procedure
The following design procedure can be used to select component values for the TPS2592xx.
10.2.1.2.1 Step
by Step Design Procedure
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.1.2.2 Programming
the Current-Limit Threshold: R
ILIM
Selection
The R
ILIM
resistor at the ILIM pin sets the over load current limit, this can be set using
Equation 4
.
I
– 0.7
ILIM
R
=
ILIM
-5
3 x 10
(4)
For I
OL
= I
ILIM
= 2.1 A, from equation 4, R
ILIM
= 45.3 k
Ω
, choose closest standard value resistor with 1%
tolerance.
10.2.1.2.3 Undervoltage
Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R
1
and R
2
as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
R
+
R
1
2
V
=
´
V
ENR
(UV)
R
1
(5)
Where V
ENR
= 1.4 V is enable voltage rising threshold.
Since R
1
and R
2
will leak the current from input supply (VIN), these resistors should be selected based on the
acceptable leakage current from input power supply (VIN). The current drawnby R
1
and R
2
from the power
supply {I
R12
= V
IN
/(R
1
+ R
2
)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I
R12
must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of V
UVR
= 4.3 V, select R
2
= OPEN, and R
1
= 1 M
Ω
. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN = 12 V. It has to be connected through R
1
= 1 M
Ω
only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
V
(PFAIL)
= 0.96 x V
UVR
(6)
Where V
UVR
is 4.3V, Power fail threshold set is : 4.1 V
10.2.1.2.4 Setting
Output Voltage Ramp Time (T
dVdT
)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C
dVdT
needed is calculated considering the two possible cases:
10.2.1.2.4.1 Case
1: Start-up without Load: Only Output Capacitance C
OUT
Draws Current During Start-up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
For TPS2592xx, the inrush current is determined as,
V
(IN)
I
=
C x
(OUT)
(INRUSH)
T
dVdT
(7)
16
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Power dissipation during start-up is:
P
=
0.5 x V
x I
(IN) (INRUSH)
D(INRUSH)
(8)
Equation 8
assumes that load does not draw any current until the output voltage has reached its final value.
10.2.1.2.4.2 Case
2: Start-up with Load: Output Capacitance C
OUT
and Load Draws Current During Start-up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load during start-up (R
L(SU)
), load current ramps up proportionally with increase in output voltage during
T
dVdT
time. The average power dissipation in the internal FET during charging time due to resistive load is given
by:
2
V
æ
ö
÷
÷
ø
1
6
(IN)
÷
x
÷
ç
P
=
ç
D(LOAD)
ç
è
R
L(SU)
(9)
(10)
(11)
Total power dissipated in the device during startup is:
P
=
P +
P
D(INRUSH) D(LOAD)
D(STARTUP)
Total current during startup is given by:
I
=
I
+ I
(t)
(STARTUP)
(INRUSH) L
If I
(STARTUP)
> I
OL
, the device limits the current to I
OL
and the current limited charging time is determined by:
é
ê
ê
ê
ê
ê
ê
ê
ë
ù
ö
æ
ç
ç
ç
ç
ç
ç
ç
ç
ç
ç
I
÷
ú
÷
÷
ú
÷
I
÷
I
(INRUSH)
ú
÷
OL
÷
ú
÷
÷
T
=
C
x R
L(SU)
x
–
1
+
LN
dVdT(Current-Limited)
OUT
V
I
ú
(IN)
÷
(INRUSH)
÷
–
ú
÷
OL
ç
÷
ú
÷
L(SU)
ø
û
R
ç
è
(12)
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
10000
T
A
= -40
o
C
T
A
= 25
o
C
T
A
= 85
o
C
1000
T
A
= 125
o
C
100
10
1
0.1
1
10
100
Power Dissipation (W)
D001
Figure 29.
Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor C
dVdT
= OPEN. Then, using
Equation 2
.
6
T
= 10
x 12 x
0 + 70 pF
=
840
m
s
)
(
dVdT
(13)
12
I
= 1
m
F x
= 15 mA
(INRUSH)
840
m
s
(14)
(15)
P
= 0.5 x 12 x 15 m = 90 mW
D(INRUSH)
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For 90 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time
T
dVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph
Figure 29
at
T
A
= 85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up
time without
any load on output.
Considering the start-up with load 4
Ω
, the additional power dissipation, when load is present during start up is
12 x 12
P
=
= 6 W
D(LOAD)
6
´
4
(16)
The total device power dissipation during start up is:
P
= 6
+
90 m = 6.09 W
D(STARTUP)
(17)
From thermal shutdown limit graph at T
A
= 85°C, the thermal shutdown time for 6.09 W is more than 100 ms. So
it is well within acceptable limits to use no external capacitor (C
dV/dT
) with start-up load of 4
Ω
.
If, due to large C
OUT
, there is a need to decrease the power loss during start-up, it can be done with increase of
C
dVdT
capacitor.
10.2.1.3 Support
Component Selection – C
VIN
C
VIN
is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001
μ
F to 0.1
μ
F is recommended for C
VIN
.
10.2.1.4 Application
Curves
Figure 30.
Output Ramp without Load on Output
Figure 31. Output Ramp with 4-
Ω
Load at Start Up
18
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10.3 Maximum
Device Power Dissipation Considerations
To prevent damage to the TPS2592x, it is necessary to keep internal power dissipation (P
D
) below the levels
specified in below Table. The power dissipation is defined as (P
D
= (V
IN
– V
OUT
) x I
OUT
).
MIN
MAX
40
UNIT
–40°C
≤
T
A
≤
+85°C
0°C
≤
T
A
≤
+85°C
Maximum Power Dissipation
W
50
During normal operation P
D
is low ( typically < ½ Watt) because the FET is fully on with low (V
IN
– V
OUT
).
However, during short circuit and surge protection the FET may be only partially on and (V
IN
– V
OUT
) can be high.
Example 1: Short Circuit on Output
→
V
IN
= 15 V, I
LIMIT
= 2.1 A. T
J
= –40°C
•
•
P
D
= 15 V x 2.1 A = 31.5 W
OK
→
(P
D
= 31.5 W) < (P
D_MAX
= 40 W)
Example 2: Short Circuit on Output
→
V
IN
= 18 V, I
LIMIT
= 2.1 A
•
•
•
P
D
= 18 V x 2.1 A = 37.8 W
OK at T
J
= 0°C
→
(P
D
= 37.8 W) < (P
D_MAX
at 0°C = 50 W)
OK at T
J
= –40°C
→
(P
D
= 37.8 W) > (P
D_MAX
at –40°C = 40 W)
Copyright © 2014, Texas Instruments Incorporated
19
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11 Power
Supply Recommendations
The device is designed for supply voltage range of 4.5 V
≤
V
IN
≤
18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1
μ
F is recommended. Power supply
should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient
Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the
Absolute Maximum Ratings
of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C
(IN)
= 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
L
(IN)
V
=
V x
I x
(IN) (LOAD)
SPIKE(Absolute)
C
(IN)
(18)
Where:
•
•
•
•
V
(IN)
is the nominal supply voltage
I
(LOAD)
is the load current,
L
(IN)
equals the effective inductance seen looking into the source
C
(IN)
is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
V
IN
V
OUT
IN
OUT
*
C
VIN
0.1µF
28m
O
ꢀ
R
1
C
OUT
EN/UVLO
dVdT
*
*
BFET
ILIM
R
2
C
dVdT
GND
TPS2592x
*Optional components for
transient suppression
R
ILIM
Figure 32.
Circuit Implementation with Optional Protection Components
11.2 Output
Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
20
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12 Layout
12.1 Layout
Guidelines
•
For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
•
•
•
High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be
a copper plane or island on the board.
Locate all support components: R
ILIM
, C
dVdT
and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the R
ILIM
and C
dVdT
components to the device should be as short as possible to reduce parasitic effects on
the current limit and soft start timing. These traces should not have any coupling to switching signals on the
board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
12.2 Layout
Example
Top layer
Bottom layer signal ground plane
Via to signal ground plane
Ground –
Bottom
layer
1
2
3
4
5
dV/dT
EN/UVLO
VIN
10
9
ILIM
BFET
8
OUT
OUT
OUT
7
6
VIN
VIN
VIN
VOUT
*
*
VIN
High Frequency
Bypass Capacitor
* Optional: Needed only to suppress the transients caused by inductive load switching
Figure 33.
Layout Example
版权
© 2014, Texas Instruments Incorporated
21
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13
器件和文档支持
13.1
器件支持
13.1.1
第三方产品免责声明
TI
发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何
TI
产品或服务一起的表示或认可。
13.2
相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表
3.
相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
TPS2592ZA
TPS2592ZL
13.3
商标
PowerPAD is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
13.5
术语表
这份术语表列出并解释术语、首字母缩略词和定义。
14
机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权
© 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
28-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2592ZADRCR
TPS2592ZADRCT
NRND
NRND
VSON
VSON
DRC
DRC
10
10
3000 RoHS
& Green
250 RoHS
& Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
2592ZA
2592ZA
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON – 1 mm max height
PLASTIC SMALL OUTLINE – NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
PACKAGE OUTLINE
DRC0010J
VSON – 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE – NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
EXAMPLE BOARD LAYOUT
DRC0010J
VSON – 1 mm max height
PLASTIC SMALL OUTLINE – NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE STENCIL DESIGN
DRC0010J
VSON – 1 mm max height
PLASTIC SMALL OUTLINE – NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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