Truesemi-TSA28N50M
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TSA28N50M
500V N-Channel MOSFET
General Description
Features
This Power MOSFET is produced using
Truesemi‘s
• 2
8
A,500V,Max.R
DS(on)
=0.
16
Ω
@
V
GS
=10V
• Low gate charge(typical
90nC)
• High ruggedness
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
advanced planar stripe DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand
high energy pulse in
the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction based on
half bridge
topology.
Absolute Maximum Ratings
T
J
=25
℃
unless otherwise specified
Symbol
V
DSS
Parameter
Value
500
Units
V
Drain-Source Voltage
Gate-Source Voltage
V
GS
±
30
V
T
C
= 25
℃
28
15
A
I
D
Drain Current
T
C
= 100
℃
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
A
I
DM
E
AS
I
AR
Pulsed Drain Current
110
A
Single Pulsed Avalanche Energy
Avalanche Current
1150
24
mJ
A
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
29
mJ
V/ns
W
4.5
290
Power Dissipation (T
C
= 25
℃
)
-Derate above
25
℃
P
D
2.33
-55 to +150
W/
℃
℃
T
J
, T
STG
T
L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
300
℃
1/8” from case for 5 seconds
Thermal Resistance
Characteristics
Symbol
Parameter
Typ.
Max.
Units
℃
/W
℃
/W
℃
/W
R
θ
JC
Thermal Resistance,Junction-to-Case
—
0.24
—
0.43
Thermal Resistance,Case-to-Sink Typ.
Thermal Resistance,Junction-to-Ambient
—
R
θ
CS
R
θ
JA
40
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Electrical Characteristics
T
J
=25
℃
unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
On Characteristics
V
GS
Gate Threshold Voltage
Static Drain-Source
On-Resistance
V
DS
= V
GS
, I
D
= 250 uA
㎂
2.0
—
—
4.0
V
R
DS(ON)
V
GS
= 10 V, I
D
= 12 A
0.1
4
0.
1
7
Ω
g
FS
Forward Transconductance
V
DS
=40V,I
D
=12A
(Note 4)
—
15
—
S
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 uA
㎂
500
—
—
—
—
V
Breakdown Voltage Temperature
Coefficient
△
BVDSS
/
△
TJ
ID = 250 uA, Referenced to
25
℃
0.5
V/
℃
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, T
J
= 125
℃
V
GS
= 30 V, V
DS
= 0 V
V
GS
=- 30 V, V
DS
= 0 V
—
—
—
—
—
—
—
—
1
uA
I
DSS
Zero Gate Voltage Drain Current
10
uA
Gate-Body Leakage Current,Forward
Gate-Body Leakage Current,Reverse
I
GSSF
I
GSSR
100
-100
nA
㎁
nA
㎁
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
—
—
—
6
500
520
55
—
—
—
pF
㎊
pF
㎊
pF
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Time
—
—
—
—
—
—
—
100
250
200
150
90
—
—
—
—
—
—
—
ns
V
DS
= 250 V, I
D
= 24 A,
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
ns
㎱
ns
㎱
ns
㎱
nC
R
G
= 25 Ω
(Note 4,5)
Q
g
Q
gs
Q
gd
V
DS
= 400 V,
I
D
= 24 A,
V
GS
= 10 V
22
nC
(Note 4,5)
45
nC
Source-Drain Diode Maximum Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Continuous Source-Drain Diode Forward Current
Pulsed Source-Drain Diode Forward Current
—
—
—
—
—
—
—
24
96
1.4
—
A
Source-Drain Diode Forward Voltage
I
S
= 24 A, V
GS
= 0 V
—
V
Reverse Recovery Time
Reverse Recovery Charge
400
7.2
ns
㎱
uC
I
S
= 24 A, V
GS
= 0 V
di
F
/dt = 100 A/
μs
(Note 4)
—
Q
rr
NOTES:
1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. L=3.4mH, I
AS
=24A, V
DD
=50V, R
G
=25
Ω,
Starting TJ=25
℃
3. I
SD
≤24A, di/dt ≤ 200A/us, V
DD
≤ BV
DSS
, Starting TJ = 25
℃
4. Pulse Test: Pulse width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially Independent of Operating Temperature Typical Characteristics
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Fig 12.
Gate Charge Test Circuit
& Waveform
V
GS
Same Type
50KΩ
as DUT
Q
g
12V
200nF
10V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
V
DS
90%
V
DS
V
DD
( 0.5 rated V
DS
)
R
G
10%
V
in
DUT
10V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
L
1
2
2
—-
E
AS
=
L
L
I
AS
V
DS
V
DD
BV
DSS
I
AS
I
D
R
G
I
D
(t)
DUT
V
DD
V
DS
(t)
10V
t
p
Time
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
DUT
+
V
DS
_
I
S
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
•
dv/dt controlled by
R
G
•
I
S
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
S
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
