Truesemi-TSD16N25M

TS

D

16N25

M  

25

0V N-Channel MOSFET  

General Description  

Features  

This Power MOSFET is produced using

 

Truesemi‘s  

advanced planar stripe DMOS technology.  

=10V  

•

16

A,

25

0V,Max.R  

This advanced technology has been especially tailored to  

minimize on-state resistance, provide superior switching  

performance, and withstand

 

high energy pulse in

 

the avalanche  

and commutation mode. These devices are well suited for high  

efficiency switched mode power supplies, active power factor  

correction based on

 

half bridge topology.  

Absolute maximum ratings

(

T

C

=25

°

C unless otherwise noted)  

Characteristic  

Symbol  

Rating  

Unit  

Drain-source voltage  

V

DSS  

250  

±

30  

16  

V

V

Gate-source voltage  

Drain current (DC)

*  

V

GSS  

T

C

=25

℃

 

T

C

=100

℃  

I

DM  

A

I

D  

7.2  

A

*

Drain current (Pulsed)  

Power dissipation  

64  

A

P

D  

I

AS  

E

AS  

I

AR  

E

AR  

T

J  

35  

W

A

Avalanche current (Single)  

Single pulsed avalanche energy  

Avalanche current (Repetitive)  

Repetitive avalanche energy  

Junction temperature  

②

②

①

①

16  

144  

mJ  

A

14  

13.9  

150  

-55~150  

mJ  

°

C  

Storage temperature range  

T

stg  

* Limited by maximum junction temperature  

Characteristic  

Symbol  

R

th(J-C)  

R

th(J-A)  

Typ.  

Max.  

3.57  

62.5  

Unit  

Junction-case  

–

–

Thermal  

resistance  

℃

/W  

Junction-ambient  

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1  

1

Electrical Characteristics

(T

C

=25

°

C unless otherwise noted)  

Characteristic  

Drain-source breakdown voltage  

Gate threshold voltage  

Drain-source cut-off current  

Gate leakage current  

Drain-source on-resistance  

Forward transfer conductance  

Input capacitance  

Symbol  

BV

DSS  

V

GS(th)  

I

DSS  

I

GSS  

R

DS(on)  

g

fs  

T

e

st Condition  

I

D

=250uA, V

GS

=0V  

I

D

=250uA, V

DS

=V

GS  

V

DS

=250

V

,

V

GS

=0V  

V

DS

=0

V

,

V

GS

=

±

30V  

V

GS

=10

V

,

I

D

=8.0A  

V

DS

=10

V

,

I

D

=8.0A  

Min. Typ. Max.

 

Unit  

250  

–

–

V

2.0  

–

–

4.0  

V

–

1

uA  

nA  

Ω

–

–

±

100  

④

④

–

0.22  

10.5  

1200  

150  

49  

0.2

5  

–

–

S

C

iss  

–

1275  

V

GS

=0

V

,

V

DS

=25V  

f=1 MHz  

pF  

ns  

nC  

Output capacitance  

C

oss  

C

rss  

–

170  

64  

–

Reverse transfer capacitance  

T

u

rn-on delay time  

–

t

d(on)  

t

r  

t

d(off)  

t

f  

–

15  

V

DD

=125

V

,

I

D

=16A  

R

G

=25

Ω

 

Rise time  

–

30  

–

T

u

rn-off delay time  

–

135  

40  

–

③

④

 

③

④  

Fall time  

–

–

T

o

tal gate charge  

Q

g  

–

22  

28  

–

V

DS

=200

V

,

V

GS

=10V  

I

D

=16A  

Gate-source charge  

Gate-drain charge  

Q

gs  

–

7.1  

5.9  

Q

gd  

–

–

Source-Drain Diode Ratings and Characteristics

(T

C

=25

°

C unless otherwise noted)  

Characteristic  

Symbol  

T

e

st Condition  

Min. Typ. Max. Unit  

Source current (DC)  

I

S  

I

SM  

V

SD  

t

rr  

–

–

–

–

–

–

16  

64  

1.4  

–

Integral reverse diode  

in the MOSFET  

A

Source current (Pulsed)  

Forward voltage  

①

④

–

V

GS

=0

V

,

I

S

=16A  

–

V

Reverse recovery time  

Reverse recovery charge  

208  

1.63  

ns  

uC  

I

S

=16A, V

GS

=0V  

dI

F

/dt=100A/us  

Q

rr  

–

Note ;  

①

Repetitive rating : Pulse width limited by maximum junction temperature  

②

L=3.0mH, I

AS

=16A, V

DD

=50

V

,

R

G

=25Ω, Starting T

J

=25

℃  

③

Pulse Test : Pulse width≤300us, Duty cycle≤2%  

④

Essentially independent of operating temperature  

2

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1  

Electrical Characteristic Curves  

Fig. 2 I

D

– V

GS  

Fig. 1 I

D

– V

DS  

:

–

Fig. 3 R

DS(on)

– I

D  

Fig. 4 I

S

– V

SD  

Fig. 5 Capacitance – V

DS  

Fig. 6 V

GS

– Q

G  

℃

3

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1  

Fig. 8 R

DS(on)

– T

J  

Fig. 7 V

DSS

– T

J  

ㅋ

C

C

Fig. 10 Safe Operating Area  

Fig. 9

 

I

D

– T

C  

`

*

4

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1  

Fig. 11 Gate Charge Test Circuit & Waveform  

Fig. 12 Resistive Switching

T

e

st Circuit & Waveform  

Fig. 13 E

AS

T

e

st Circuit & Waveform  

5

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1  

Fig. 14 Diode Reverse

 

Recovery Time Test Circuit & Waveform  

6

© 201

8

Truesemi Semiconductor

 

Corporation  

Ver.B1