Truesemi-TSD840MD
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TS
D
840M
D
500V N-Channel MOSFET
General Description
Features
This Power MOSFET is produced using
Truesemi‘s
•
8
.0A,500V,Max.R
=10V
advanced planar stripe DMOS technology.
DS(on)
=
0.95
Ω
@ V
GS
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand
high energy pulse in
the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction based on
half bridge
topology.
• 100% avalanche tested
• High ruggedness
• Fast switching
• Improved
dv/dt capability
D
G
S
TO-252
Absolute Maximum Ratings
T
J
=25
℃
unless otherwise specified
Symbol
V
DSS
Parameter
Value
Units
Drain-Source Voltage
Gate-Source Voltage
500
V
V
V
GS
30
±
T
C
= 25
℃
T
C
= 100
℃
(Note 1)
(Note 2)
(Note 1)
(Note 3)
8
.0*
5.
0
*
A
I
D
Drain Current
A
I
DM
E
AS
Pulsed Drain Current
3
2
A
280
Single Pulsed Avalanche Energy
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
mJ
mJ
V/ns
W
E
AR
6.3
dv/dt
4.5
1
0
0
Power Dissipation (T
C
= 25
℃
)
-Derate above 25
℃
P
D
T
J
, T
STG
T
L
0.36
W/
℃
℃
Operating and Storage Temperature Range
-55 to +150
Maximum lead temperature for soldering purposes,
300
℃
1/8” from case for 5 seconds
* Drain current limited by maximum junction temperature.
Thermal Resistance
Characteristics
Symbol
Parameter
Value
0.9
Units
℃
/W
℃
/W
℃
/W
R
θ
JC
Thermal Resistance,Junction-to-Case
Thermal Resistance,Case-to-Sink Typ.
—
R
θ
CS
R
θ
JA
Thermal Resistance,Junction-to-Ambient
62.5
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Electrical Characteristics
T
J
=25
℃
unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
On Characteristics
V
GS
(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 uA
㎂
2
.0
—
4
.0
V
Static Drain-Source
R
DS(ON)
V
GS
= 10 V, I
D
= 4.5 A
—
0.95
Ω
0.88
On-Resistance
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 uA
㎂
500
—
—
—
—
V
Breakdown Voltage Temperature
Coefficient
△
BVDSS
/
△
TJ
ID = 250 uA, Referenced to
25
℃
—
V/
℃
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, T
J
= 125
℃
V
GS
= 30 V, V
DS
= 0 V
V
GS
=- 30 V, V
DS
= 0 V
—
—
—
—
—
—
—
—
1
uA
I
DSS
Zero Gate Voltage Drain Current
10
uA
Gate-Body Leakage Current,Forward
Gate-Body Leakage Current,Reverse
I
GSSF
I
GSSR
100
-100
nA
㎁
nA
㎁
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
—
—
—
1
4
00
210
80
—
—
—
pF
㎊
pF
㎊
pF
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Time
—
—
—
—
—
—
—
1
5
6
2
93
48
26
4
—
—
—
—
—
—
—
ns
V
DS
= 250 V, I
D
=
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
ns
㎱
ns
㎱
ns
㎱
nC
8
.0A, R
G
= 25 Ω
(Note 4,5)
Q
g
Q
gs
Q
gd
V
DS
= 400 V,
I
D
=
8
.0A,
V
GS
= 10 V
nC
(Note 4,5)
13
nC
Source-Drain Diode Maximum Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Continuous Source-Drain Diode Forward Current
Pulsed Source-Drain Diode Forward Current
—
—
—
—
—
—
—
8
.0
24
.0
1.4
—
A
Source-Drain Diode Forward Voltage
I
S
=
3
.0 A, V
GS
= 0 V
—
V
Reverse Recovery Time
Reverse Recovery Charge
34
0
3
ns
㎱
uC
I
S
=
8
.0A, V
GS
= 0 V
di
F
/dt = 100 A/
μs
(Note 4)
—
Q
rr
NOTES:
1.
Repetitive Rating: Pulse width limited by maximum junction temperature
2.
L=
5
mH, I
AS
=
10.6
A, V
DD
=50V,
V
G
=
10V
,
Starting TJ=25
℃
3.
I
SD
≤
8
.0A, di/dt ≤ 200A/us, V
DD
≤ BV
DSS
, Starting TJ = 25
℃
4.
Pulse Test: Pulse width ≤ 300us, Duty Cycle ≤ 2%
5.
Essentially Independent of Operating Temperature Typical
Characteristics
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Electrical Characteristics Curves
Fig. 1 Typical Output Characteristics
Fig. 2 Typical Output Characteristics
Fig.3 On-Resistance Variation with Drain
Fig. 4 Body Diode Forward Voltage
Variation with Source Current and
T
e
mperature
and Gate
Current
Voltage
Fig. 5 Typical Capacitance Characteristics
Fig. 6 Typical
T
o
tal Gate Charge Characteristics
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Fig. 8 On-Resistance Variation vs.
T
e
mperature
Fig. 7 Breakdown Voltage Variation vs.
T
e
mperature
Fig. 9 Maximum Drain Current vs. Case
T
e
mperature
Fig. 10 Maximum Safe Operating Area
Fig. 11
T
r
ansient Thermal Impedance
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Fig. 12 Gate Charge Test Circuit & Waveform
Fig. 13 Resistive Switching Test Circuit & Waveform
Fig. 14 E
AS
T
e
st Circuit & Waveform
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
Fig. 15 Diode Reverse
Recovery Time
T
e
st Circuit & Waveform
© 201
8
Truesemi Semiconductor
Corporation
Ver.B1
