Truesemi-TSF12N65M
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TSP12N65M/TSF12N65M
650V N-Channel MOSFET
General Description
Features
This Power MOSFET is produced using
Truesemi‘s
advanced planar stripe DMOS technology.
• 12A,650V,Max.R
DS(on)
=0.75 Ω @ V
GS
=10V
• Low gate charge(typical
52nC)
• High ruggedness
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand
high energy pulse in
the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction based on
half bridge
topology.
Absolute Maximum Ratings
T
C
=25
℃
unless otherwise specified
TSP12N65M TSF12N65M
Symbol
Parameter
Units
V
V
DSS
Drain-Source Voltage
Gate-Source Voltage
650
V
GS
V
± 30
T
C
= 25
℃
T
C
= 100
℃
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
A
12
7.4
48
12*
7.4*
48*
I
D
Drain Current
A
I
DM
E
AS
I
AR
Pulsed Drain Current
A
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
865
12
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
mJ
V/ns
W
23.1
4.5
231
54
Power Dissipation (T
C
= 25
℃
)
-Derate above
25
℃
P
D
T
J
, T
STG
T
L
W/
℃
℃
1.85
0.43
Operating and Storage Temperature Range
-55 to +150
Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
℃
300
* Drain current limited by maximum junction temperature.
Thermal Resistance
Characteristics
TSP12N65M TSF12N65M
Symbol
Parameter
Units
R
θJC
Thermal Resistance,Junction-to-Case
0.54
0.5
2.33
—
℃
/W
Thermal Resistance,Case-to-Sink Typ.
Thermal Resistance,Junction-to-Ambient
℃
/W
℃
/W
R
θCS
R
θJA
62.5
62.5
© 201
8
Truesemi Semiconductor
Corporation
Ver.C1
Electrical Characteristics
T
C
=25
℃
unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
On Characteristics
V
GS
V
DS
= V
GS
, I
D
= 250 uA
㎂
Gate Threshold Voltage
3.0
—
—
5.0
V
Static Drain-Source
On-Resistance
R
DS(ON)
V
GS
= 10 V, I
D
= 6A
0.63
0.75
Ω
Off Characteristics
BV
DSS
V
GS
= 0 V, I
D
= 250 uA
㎂
Drain-Source Breakdown Voltage
650
—
—
—
—
V
Breakdown Voltage Temperature
Coefficient
△
BVDSS
/
△
TJ
ID = 250 uA, Referenced to 25
℃
0.7
V/
℃
V
DS
= 650 V, V
GS
= 0 V
V
DS
= 520 V, T
J
= 125
℃
V
GS
= 30 V, V
DS
= 0 V
V
GS
=- 30 V, V
DS
= 0 V
—
—
—
—
—
—
—
—
1
uA
I
DSS
Zero Gate Voltage Drain Current
10
uA
I
GSSF
I
GSSR
Gate-Body Leakage Current,Forward
Gate-Body Leakage Current,Reverse
100
-100
nA
㎁
nA
㎁
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
—
—
—
1850
180
20
—
—
—
pF
㎊
pF
㎊
pF
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Time
—
—
—
—
—
—
—
30
90
—
—
—
—
—
—
—
ns
V
DS
= 325 V, I
D
= 12A,
R
G
= 25 Ω
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
ns
㎱
ns
㎱
ns
㎱
nC
(Note 4,5)
140
90
Q
g
Q
gs
Q
gd
52
V
DS
= 520 V,
I
D
= 12A,
V
GS
= 10 V
8.5
20
nC
(Note 4,5)
nC
Source-Drain Diode Maximum Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Continuous Source-Drain Diode Forward Current
Pulsed Source-Drain Diode Forward Current
—
—
—
—
—
—
12
48
1.4
—
A
I
S
= 12 A, V
GS
= 0 V
Source-Drain Diode Forward Voltage
Reverse Recovery Time
—
V
430
ns
㎱
I
S
=12A, V
GS
= 0 V
di
F
/dt = 100 A/
μ
s
(Note 4)
Reverse Recovery Charge
—
5.0
—
uC
Q
rr
NOTES:
1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. L=11mH, I
AS
=12A, V
DD
=50V, R
G
=25
Ω,
Starting TJ=25
℃
3. I
SD
≤12A, di/dt ≤ 200A/us, V
DD
≤ BV
DSS
, Starting TJ = 25
℃
4. Pulse Test: Pulse width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially Independent of Operating Temperature Typical Characteristics
© 201
8
Truesemi Semiconductor
Corporation
Ver.C1
Fig 12.
Gate Charge Test Circuit
& Waveform
V
GS
Same Type
50K
Ω
as DUT
Q
g
12V
200nF
10V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
V
DS
90%
V
DS
V
DD
R
G
( 0.5 rated V
DS
)
10%
V
in
DUT
10V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
L
1
2
2
—-
E
AS
=
L
L
I
AS
V
DS
V
DD
BV
DSS
I
AS
I
D
R
G
I
D
(t)
DUT
V
DD
V
DS
(t)
10V
t
p
Time
© 201
8
Truesemi Semiconductor
Corporation
Ver.C1
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
DUT
+
V
DS
_
I
S
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
S
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
S
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
© 201
8
Truesemi Semiconductor
Corporation
Ver.C1
