UMW-Youtai-Semiconductor-Co—Ltd–IRF2804PBF-UMW
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R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
Features
•
•
V
DS
(V) =40V
I
D
=75A (
V
G
S
= 10V)
•
•
R
DS(ON)
<2.0m
Ω
(V
GS
=10V)
R
DS(ON)
<2.3m
Ω
(V
GS
=4.5V)
D
S
G
Absolute Maximum Ratings
Parameter
Max.
Units
I
I
I
@ T
C
= 25°C
@ T
C
= 100°C
@ T
C
= 25°C
270
190
75
A
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (See Fig. 9)
D
D
D
(Package Limited)
Continuous Drain Current, V
GS
@ 10V
I
DM
1080
300
Pulsed Drain Current
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
Gate-to-Source Voltage
2.0
± 20
W/°C
V
V
GS
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy Tested Value
540
1160
mJ
E
AS
(tested)
Avalanche Current
I
AR
See Fig.12a,12b,15,16
A
mJ
°C
Repetitive Avalanche Energy
E
AR
T
J
Operating Junction and
-55 to
+ 175
T
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θ
JC
R
θ
CS
R
θ
JA
R
θ
JA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
°C/W
0.50
0.50
Junction-to-Ambient
62
40
Junction-to-Ambient (PCB Mount, steady state)
UTD Semiconductor Co.,Limited
1
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
Conditions
V
GS
= 0V, I
D
= 250µA
V/°C Reference
to 25°C, I
D
= 1mA
V
(BR)DSS
∆Β
V
DSS
/
∆
T
J
R
DS(on)
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
40
V
0.031
1.5
2.0
2.3
4.0
V
GS
= 10V, I
D
= 75A
V
GS
= 10V, I
D
= 75A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 10V, I
D
= 75A
Ω
m
R
DS(on)
1.8
V
GS(th)
2.0
130
V
S
gfs
Forward Transconductance
I
DSS
Drain-to-Source Leakage Current
20
250
200
-200
240
62
µA V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA V
GS
= 20V
V
GS
= -20V
Q
g
Q
gs
Q
gd
t
d(on)
t
r
160
41
nC I
D
= 75A
V
DS
= 32V
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
66
99
V
GS
= 10V
DD
= 20V
13
ns
V
Rise Time
120
130
130
4.5
I
D
= 75A
t
d(off)
t
f
Turn-Off Delay Time
R
G
= 2.5
Ω
V
GS
= 10V
Fall Time
L
D
D
Internal Drain Inductance
nH Between
lead,
6mm (0.25in.)
from package
G
L
S
Internal Source Inductance
7.5
S
and center of die contact
pF V
GS
= 0V
DS
= 25V
ƒ = 1.0MHz, See Fig. 5
C
iss
Input Capacitance
6450
1690
840
C
oss
C
rss
Output Capacitance
V
Reverse Transfer Capacitance
Output Capacitance
C
oss
C
oss
C
oss
eff.
I
S
5350
1520
2210
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
GS
= 0V,
V
DS
= 32V,
ƒ = 1.0MHz
GS
= 0V, V
DS
= 0V to 32V
Output Capacitance
V
Effective Output Capacitance
Continuous Source Current
V
D
270
MOSFET symbol
(Body Diode)
Pulsed Source Current
A
V
showing the
integral reverse
I
SM
G
1080
S
(Body Diode)
Diode Forward Voltage
p-n junction diode.
V
SD
T =
25°C, I
= 75A, V
= 0V
1.3
J
S
GS
t
rr
Q
rr
T =
25°C, I
= 75A, V
DD
= 20V
J F
di/dt = 100A/µs
Reverse Recovery Time
Reverse Recovery Charge
56
67
84
100
ns
nC
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Forward Turn-On Time
Notes:
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C,
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
L=0.24mH, R
G
= 25
Ω
, I
AS
= 75A, V
GS
=10V.
This is applied to D
2
Pak, when mounted on 1″ square PCB
( FR-4 or G-10 Material ).
For recommended footprint and
soldering techniques refer to application note #AN-994.
Max R
DS(on)
for D
2
Pak and TO-262 (SMD) devices.
Part not recommended for use above this value.
I
SD
≤
75A, di/dt
≤
220A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C.
,
Pulse width
≤
1.0ms; duty cycle
≤
2%.
ꢀ
C
oss
eff. is a fixed capacitance that gives the same
TO-220 device will have an Rth value of 0.45°C/W.
charging time as C
oss
while V
DS
is rising from 0 to 80%
V
DSS
.
UTD Semiconductor Co.,Limited
2
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
10000
1000
100
10
10000
1000
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
V
GS
TOP
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 4.5V
5.0V
BOTTOM 4.5V
4.5V
20µs PULSE WIDTH
4.5V
20µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
10
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
300
250
200
150
100
50
T
J
= 25°C
J
T
= 175°C
J
T
= 175°C
T
= 25°C
J
V
= 10V
V
= 10V
DS
20µs PULSE WIDTH
DS
20µs PULSE WIDTH
1
0
4.0
5.0
6.0
7.0
8.0
9.0
0
40
80
120
160
200
V
, Gate-to-Source Voltage (V)
I ,
Drain-to-Source Current (A)
GS
D
Fig 3.
Typical Transfer Characteristics
Fig 4.
Typical Forward Transconductance
vs. Drain Current
UTD Semiconductor Co.,Limited
3
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
20
16
12
8
12000
10000
8000
6000
4000
2000
V
C
= 0V,
f = 1 MHZ
SHORTED
I =
75A
D
GS
= C
+ C
, C
i
s
s
gs
gd
ds
V
= 32V
DS
C
= C
rss
gd
VDS= 20V
VDS= 8.0V
C
= C
+ C
oss
ds
gd
Ciss
4
Coss
Crss
0
0
0
40
80
120
160
200
240
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6.
Typical Gate Charge vs.
Fig 5.
Typical Capacitance vs.
Gate-to-Sourc
e
V
oltage
Drain-to-Sourc
e
V
oltage
10000
1000.0
100.0
10.0
1.0
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
1000
100
10
100µsec
1msec
10msec
T
= 25°C
1.0
Tc = 25°C
Tj = 175°C
Single Pulse
J
V
= 0V
GS
0.1
1
0.2
0.6
SD
1.4
1.8
2.2
0
1
10
100
V
, Source-toDrain Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
UTD Semiconductor Co.,Limited
4
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
2.0
1.5
1.0
0.5
300
250
200
150
100
50
I
= 75A
D
V
= 10V
GS
Limited By Package
0
-60 -40 -20
T
0
20 40 60 80
100 120 140 160 180
25
50
75
100
125
150
175
, Junction Temperature (°C)
J
T
, Case Temperature (°C)
C
Fig 10.
Normalized On-Resistance
Fig 9.
Maximum Drain Current vs.
vs
.
T
emperature
Cas
e
T
emperature
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-008
1E-007
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
UTD Semiconductor Co.,Limited
5
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
15V
1200
1000
800
600
400
200
0
I
D
TOP
31A
53A
DRIVER
+
L
V
DS
BOTTOM 75A
D.U.T
AS
R
G
V
DD
–
I
A
V
20V
GS
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
4.0
3.0
2.0
1.0
V
G
I
= 250µA
D
Charge
Fig 13a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
-75 -50 -25
0
25 50 75
100 125 150 175
, Temperature ( °C )
V
GS
T
J
3mA
I
I
D
G
Current Sampling Resistors
Fig 14.
Threshold Voltage vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
UTD Semiconductor Co.,Limited
6
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆
Tj = 25°C due to
avalanche losses
0.01
0.05
0.10
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
600
TOP
Single Pulse
1. Avalanche failures assumption:
BOTTOM 10%
Duty Cycle
500
400
300
200
100
0
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
I
= 75A
D
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 16.
Maximum Avalanche Energy
vs
.
T
emperature
UTD Semiconductor Co.,Limited
7
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
Package Demensions
TO 220
Symbol
Dimensions
Symbol
Dimensions
(mm)
Symbol
Dimensions
（
mm
）
10.0±0.3
8.0±0.2
0.94±0.1
8.7±0.1
15.6±0.4
13.2±0.2
4.5±0.2
(mm)
13.2±0.4
1.38±0.1
1.28±0.1
2.54(typ)
2.4±0.3
A
C1
D
D1
E
F
H
1.3±0.2
0.8±0.2
0.5±0.1
10.0±0.3
2.8±0.1
3.6±0.1
3.1±0.2
L
M
M1
N
P
Q
A1
A2
A3
B
B1
C
9.15±0.25
K
UTD Semiconductor Co.,Limited
8
R
IRF2804
UMW
4
0 V
N-Channel
MOSFET
Marking
Ordering information
Package
Deliverymode
Tube and box
Baseqty
Order code
UMW IRF2804P
B
F
TO-220
1000
UTD Semiconductor Co.,Limited
9
