UMW-Youtai-Semiconductor-Co—Ltd–IRLR3410TR
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R
UMW
I
RLR
3
410
Description
D
The D-PAK is designed for surface mounting
using vapor
phase, infrared, or
wave soldering
techniques.
G
Power dissipation
levels up
to 1.5 watts are pos-
sible in typical surface mount applications.
S
Features
V
DS
(V) = 100V
I
D
= 17A (V
GS
= 10V)
R
DS(ON)
=105m
Ω
(V
GS
= 10V)
Absolute Maximum Ratings
Parameter
Max.
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
ꢀ
17
12
60
A
P
D
@T
C
= 25°C
Power Dissipation
79
W
W/°C
V
Linear Derating Factor
0.53
± 16
150
V
GS
E
AS
I
AR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
ꢀ
Avalanche Current
ꢀ
mJ
A
9.0
E
AR
dv/dt
T
J
Repetitive Avalanche Energy
ꢀ
Peak Diode Recovery dv/dt
Operating Junction and
7.9
mJ
V/ns
5.0
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
1.9
Units
R
θ
JC
R
θ
JA
R
θ
JA
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
50
°C/W
110
1
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
100 –––
–––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
V
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
––– 0.122
––– V/°C
Reference to 25°C, I
D
= 1mA
––– ––– 105
V
GS
= 10V, I
D
= 10A
V
GS
= 5.0V, I
D
= 10A
V
GS
= 4.0V, I
D
= 9.0A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 25V, I
D
= 9.0A
ꢀ
R
DS(on)
Static Drain-to-Source On-Resistance
––– ––– 125
mW
––– ––– 155
V
GS(th)
g
fs
Gate Threshold Voltage
1.0
7.7
––– 2.0
––– –––
V
S
Forward Transconductance
––– ––– 25
––– –––
250
––– –––
100
––– –––
-100
––– ––– 34
––– ––– 4.8
––– ––– 20
V
DS
= 100V, V
GS
= 0V
I
DSS
I
GSS
Drain-to-Source Leakage Current
µA
V
DS
= 80V, V
GS
= 0V, T
J
= 150°C
V
GS
= 16V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
V
GS
= -16V
Q
g
I
D
= 9.0A
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC V
DS
= 80V
V
GS
= 5.0V, See Fig. 6 and 13
ꢀ
–––
–––
–––
–––
7.2 –––
53 –––
30 –––
26 –––
V
DD
= 50V
I
D
= 9.0A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 6.0
Ω,
V
GS
= 5.0V
R
D
= 5.5
Ω,
See Fig. 10
ꢀ
Between lead,
L
D
L
S
Internal Drain Inductance
Internal Source Inductance
4.5
nH
6mm (0.25in.)
from package
––– 7.5 –––
and center of die contact
V
GS
= 0V
C
iss
C
oss
C
rss
Input Capacitance
––– 800
–––
––– 160
–––
Output Capacitance
pF
V
DS
= 25V
Reverse Transfer Capacitance
–––
90 –––
ƒ = 1.0MHz, See Fig. 5
ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
I
S
17
60
––– –––
––– –––
showing the
A
I
SM
Pulsed Source Current
(Body Diode)
ꢀ
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 9.0A, V
GS
= 0V
T
J
= 25°C, I
F
=9.0A
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 140 210
V
ns
Q
rr
t
on
––– 740
1100 nC di/dt
= 100A/µs
ꢀ
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating;
pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
= 25V, starting T
J
= 25°C, L = 3.1mH
R
G
= 25
Ω
, I
AS
= 9.0A. (See Figure 12)
Pulse width
≤
300µs; duty cycle
≤
2%
ꢀ
Uses IRL530N data and test conditions
I
SD
≤
9.0A, di/dt
≤
540A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
,
This is applied for I-PAK, L
S
of D-PAK is measured between lead and
center of
die contact
2
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
100
10
1
100
10
1
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 175°C
T
= 25°C
J
J
0.1
0.1
0.1
A
A
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2.
Typical Output Characteristics
Fig 1.
Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
I
= 15A
D
T
J
= 25°C
T
J
= 175°C
10
1
V
D
S
= 50V
20µs PULSE WIDTH
1
0
A
V
= 10V
GS
0.1
A
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
2
3
4
5
6
7
8
9
T ,
Junction Temperature (°C)
V
GS
, Gate-to-Source Voltage (V)
J
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
1400
1200
1000
800
600
400
200
0
15
12
9
V
C
C
C
= 0V,
f = 1MHz
I
= 9.0A
D
GS
iss
rss
oss
= C
+ C
,
C
SHORTED
V
V
V
= 80V
= 50V
= 20V
gs
gd
ds
DS
DS
DS
= C
gd
= C
+ C
ds
gd
C
C
iss
6
oss
C
rss
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
10
20
30
40
50
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance Vs.
Fig 6.
Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
100
10
1
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T =
175°C
J
100
10
1
10µs
T =
25°C
J
100µs
1ms
T
T
= 25°C
C
J
= 175°C
Single Pulse
V
= 0V
10ms
GS
A
A
0.4
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7.
Typical Source-Drain Diode
Fig 8.
Maximum Safe Operating Area
Forward Voltage
4
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
20
15
10
5
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
5.0V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
C
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
2
DM
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D =
t /
t
1
2. Peak T
=
P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
350
300
250
200
150
100
50
I
D
TOP
3.7A
6.4A
BOTTOM 9.0A
15V
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
–
I
A
AS
10V
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
= 25V
50
DD
0
A
175
25
75
100
125
150
Starting T
, Junction Temperature (°C)
V
(BR)DSS
J
t
p
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Same Type as D.U.
T
.
Fig 12b.
Unclamped Inductive Waveforms
50K
Ω
.2
µ
F
12V
.3
µ
F
Q
G
+
5.0 V
V
DS
D.U.
T
.
–
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a.
Basic Gate Charge Waveform
Fig 13b.
Gate Charge Test Circuit
6
UTD Semiconductor Co.,Limited
R
UMW
I
RLR
3
410
Package Mechanical Data
TO-252
A
B2
Dimensions
C2
V 1
Ref.
Millimeters
Typ.
Inches
Typ.
Min.
2.10
0
Max.
Min.
0.083
0
Max.
0.098
0.004
0.034
0.216
0.024
0.023
0.248
2.50
0.10
0.86
5.48
0.60
0.58
6.30
A
A2
B
0.66
5.18
0.40
0.44
5.90
0.026
0.202
0.016
0.017
0.232
B2
C
C2
D
C
B
G
5.30REF
0.209REF
D1
E
DETAIL A
6.40
4.63
4.47
9.50
1.09
1.35
6.80
0.252
0.182
0.176
0.374
0.043
0.053
0.268
V1
E1
G
4.67
10.70
1.21
0.184
0.421
0.048
0.065
V 2
H
L
V1
1.65
L2
V1
V2
E1
L2
7°
7°
DETAIL A
0°
6°
0°
6°
Ordering information
Order code
Package
Baseqty
2500
Delivery mode
Tape and reel
UMW IRLR3410TR
TO-252
7
UTD Semiconductor Co.,Limited
