UMW-Youtai-Semiconductor-Co—Ltd–NTD20N06LT4G
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R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
Typical Applications
D
•
Power Supplies
•
Converters
•
Power Motor Controls
G
•
Bridge Circuits
S
Features
V
DS
60V
20A
I
D
(at V
GS
=10V)
R
DS(ON)
(at V
GS
=
4.5
V)
< 3
5
m
Ω
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol
Value
60
Unit
Vdc
Vdc
Vdc
Drain−to−Source Voltage
V
DSS
DGR
Drain−to−Gate Voltage (R
= 10 M
W
)
V
60
GS
Continuous
Non−repetitive (t
v
10 ms)
V
V
15
20
Gate−to−Source V
oltage
GS
GS
p
Continuous @ T
= 25
°
C
A
I
I
20
10
60
Adc
Apk
D
D
Continuous @ T
= 100
°
C
Drain Current
A
Single Pulse (t
v
10
m
s)
p
I
DM
T
o
tal Power Dissipation @ T
= 25
°
C
60
W
W/
°
C
W
A
°
Derate above 25 C
0.40
1.88
1.36
P
D
A
W
A
−
5
5 to
+175
Operating and Storage
T
e
mperature Range
Single Pulse Drain−to−Source Avalanche
T , T
°
C
J
stg
Energy − Starting T
= 25
°
C
J
E
R
128
2.5
mJ
AS
(V =
25 Vdc, V
= 5.0 Vdc,
DD
GS
L = 1.0 mH, I
(pk) = 16 A, V
= 60 Vdc)
L
DS
Junction−to−Case
q
JC
C/W
°
80
R
R
Thermal Resistance
q
q
JA
JA
110
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
L
260
°
C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
1. When
surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in
).
2. When
surface mounted to an FR4 board using recommended pad size,
2
(Cu Area 0.412 in
).
1
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage (Note 3)
V
Vdc
(BR)DSS
(V =
0 Vdc, I
= 250
m
Adc)
T
e
mperature Coefficient (Positive)
60
−
71.3
71.2
−
−
GS
D
mV/
°
C
m
Adc
I
DSS
−
−
−
−
1.0
10
DS
GS
(V =
60 Vdc, V
= 0 Vdc, T
= 150
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V
= 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage (Note 3)
V
GS(th)
(V =
V ,
I =
250
m
Adc)
Threshold
T
e
mperature Coefficient (Negative)
1.0
−
1.6
4.6
2.0
−
DS
GS
D
mV/
°
C
m
W
R
V
DS(on)
−
45
(V =
4.5
Vdc, I
= 10 Adc)
3
5
GS
D
Static Drain−to−Source On−Resistance (Note 3)
(V =
5.0 Vdc, I
= 20 Adc)
Vdc
DS(on)
−
−
0.81
0.72
1.66
−
GS
D
(V =
5.0 Vdc, I
= 10 Adc, T
= 150
°
C)
GS
D
J
Forward Transconductance (Note 3) (V
= 4.0 Vdc, I
= 10 Adc)
g
FS
−
17.5
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
707
224
72
990
320
105
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
C
oss
f = 1.0 MHz)
C
rss
t
−
−
−
−
−
−
−
9.6
98
20
200
50
120
32
−
ns
d(on)
(V =
30 Vdc, I
= 20 Adc,
DD
D
t
r
V
GS
= 5.0 Vdc,
Turn−Off Delay Time
Fall Time
t
25
d(off)
R
G
t
f
62
Q
T
Q
1
Q
2
16.6
5.5
8.5
nC
Gate Charge
(V =
48 Vdc, I
= 20 Adc,
DS
D
V
GS
= 5.0 Vdc) (Note 3)
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I =
20 Adc, V
= 0 Vdc) (Note 3)
V
SD
−
−
0.97
0.85
1.2
−
Vdc
ns
S
GS
(I =
20 Adc, V
= 0 Vdc, T
= 150
°
C)
S
GS
J
t
rr
−
−
−
−
42
30
−
−
−
−
Reverse Recovery Time
(I =
20 Adc, V
= 0 Vdc,
S
GS
t
a
dI /dt
= 100 A/
m
s) (Note 3)
S
t
b
12
Reverse Recovery Stored Charge
Q
0.066
m
C
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
40
40
30
V
GS
= 10 V
V
≥
10 V
DS
4.5 V
4 V
4.5
V
30
20
10
6 V
20
10
3.5 V
3 V
T =
25
°
C
J
T =
100
°
C
J
T =
−55
°
C
J
0
0
0
1
2
3
4
5
1.6
2.4
3.2
4
4.8
5.6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.085
0.075
0.065
0.055
0.045
0.035
0.025
0.015
0.085
0.075
0.065
0.055
V
=
4.5
V
GS
V
GS
= 10 V
T =
100
°
C
J
T =
100
°
C
J
T =
25
°
C
J
0.045
0.035
0.025
0.015
T =
25
°
C
J
T =
−55
°
C
J
T =
−55
°
C
J
0
10
20
30
40
0
10
20
30
40
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
1000
2
1.8
1.6
V
GS
= 0 V
I
= 10 A
D
V
=
4.5
V
GS
T =
150
°
C
J
1.4
1.2
1
100
10
T =
100
°
C
J
0.8
0.6
−50 −25
0
25
50
75 100
125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
3
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
Switching behavior
is most easily modeled and
charge controlled. The lengths of various switching
intervals (t) are determined by how fast the FET in-
put capacitance can be charged by current from the
generator.
The capacitance (C
iss
) is read from the capacitance
curve at a voltage corresponding to the off
−
state
condition when calculating t
d(on)
and is read at a vol-
tage corresponding to the on
−
state when calculating
t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOS-
FET source lead, inside the package and in the cir-
cuit wiring which is common to both the drain and
gate current paths, produces a voltage at the source
which reduces the gate drive current. The voltage is
determined by Ldi/dt, but since di/dt is a function of
drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal re-
sistance is difficult to measure and, consequently, is
not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit ele-
ments. If
the parasitics were not present, the slope
of the curves would maintain a value of unity regard-
less of the switching speed. The circuit used to obta-
in the data is constructed to minimize common in-
ductance in the drain and gate circuit loops and is
believed readily achievable with board mounted
components. Most
power electronic loads are induc-
tive; the data in the figure is taken with a resistive lo-
ad, which approximates an optimally snubbed induc-
tive load.
Power MOSFETs may be safely operated
into an inductive load; however, snubbing reduces
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capaci-
tance varies greatly with applied voltage. According-
ly, gate charge data is used.
In most cases, a satis-
factory estimate of average input current (I
be made from a rudimentary analysis of the drive cir-
cuit so that
) can
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching
a resistive load, V
remains virtually constant at a
level known as the plateau voltage, V
re, rise and fall times may be approximated by the
following:
GS
. Therefo-
SGP
t =
Q x
R /(V
−
V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where V
= the gate drive voltage, which varies
GG
from zero to V
R =
the gate drive resistance
GG
G
and Q
and V
are read from the gate charge cur-
2
GSP
ve.During the turn
−
on and turn
−
off delay times, gate
current is not constant.
The simplest calculation
uses appropriate values from the capacitance curves
in a standard equation for voltage change in an RC
network. The
equations are:
t
t
= R
C In
[V /(V
−
V
)]
GSP
d(on)
G
iss
GG
GG
= R
C In
(V /V
)
GG GSP
d(off)
G
iss
switching losses.
2400
2000
1600
1200
V
= 0 V
V
GS
= 0 V
DS
T =
25
°
C
J
C
iss
C
rss
C
iss
800
400
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
1000
100
6
V
= 30 V
DS
I
D
= 20 A
Q
T
V
=
4.5
V
GS
V
GS
4
Q
t
r
Q
2
1
t
f
3
2
t
d(off)
10
1
t
d(on)
1
0
I
= 20 A
D
T =
25
°
C
J
0
4
8
12
16
20
1
10
100
Q ,
TOTAL GATE CHARGE (nC)
G
R ,
GATE RESISTANCE (OHMS)
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
20
V
GS
= 0 V
T =
25
°
C
J
16
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal Re-
sistance
−
General Data and Its Use.”
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the transiti-
on time (t
r
,t
f
) do not exceed 10 s. In addition the total po-
wer averaged over a complete switching cycle must not
exceed (T
J(MAX)
−
T
C
)/(R
JC
).
reliable operation, the stored energy from circuit inductan-
ce dissipated in the transistor while in avalanche must be
less than the rated limit and adjusted for operating conditi-
ons differing from those specified. Although industry practi-
ce is to rate in terms of energy, avalanche energy capabili-
ty is not a constant. The energy rating decreases non
−
line-
arly with an increase of peak current in avalanche and pe-
ak junction temperature.
Although many E
−
FETs can withstand the stress of dra-
in
−
to
−
source avalanche at currents up to rated pulsed cur-
rent (I
DM
), the energy rating is specified at rated continu-
ous current (I
D
), in accordance with industry custom. The
energy rating must be derated for temperature as shown in
the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
D
can safely be assumed
A Power MOSFET designated E
−
FET can be safely used
in switching circuits with unclamped inductive loads. For
to equal the values indicated.
5
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
SAFE OPERATING AREA
140
GS
I
D
= 16 A
SINGLE PULSE
120
100
80
10
m
s
T
C
= 25
°
C
10
100
m
s
1 ms
60
10 ms
1
dc
40
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
20
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
10
50% Duty Cycle
1
20%
10%
5%
0.1
2%
1%
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
UTD Semiconductor Co.,Limited
R
UMW
NT
D2
0N06L
60V N-Channel
MOSFET
Package Mechanical Data
TO-252
A
B2
Dimensions
Inches
C2
V 1
Ref.
Millimeters
Typ.
Typ.
Min.
2.10
0
Max.
2.50
0.10
0.86
5.48
0.60
0.58
6.30
Min.
0.083
0
Max.
0.098
0.004
0.034
0.216
0.024
0.023
0.248
A
A2
B
0.66
5.18
0.40
0.44
5.90
0.026
0.202
0.016
0.017
0.232
B2
C
C2
D
C
B
G
5.30REF
0.209REF
D1
E
DETAIL A
6.40
4.63
4.47
9.50
1.09
1.35
6.80
0.252
0.182
0.176
0.374
0.043
0.053
0.268
V1
E1
G
4.67
10.70
1.21
0.184
0.421
0.048
0.065
V 2
H
L
V1
1.65
L2
V1
V2
E1
L2
7°
7°
DETAIL A
0°
6°
0°
6°
Ordering information
Order code
Package
Baseqty
2500
Delivery mode
Tape and reel
UMW NTD20N06LT4
G
TO-252
7
UTD Semiconductor Co.,Limited
