VBsemi-Elec-CEPF634-VB
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CEPF634
Power MOSFET
FEATURES
PRODUCT SUMMARY
V
DS
(V)
• Dynamic dV/dt rating
250
Available
Available
• Repetitive avalanche rated
• Fast switching
R
DS(on)
(
)
Q
g
max. (nC)
Q
gs
(nC)
V
GS
= 10 V
0.
19
68
11
• Ease of paralleling
Q
gd
(nC)
35
• Simple drive requirements
Configuration
Single
D
TO-220AB
G
S
S
D
G
N-Channel MO
S
FET
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
250
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
V
V
GS
T
C
= 25 °C
14
Continuous Drain Current
V
GS
at 10 V
I
D
T
C
= 100 °C
8.5
A
Pulsed Drain Current
a
I
DM
56
Linear Derating Factor
1.0
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
E
AS
I
AR
550
14
E
AR
13
mJ
W
Maximum Power Dissipation
Peak Diode Recovery dV/dt
c
T
C
= 25 °C
P
D
125
4.8
dV/dt
T
J
, T
stg
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature)
d
-55 to +150
300
10
°C
for 10 s
lbf · in
N · m
Mounting Torque
6-32 or M3 screw
1.1
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 4.5 mH, R
g
= 25
, I
AS
= 14 A (see fig. 12).
c. I
SD
14 A, dI/dt
150 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6
mm from case.
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1
CEPF634
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
62
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
R
thJA
–
0.50
–
R
thCS
–
°C/W
R
thJC
1.0
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
250
–
–
–
V
V/°C
V
–
2.0
–
0.34
–
4.0
100
25
250
–
V
GS
V
DS
= 250 V, V
GS
= 0 V
DS
= 200 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 8.4 A
b
=
20 V
–
nA
–
–
Zero Gate Voltage Drain Current
I
DSS
μA
V
–
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
0.19
–
V
DS
= 50 V, I
D
= 8.4 A
b
6.7
–
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
C
iss
C
oss
C
rss
Q
g
–
–
–
–
–
–
–
–
–
–
1300
330
85
–
–
–
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
pF
nC
–
68
11
35
–
I
D
= 7.9 A, V
DS
= 200 V,
Q
gs
Q
gd
t
d(on)
t
r
V
GS
= 10 V
–
see fig. 6 and 13
b
–
11
24
53
49
–
V
DD
= 125 V, I
D
= 7.9 A,
ns
R
g
= 9.1
, R
D
= 8.7
, see fig. 10
b
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
–
–
D
Between lead,
Internal Drain Inductance
Internal Source Inductance
L
D
–
4.5
–
6 mm (0.25″) from
package and center of
die contact
nH
G
L
S
R
g
–
7.5
–
–
S
Gate Input Resistance
f = 1 MHz, open drain
0.3
1.2
Drain-Source Body Diode Characteristics
MOSFET symbol
D
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
I
S
–
–
–
–
14
56
showing the
A
integral reverse
p – n junction diode
G
I
SM
S
Body Diode Voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 14 A, V
GS
= 0 V
b
–
–
–
–
1.8
500
4.6
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
250
2.3
ns
μC
T
J
= 25 °C, I
F
= 7.9 A, dI/dt = 100 A/μs
b
Q
rr
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
300 μs; duty cycle
2 %.
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2
CEPF634
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
3.0
V
GS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
I
D
= 7.9 A
V
GS
= 10 V
T
o
p
2.5
2.0
10
1
Bottom
1.5
1.0
0.5
0.0
10
0
4.5 V
20 µs Pulse Width
T
C
=
25 °C
10
-1
10
0
10
1
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
V
DS
, Drain-to-Source Voltage (V)
91039_01
T
J
,
Junction
T
e
mperature (°C)
91039_04
Fig. 1 – Typical Output Characteristics, T
C
= 25 °C
Fig. 4 – Normalized On-Resistance vs. Temperature
3000
V
GS
15 V
10 V
V
GS
= 0
V
, f = 1
M
Hz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
T
o
p
C
rss
= C
gd
2400
1800
1200
600
0
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
C
oss
= C
ds
+ C
gd
10
1
C
iss
4.5 V
Bottom
C
oss
C
rss
10
0
20 µs Pulse Width
T
C
=
150 °C
10
0
10
1
10
-1
10
0
10
1
V
DS
,
Drain-to-Source Voltage (V)
91039_02
V
DS
,
Drain-to-Source Voltage (V)
91039_05
Fig. 2 – Typical Output Characteristics, T
C
= 150 °C
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
20
I
D
= 7.9 A
V
DS
= 200 V
DS
= 125 V
DS
= 50 V
16
12
8
10
1
V
150
°
C
25
°
C
V
10
0
4
20 µs Pulse Width
For test circuit
see figure 13
V
DS
=
50 V
10
-1
0
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
91039_03
V
GS
,
Gate-to-Source Voltage (V)
Q
G
,
T
o
tal Gate Charge (nC)
91039_06
Fig. 3 – Typical Transfer Characteristics
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
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3
CEPF634
14
12
10
8
150
°
C
10
1
10
0
10
-1
25
°
C
6
4
2
V
GS
= 0 V
1.1
0
0.9
0.5
0.6
0.7
0.8
1.0
25
50
75
100
125
150
V
SD
, Source-to-Drain Voltage (V)
91039_07
T
C
, Case
T
e
mperature (°C)
91039_09
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 9 – Maximum Drain Current vs. Case Temperature
R
D
10
3
V
DS
Operation in this area limited
5
by R
DS(on)
V
GS
D.U.T.
2
R
G
+
V
10
2
–
DD
5
10
µs
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
2
100
µs
10
Fig. 10a – Switching Time Test Circuit
5
1
ms
T
C
= 25
°
C
T
J
= 150
°
C
Single Pulse
2
V
DS
10
ms
1
90 %
2
5
2
5
2
5
10
3
1
10
10
2
V
DS
, Drain-to-Source Voltage (V)
91039_08
Fig. 8 – Maximum Safe Operating Area
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 10b – Switching Time Waveforms
10
1
0
−
0.5
P
DM
0.2
0.1
0.1
t
1
0.05
t
2
Notes:
0.02
0.01
Single Pulse
(Thermal Response)
1. Duty
Factor, D = t
1
/t
2
2. Peak
T
j
= P
DM
x Z
thJC
+ T
C
10
-2
10
-5
10
-4
10
-3
10
-2
0.1
1
10
t
1
, Rectangular Pulse Duration (s)
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
91039_11
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4
CEPF634
V
DS
L
V
DS
t
p
Vary t
p
to obtain
required I
AS
V
DD
D.U.T
R
G
+
–
V
DS
V
DD
I
AS
10 V
I
AS
0.01
Ω
t
p
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
1200
I
D
T
o
p
6.3 A
8.9 A
1000
800
Bottom 14
A
600
400
200
V
DD
= 50 V
25
0
125
75
100
150
50
91039_12c
Starting T
J
, Junction
T
e
mperature (°C)
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 k
Ω
Q
G
10 V
12 V
0.2 µF
0.3 µF
Q
GS
Q
GD
+
–
V
DS
D.U.T.
V
G
V
GS
3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
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5
CEPF634
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
Circuit layout con
s
ideration
s
•
Low
s
tray inductance
•
G
round plane
D.U.T.
•
Low leakage inductance
current tran
s
former
–
+
–
–
+
R
g
•
dV/dt controlled by R
g
•
Driver
s
ame type a
s
D.U.T.
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
+
–
V
DD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 14 – For N-Channel
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CEPF634
TO-220-1
MILLIMETERS
MIN.
INCHES
A
DIM.
E
MAX.
4.65
1.02
1.78
0.61
15.85
10.52
2.67
5.28
1.40
6.71
2.92
14.40
4.04
3.94
3.00
MIN.
MAX.
0.183
0.040
0.070
0.024
0.624
0.414
0.105
0.208
0.055
0.264
0.115
0.567
0.159
0.155
0.118
F
A
b
4.24
0.69
1.14
0.36
14.33
9.96
2.41
4.88
1.14
6.10
2.41
13.36
3.33
3.53
2.54
0.167
0.027
0.045
0.014
0.564
0.392
0.095
0.192
0.045
0.240
0.095
0.526
0.131
0.139
0.100
Ø P
b(1)
c
D
E
e
e(1)
F
H(1)
J(1)
L
1
3
2
L(1)
Ø P
Q
*
M
b(1)
ECN: X15-0364-Rev. C, 14-Dec-15
DWG: 6031
Note
•
M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM
C
b
e
J(1)
e(1)
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7
CEPF634
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aiwan VBsemi”), assumes no responsibility for any errors, inaccuracies or
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o
t
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aiwan VBsemi
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aiwan demand that the Taiwan VBsemi of. Statement on whether the
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aiwan
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