VBsemi-Elec-FDP10N60NZ-VB
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FDP10N60NZ
N-Channel 650V (D-S)
Power MOSFET
FEATURES
• Low figure-of-merit (FOM) R
on
x Q
g
• Low input capacitance (C
iss
• Reduced switching and conduction losses
• Ultra low gate charge (Q
g
)
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
max. at 25 °C (
Ω
)
Q
g
max. (nC)
65
0
)
V
GS
= 10 V
0.
58
43
5
Q
gs
(nC)
• Avalanche energy rated (UIS)
22
Q
gd
(nC)
Configuration
Single
APPLICATIONS
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
– High-intensity discharge (HID)
– Fluorescent ballast lighting
• Industrial
TO-220AB
TO-220 FULLPAK
D
D
2
PAK
(TO-263)
G
G
D
S
S
D
G
S
G D
S
Top
V
ie
w
N-Channel MOSFET
Top View
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
650
30
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
V
V
GS
12
T
C
= 25 °C
Continuous Drain Current (T
J
= 150 °C)
V
GS
at 10 V
I
D
9.4
T
C
= 100 °C
A
Pulsed Drain Current
a
I
DM
45
3.6
Linear Derating Factor
Single Pulse Avalanche Energy
b
W/°C
mJ
W
E
AS
P
D
29
0
1
0
6
/
3
4
-55 to +150
15
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt
d
T
J
, T
stg
°C
T
J
= 125 °C
for 10 s
dV/dt
V/ns
°C
4.
1
Soldering Recommendations (Peak Temperature)
c
300
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature.
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 28.2 mH, R
g
= 25
Ω
, I
AS
= 4.5 A.
c. 1.6
mm from case.
d. I
SD
≤
I
D
, dI/dt = 100 A/μs, starting T
J
= 25 °C.
1
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FDP10N60NZ
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
60
UNIT
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
R
thJA
R
thJC
–
–
°C/W
0.8
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage (N)
V
DS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
650
–
–
–
V
V/°C
V
Δ
V
DS
/T
J
V
GS(th)
–
2
–
–
–
–
–
–
0.75
–
4
V
GS
V
GS
=
=
20 V
30 V
–
–
100
1
nA
μA
Gate-Source Leakage
I
GSS
V
DS
= 650 V, V
GS
= 0 V
V
DS
= 520 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 8 A
V
DS
= 30 V, I
D
= 8 A
–
1
Zero Gate Voltage Drain Current
I
DSS
μA
–
10
Drain-Source On-State Resistance
Forward Transconductance
R
DS(on)
g
fs
0.
58
16
Ω
–
–
S
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
iss
C
oss
C
rss
–
–
–
2200
4
20
–
–
–
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
210
pF
nC
Effective Output Capacitance, Energy
Related
a
C
o(er)
C
o(tr)
–
–
63
–
–
V
DS
= 0 V to 520 V, V
GS
= 0 V
Effective Output Capacitance, Time
Related
b
213
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
–
–
–
–
–
–
–
–
43
5
–
–
–
V
GS
= 10 V
I
D
= 8 A, V
DS
= 520 V
22
13
11
81
25
3.5
–
–
–
–
V
DD
= 520 V, I
D
= 8 A,
V
GS
= 10 V, R
g
= 9.1
Ω
ns
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
Gate Input Resistance
R
g
f = 1 MHz, open drain
–
Ω
Drain-Source Body Diode Characteristics
MOSFET symbol
showing the
integral reverse
p – n junction diode
D
Continuous Source-Drain Diode Current
I
S
–
–
–
–
15
40
A
G
Pulsed Diode Forward Current
I
SM
S
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
V
SD
t
rr
T
J
= 25 °C, I
S
= 8 A, V
GS
= 0 V
–
–
–
–
–
1.5
V
ns
μC
A
345
4.5
35
–
–
–
T
J
= 25 °C, I
F
= I
S
= 8 A,
dI/dt = 100 A/μs, V
R
= 400 V
Q
rr
I
RRM
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
.
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
.
2
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FDP10N60NZ
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
3
2.5
2
50
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
I
D
= 8 A
T
J
= 25 °C
40
30
20
10
0
BOTTOM 5
V
1.5
1
V
GS
= 10 V
0.5
0
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
0
5
10
15
20
25
30
T
J
, Junction
T
e
mperature (°C)
V
DS
, Drain-to-Source Voltage (V)
Fig. 1 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
30
25
20
15
10
5
2800
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
T
J
= 150 °C
C
i
ss
2100
V
GS
= 0
V
, f = 1
M
Hz
C
i
ss
= C
g
s
+ C
gd
, C
d
s
S
horted
8 V
7 V
BOTTOM 6
V
C
r
ss
= C
gd
C
o
ss
1400
700
0
C
o
ss
= C
d
s
+ C
gd
ġ
C
r
ss
ġ
5 V
0
0
5
10
15
20
25
30
0
100
200
300
400
500
600
V
DS
, Drain-to-Source Voltage (V)
V
D
S
, Drain-to-
S
ource Voltage (V)
Fig. 2 – Typical Output Characteristics
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
50
40
30
20
10
0
24
V
D
S
= 520 V
V
D
S
= 325 V
D
S
= 130 V
20
V
16
12
8
T
J
= 25 °C
4
T
J
= 150 °C
V
D
S
= 30.8 V
0
0
5
10
15
20
25
0
20
40
60
80
100
V
GS
, Gate-to-Source Voltage (V)
Q
g
,
T
o
tal
G
ate Charge (nC)
Fig. 3 – Typical Transfer Characteristics
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
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3
FDP10N60NZ
20
15
10
5
100
T
J
= 150 °C
T
J
= 25 °C
10
1
V
GS
= 0 V
0
0.1
25
50
75
100
125
150
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
V
S
D
,
S
ource-Drain Voltage (V)
T
J
, Case
T
e
mperature (°C)
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 9 – Maximum Drain Current vs. Case Temperature
800
775
750
725
700
1000
Operation in thi
s
Area
Limited by R
D
S
(on)
I
DM
= Limited
100
10
100 μ
s
Limited by R
D
S
(on)
*
1
675
650
625
600
1 m
s
10 m
s
0.1
T
T
= 25 °C
= 150 °C
C
J
BVD
SS
Limited
S
ingle Pul
s
e
0.01
1
10
100
1000
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
V
D
S
– Drai
n
–
t
o
–
S
ource Voltage (V)
*
V
GS
> minimum V
GS
at which R
D
S
(on)
i
s s
pecified
T
J
, Junction
T
e
mperature (°C)
Fig. 8 – Maximum Safe Operating Area
Fig. 10 – Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
S
ingle Pul
s
e
0.01
0.0001
0.001
0.01
0.1
1
Pul
s
e Time (
s
)
Fig. 11 – Normalized Thermal Transient Impedance, Junction-to-Case
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4
FDP10N60NZ
R
D
V
DS
Q
G
10 V
V
GS
D.U.T.
Q
GS
Q
GD
R
G
+
–
V
DD
V
G
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Charge
Fig. 12 – Switching Time Test Circuit
Fig. 16 –
Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
V
DS
90 %
50 k
Ω
12 V
0.2 µF
0.3 µF
+
–
V
DS
10 %
V
GS
D.U.T.
t
d(on)
t
r
t
d(off)
t
f
V
GS
3 mA
Fig. 13 – Switching Time Waveforms
I
G
I
D
Current sampling resistors
L
Fig. 17 – Gate Charge Test Circuit
V
DS
Vary t
p
to obtain
required I
AS
D.U.T
I
AS
R
G
+
–
V
DD
10 V
0.01
Ω
t
p
Fig. 14 – Unclamped Inductive Test Circuit
V
DS
t
p
V
DD
V
DS
I
AS
Fig. 15 – Unclamped Inductive Waveforms
5
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FDP10N60NZ
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
Circuit layout con
s
ideration
s
•
Low
s
tray inductance
•
G
round plane
D.U.T.
•
Low leakage inductance
current tran
s
former
–
+
–
–
+
R
g
•
dV/dt controlled by R
g
•
Driver
s
ame type a
s
D.U.T.
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
+
–
V
DD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 18 – For N-Channel
6
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FDP10N60NZ
TO-220AB
MILLIMETERS
MIN.
INCHES
A
E
DIM.
MAX.
4.65
1.01
1.73
0.61
15.49
10.51
2.67
5.28
1.40
6.48
2.92
14.02
3.82
3.94
3.00
MIN.
0.167
0.027
0.047
0.014
0.585
0.395
0.095
0.192
0.045
0.240
0.095
0.526
0.131
0.139
0.102
MAX.
0.183
0.040
0.068
0.024
0.610
0.414
0.105
0.208
0.055
0.255
0.115
0.552
0.150
0.155
0.118
F
A
b
4.25
0.69
1.20
0.36
14.85
10.04
2.41
4.88
1.14
6.09
2.41
13.35
3.32
3.54
2.60
Ø P
b(1)
c
D
E
e
e(1)
F
H(1)
J(1)
L
1
3
2
L(1)
Ø P
Q
*
M
b(1)
ECN: X12-0208-Rev. N, 08-Oct-12
DWG: 5471
Notes
* M = 1.32 mm to 1.62 mm (dimension including protrusion)
Heatsink hole for HVM
C
b
e
J(1)
e(1)
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FDP10N60NZ
TO-220 FULLPAK (HIGH VOLTAGE)
A
E
A1
Ø P
n
d1
d3
D
u
L1
V
L
b
3
A2
b
2
c
b
e
MILLIMETERS
INCHES
DIM.
A
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
A1
A2
b
b2
b3
c
D
d1
d3
E
e
2.54 BSC
0.100 BSC
L
13.200
3.100
6.050
3.050
2.400
0.400
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
0.541
0.138
0.242
0.136
0.098
0.020
L1
n
Ø P
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet C
pk
> 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
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FDP10N60NZ
TO-263AB (HIGH VOLTAGE)
A
B
(Dat
u
m A)
3
4
A
A
E
c2
H
L1
4
Ga
u
ge
plane
4
0° to
8
°
B
5
Detail A
Seating plane
D
H
L
C
C
A1
L3
L4
Detail “A”
1
2
3
L2
Rotated 90° CW
B
B
scale
8
:1
A
2 x
b
2
2 x
b
c
E
M
M
B
0.010
A
M
± 0.004
B
2 x e
Base
metal
5
D1
4
Plating
(c)
b
1,
b
3
5
c1
(
b
,
b
2)
Lead tip
4
E1
Section B – B and C – C
Scale: none
V
ie
w
A – A
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
A
MIN.
4.06
0.00
0.51
0.51
1.14
1.14
0.38
0.38
1.14
8.38
MAX.
4.83
0.25
0.99
0.89
1.78
1.73
0.74
0.58
1.65
9.65
MIN.
0.160
0.000
0.020
0.020
0.045
0.045
0.015
0.015
0.045
0.330
MAX.
0.190
0.010
0.039
0.035
0.070
0.068
0.029
0.023
0.065
0.380
DIM.
D1
E
MIN.
6.86
MAX.
MIN.
MAX.
–
10.67
–
0.270
0.380
0.245
–
0.420
–
A1
b
9.65
6.22
E1
e
b1
b2
b3
c
2.54 BSC
0.100 BSC
H
14.61
15.88
2.79
1.65
1.78
0.575
0.625
0.110
0.066
0.070
L
1.78
0.070
L1
L2
L3
L4
–
–
–
–
c1
c2
D
0.25 BSC
0.010 BSC
4.78
5.28
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
D
W
G: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
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FDP10N60NZ
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aiwan VBsemi”), assumes no responsibility for any errors, inaccuracies or
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aiwan
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