VBsemi-Elec-FDPF13N50FT-VB
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FDPF13N50FT
N-Channel
(D-S)
Power MOSFET
550
V
FEATURES
• Optimal Design
PRODUCT SUMMARY
V
DS
(V)
550
– Low Area Specific On-Resistance
– Low Input Capacitance (C
iss
R
DS(on)
max. at 25 °C (
)
Q
g
max. (nC)
V
GS
= 10 V
0.26
)
150
12
– Reduced Capacitive Switching Losses
– High Body Diode Ruggedness
– Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
– Low Cost
Q
gs
(nC)
Q
gd
(nC)
25
Configuration
Single
– Simple Gate Drive Circuitry
– Low Figure-of-Merit (FOM): R
on
x Q
g
– Fast Switching
APPLICATIONS
D
• Consumer Electronics
TO-220 FULLPAK
– Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
– SMPS
• Industrial
G
– Welding
– Induction Heating
– Motor Drives
• Battery Chargers
• SMPS
S
N-Channel MOSFET
– Power Factor Correction (PFC)
S
D
G
Top
V
ie
w
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
Gate-Source Voltage AC (f > 1 Hz)
V
DS
550
20
V
V
GS
30
T
C
= 25 °C
18
Continuous Drain Current (T
J
= 150 °C)
V
GS
at 10 V
I
D
T
C
= 100 °C
11
A
Pulsed Drain Current
a
I
DM
56
2.2
Linear Derating Factor
Single Pulse Avalanche Energy
b
W/°C
mJ
W
E
AS
P
D
281
Maximum Power Dissipation
60
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt
d
T
J
, T
stg
– 55 to + 150
24
°C
T
J
= 125 °C
for 10 s
dV/dt
V/ns
°C
0.36
300
c
Soldering Recommendations (Peak Temperature)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature.
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 10 mH, R
g
= 25
, I
AS
= 7.5 A.
c. 1.6
mm from case.
d. I
SD
I
D
, starting T
J
= 25 °C.
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1
FDPF13N50FT
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
R
thJA
R
thJC
–
–
40
°C/W
Maximum Junction-to-Case (Drain)
0.45
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 μA
550
–
–
–
V
V/°C
V
–
2
–
–
–
–
–
0.56
Reference to 25 °C, I
D
= 250 μA
V
DS
= V
GS
, I
D
= 250 μA
–
–
4
V
GS
=
20 V
100
1
nA
V
DS
= 500 V, V
GS
= 0 V
–
Zero Gate Voltage Drain Current
I
DSS
μA
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
–
10
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
V
GS
= 10 V
I
D
= 10 A
0.26
12
V
DS
= 50 V, I
D
= 10 A
–
S
Input Capacitance
C
iss
C
oss
C
rss
–
–
–
3094
152
13
–
–
–
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
pF
nC
Effective output capacitance, energy
related
a
C
o(er)
C
o(tr)
–
–
131
189
–
–
V
GS
= 0 V,
V
DS
= 0 V to 400 V
Effective output capacitance, time
related
b
Total Gate Charge
Q
g
Q
gs
Q
gd
t
d(on)
t
r
–
–
–
–
–
–
–
–
80
12
150
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
V
GS
= 10 V
I
D
= 10 A, V
DS
= 400 V
–
25
24
–
50
31
117
56
62
176
112
–
V
DD
= 400 V, I
D
= 10 A,
V
GS
= 10 V, R
g
= 9.1
ns
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
Gate Input Resistance
Drain-Source Body Diode Characteristics
R
g
f = 1 MHz, open drain
1.8
MOSFET symbol
showing the
integral reverse
p – n junction diode
D
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
I
S
–
–
–
–
20
80
A
G
I
SM
S
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
V
SD
t
rr
T
J
= 25 °C, I
S
= 10 A, V
GS
= 0 V
–
–
–
–
–
1.2
V
ns
μC
A
437
5.9
25
–
–
–
T
J
= 25 °C, I
F
= I
S
= 10 A,
dI/dt = 100 A/μs, V
R
= 20 V
Q
rr
I
RRM
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
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FDPF13N50FT
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
80
3
2.5
2
TOP
15 V
14 V
13 V
12 V
T
J
= 25 °C
I
D
= 10 A
11 V
10 V
9 V
8 V
7 V
6 V
60
40
20
BOTTOM 5
V
1.5
1
V
GS
= 10 V
0.5
0
0
0
5
10
15
20
25
30
30
25
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
V
DS
, Drain-to-Source Voltage (V)
T
J
, Junction
T
e
mperature (°C)
Fig. 1 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
40
30
20
10
10 000
TOP
15 V
14 V
13 V
12 V
T
J
= 150 °C
ġ
11 V
C
i
ss
1000
100
10
V
GS
= 0
V
, f = 1
M
Hz
10 V
9 V
8 V
7 V
6 V
C
i
ss
= C
g
s
+ C
gd
, C
d
s
S
horted
C
r
ss
= C
gd
C
o
ss
= C
d
s
+ C
gd
BOTTOM 5
V
ġ
C
o
ss
ġ
C
r
ss
1
0
0
100
200
300
400
500
0
5
10
15
20
25
V
DS
, Drain-to-Source Voltage (V)
V
D
S
, Drain-to-
S
ource Voltage (V)
Fig. 2 – Typical Output Characteristics
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
24
80
60
40
20
V
D
S
= 400 V
V
D
S
= 250 V
T
J
= 25 °C
20
16
12
8
V
D
S
= 100 V
T
J
= 150 °C
4
0
0
120
0
30
60
90
150
180
0
5
10
15
20
V
GS
, Gate-to-Source Voltage (V)
Q
g
,
T
o
tal
G
ate Charge (nC)
Fig. 3 – Typical Transfer Characteristics
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
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3
FDPF13N50FT
20
100
T
J
= 150 °C
16
12
8
T
J
= 25 °C
10
ġ
ġ
1
4
V
GS
= 0 V
ġ
0
0.1
25
50
75
100
125
150
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
S
D
,
S
ource-Drain Voltage (V)
T
J
, Case
T
e
mperature (°C)
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 9 – Maximum Drain Current vs. Case Temperature
1000
625
600
575
550
525
500
475
Operation in thi
s
area
limited by R
D
S
(on)
100
10
1
100 μ
s
1 m
s
Limited by R
D
S
(on)
*
T
T
= 25 °C
= 150 °C
C
J
S
ingle Pul
s
e
10 m
s
BVD
SS
Limited
0.1
1
10
100
1000
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
V
D
S
, Drain-to-
S
ource Voltage (V)
* V
GS
> minimum V
GS
at which R
D
S
(on)
i
s s
pecified
T
J
, Junction
T
e
mperature (°C)
Fig. 8 – Maximum Safe Operating Area
Fig. 10 – Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.02
0.05
S
ingle Pul
s
e
0.01
0.0001
0.001
0.01
0.1
1
Pul
s
e Time (
s
)
Fig. 11 – Normalized Thermal Transient Impedance, Junction-to-Case
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4
FDPF13N50FT
R
D
V
DS
Q
G
10 V
V
GS
D.U.T.
Q
GS
Q
GD
R
G
+
–
V
DD
V
G
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Charge
Fig. 12 – Switching Time Test Circuit
Fig. 16 –
Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
V
DS
90 %
50 k
Ω
12 V
0.2 µF
0.3 µF
+
–
V
DS
10 %
V
GS
D.U.T.
t
d(on)
t
r
t
d(off)
t
f
V
GS
3 mA
Fig. 13 – Switching Time Waveforms
I
G
I
D
Current sampling resistors
Fig. 17 – Gate Charge Test Circuit
L
V
DS
Vary t
p
to obtain
required I
AS
D.U.T
I
AS
R
G
+
–
V
DD
10 V
0.01
Ω
t
p
Fig. 14 – Unclamped Inductive Test Circuit
V
DS
t
p
V
DD
V
DS
I
AS
Fig. 15 – Unclamped Inductive Waveforms
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5
FDPF13N50FT
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
Circuit layout con
s
ideration
s
•
Low
s
tray inductance
•
G
round plane
D.U.T.
•
Low leakage inductance
current tran
s
former
–
+
–
–
+
R
g
•
dV/dt controlled by R
g
•
Driver
s
ame type a
s
D.U.T.
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
+
–
V
DD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 18 – For N-Channel
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FDPF13N50FT
TO-220 FULLPAK (HIGH VOLTAGE)
A
E
n
A1
Ø P
d1
d3
D
u
L1
V
L
b
3
A2
b
2
c
b
e
MILLIMETERS
INCHES
DIM.
A
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
A1
A2
b
b2
b3
c
D
d1
d3
E
e
2.54 BSC
0.100 BSC
L
13.200
3.100
6.050
3.050
2.400
0.400
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
0.541
0.138
0.242
0.136
0.098
0.020
L1
n
Ø P
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet C
pk
> 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
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7
FDPF13N50FT
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data are subject to change without notice.
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representatives (collectively, the “
T
aiwan VBsemi”), assumes no responsibility for any errors, inaccuracies or
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any goods or continuous production.
T
o
t
he maximum extent permitted by applicable law on
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aiwan VBsemi
relinquished: (1) any application and all liability arising out of or use of any products; (2) any and all liability,
including but not limited to special, consequential damages or incidental ; (3) any and all implied warranties,
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Statement on certain types of applications are based on knowledge of the product is often used in a typical
application of the general product VBsemi
T
aiwan demand that the Taiwan VBsemi of. Statement on whether the
product is suitable for a particular application is non-binding. It is the customer’s responsibility to verify specific
product features in the products described in the specification is appropriate for use in a particular application.
Parameter data sheets and technical specifications can be provided may vary depending on the application and
performance over time. All operating parameters, including typical parameters must be made by customer’s
technical experts validated for each customer application. Product specifications do not expand or modify
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aiwan
VBsemi purchasing terms and conditions, including but not limited to warranty herein.
Unless expressly stated in writing,
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aiwan VBsemi products are not intended for use in medical, life saving,
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aiwan VBsemi such applications using client did not express their
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aiwan VBsemi people who are related to product design applications and
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oHS compliant and meets the definition of restrictions under Directive of the European Parliament
2011/65 / EU, 2011 Nian. 6. 8 Ri Yue restrict the use of certain hazardous substances in electrical and
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