VBsemi-Elec-SI2309DS-VB

SI2309DS  

P-Channel 60-V (D-S) MOSFET  

FEATURES  

PRODUCT SUMMARY  

V

DS

(V)  

• Isolated

 

Package  

– 60  

A

v

aila

b

le  

• High Voltage Isolation = 2.5 kV

RMS

(t = 60 s;  

f = 60 Hz)  

R

DS(on)

(

Ω

)  

Q

g

(Max.) (nC)  

V

GS

= – 10 V  

0.

04  

RoHS*  

COMPLIANT  

• Sink

 

to Lead Creepage Distance = 4.8 mm  

• P-Channel  

• 175

 

°C Operating Temperature  

• Dynamic

 

dV/dt Rating  

• Low

 

Thermal Resistance  

• Lead

 

(Pb)-free Available  

12  

3.8  

5.1  

Q

Q

Configuration  

Single  

S

TO-236  

(SOT-23)  

G

G

S

1

2

3

D

D

P-Channel MOSFET  

Top

V

ie

w  

ABSOLUTE MAXIMUM RATINGS

T

C

= 25 °C, unless otherwise noted  

PARAMETER  

SYMBOL  

LIMIT  

– 60  

UNIT  

Drain-Source Voltage  

Gate-Source Voltage  

V

DS  

V

V

GS  

± 20  

– 5.2  

– 3.8  

– 21  

T

C

= 25 °C  

T

C

=

1

0

0

°

C  

Continuous Drain Current  

V

GS

at – 10 V  

I

D  

A

Pulsed Drain Current

a  

I

DM  

Linear Derating Factor  

0.18  

120  

W/°C  

mJ  

A

Single Pulse Avalanche Energy

b  

Repetitive Avalanche Current

a  

Repetitive Avalanche Energy

a  

E

AS  

I

AR  

– 5.2  

2.7  

E

AR  

mJ  

W

Maximum Power Dissipation  

T

P

D  

27  

Peak Diode Recovery dV/dt

c  

dV/dt  

T

J

, T

stg  

– 4.5  

– 55 to + 175  

300

d  

10  

V/ns  

Operating Junction and Storage Temperature Range  

Soldering Recommendations (Peak Temperature)  

°C  

for 10 s  

6-32 or M3 screw  

lbf · in  

N · m  

Mounting Torque  

1.1  

Notes  

a. Repetitive

 

rating; pulse width limited by maximum junction temperature (see fig. 11).  

b. V

DD

= – 25 V, starting T

J

= 25 °C, L = 5.0 mH, R

G

= 25

Ω

, I

AS

= – 5.3 A (see fig. 12).  

c. I

SD

≤

– 6.7 A, dI/dt

≤

90 A/µs, V

DD

≤

V

DS

, T

J

≤

175 °C.  

d. 1.6

 

mm from case.  

1

SI2309DS  

THERMAL RESISTANCE RATINGS  

PARAMETER  

SYMBOL  

TYP.  

MAX.  

65  

UNIT  

Maximum Junction-to-Ambient  

Maximum Junction-to-Case (Drain)  

R

thJA  

–

–

°C/W  

R

thJC  

5.5  

SPECIFICATIONS

T

J

= 25 °C, unless otherwise noted  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

MIN.  

TYP.  

MAX.  

UNIT  

Static  

Drain-Source Breakdown Voltage  

V

DS

Temperature Coefficient  

Gate-Source Threshold Voltage  

Gate-Source Leakage  

V

DS  

Δ

V

DS

/T

J  

V

GS(th)  

I

GSS  

V

GS

= 0 V, I

D

= – 250 µA  

Reference to 25 °C, I

D

= – 1 mA  

V

DS

= V

GS

, I

D

= – 250 µA  

V

GS

= ± 20 V  

– 60  

–

–

–

V

V/°C  

V

–

– 0.060  

– 1.0  

–

–

–

–

– 2.5  

± 100  

– 100  

– 500  

–

–

nA  

V

DS

= – 60 V, V

GS

= 0 V  

–

–

Zero Gate Voltage Drain Current  

I

DSS  

µA  

V

DS

= – 48 V

GS

= 0 V, T

J

= 150 °C  

Drain-Source On-State Resistance  

Forward Transconductance  

Dynamic  

R

DS(on)  

g

fs  

V

GS

= – 10 V  

I

D

= – 3.2 A

b  

–

Ω

0.

0

5

 

V

DS

= – 25 V, I

D

= – 3.2 A

b  

1.6  

–

–

S

Input Capacitance  

C

iss  

C

oss  

C

rss  

C

–

–

–

–

–

–

–

–

–

–

–

270  

170  

31  

12  

–

–

V

GS

= 0 V,  

V

DS

= – 25 V,  

f = 1.0 MHz, see fig. 5  

Output Capacitance  

Reverse Transfer Capacitance  

Drain to Sink Capacitance  

Total Gate Charge  

Gate-Source Charge  

Gate-Drain Charge  

Turn-On Delay Time  

Rise Time  

–

pF  

nC  

ns  

–

–

f = 1.0 MHz  

Q

g  

12  

3.8  

5.1  

–

I

see fig. 6 and 13

b  

Q

gs  

Q

gd  

t

d(on)  

t

r  

V

GS

= – 10 V  

–

–

11  

63  

9.6  

31  

V

DD

= – 30 V, I

D

= – 4.7 A,  

R

G

= 24

Ω

,

R

D

= 4.0

Ω

,  

see fig. 10

b  

–

Turn-Off Delay Time  

Fall Time  

t

d(off)  

t

f  

–

–

D

Between lead,  

Internal Drain Inductance  

Internal Source Inductance  

L

D  

L

S  

–

–

4.5  

7.5  

–

–

6 mm (0.25″) from  

package and center of  

die contact  

nH  

G

S

Drain-Source Body Diode Characteristics  

MOSFET symbol  

showing the  

integral reverse  

p – n junction diode  

D

Continuous Source-Drain Diode Current  

I

S  

–

–

–

–

– 5.2  

– 21  

A

G

Pulsed Diode Forward Current

a  

I

SM  

S

Body Diode Voltage  

V

SD  

t

rr  

T

J

= 25 °C, I

S

= – 5.2 A, V

GS

= 0 V

b  

–

–

–

–

– 5 .5  

160  

V

Body Diode Reverse Recovery Time  

Body Diode Reverse Recovery Charge  

Forward Turn-On Time  

80  

ns  

µC  

T

J

= 25 °C, I

F

= – 4.7 A, dI/dt = 100 A/µs

b  

Q

rr  

t

on  

0.096  

0.19  

Intrinsic turn-on time is negligible (turn-on is dominated by L

S

and L

D

)  

Notes  

a. Repetitive

 

rating; pulse width limited by maximum junction temperature (see fig. 11).  

b. Pulse

 

width

≤

300 µs; duty cycle

≤

2 %.  

2

SI2309DS  

TYPICAL CHARACTERISTICS

25 °C, unless otherwise noted  

Fig. 1 – Typical Output Characteristics, T

C

= 25 °C  

Fig. 3 – Typical Transfer Characteristics  

Fig. 2 – Typical Output Characteristics, T

C

= 175 °C  

Fig. 4 – Normalized On-Resistance vs. Temperature  

3

SI2309DS  

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage  

Fig. 7 – Typical Source-Drain Diode Forward Voltage  

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage  

Fig. 8 – Maximum Safe Operating Area  

4

SI2309DS  

R

D  

V

DS  

V

GS  

D.U.T.  

R

G  

–

+

V

DD  

– 10

V  

P

u

lse

w

idth

≤

1

µ

s  

D

u

ty factor

≤

0.1

%  

Fig. 10a – Switching Time Test Circuit  

t

d(on)

t

r  

t

d(off)

t

f  

V

GS  

10

%  

90

%  

V

DS  

Fig. 10b – Switching Time Waveforms  

Fig. 9 – Maximum Drain Current vs. Case Temperature  

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case  

L

I

AS  

V

DS  

V

ary t

p

to o

b

tain  

re

qu

ired I

AS  

V

DS  

D.U.T.  

R

G  

–

V

+

DD  

V

DD  

I

AS  

t

p  

– 10

V

 

0.01

Ω

 

t

p  

V

DS  

Fig. 12b – Unclamped Inductive Waveforms  

Fig. 12a – Unclamped Inductive Test Circuit  

5

SI2309DS  

Fig. 12c – Maximum Avalanche Energy vs. Drain Current  

C

u

rrent reg

u

lator  

Same type as D.U.T.  

50 k

Ω

 

Q

G  

– 10

V  

12

V

 

0.2

µ

F  

0.3

µ

F  

–

Q

GS  

Q

GD  

V

+

DS  

D.U.T.  

V

G  

V

GS  

– 3 mA  

Charge  

I

G  

I

D  

C

u

rrent sampling resistors  

Fig. 13b – Gate Charge Test Circuit  

Fig. 13a – Basic Gate Charge Waveform  

6

SI2309DS  

Peak Diode Recovery dV/dt Test Circuit  

D.U.T.  

+

Circ

u

it layo

u

t considerations  

•

Lo

w

stray ind

u

ctance  

•

Gro

u

nd plane  

•

Lo

w

leakage ind

u

ctance  

c

u

rrent transformer  

–

+

–

+

–

R

G  

+

–

•

d

V

/dt controlled

b

y R

G  

•

I

SD

controlled

b

y d

u

ty factor “D”  

•

D.U.T. – de

v

ice

u

nder test  

V

DD  

Compliment

N

-Channel of D.U.

T

. for dri

v

er  

Dri

v

er gate dri

v

e  

P.

W

.  

Period  

Period  

D =  

P.

W

.  

V

= – 10

V

*  

GS  

D.U.T. I

 

w

a

v

eform  

SD  

Re

v

erse  

reco

v

ery  

c

u

rrent  

Body diode for

w

ard  

c

u

rrent  

dI/dt  

D.U.T.

V w

a

v

eform  

DS  

Diode reco

v

ery  

d

V

/dt  

V

DD  

Re-applied  

v

oltage  

Body diode for

w

ard drop  

Ripple

≤

5

%  

Ind

u

ctor c

u

rrent  

I

SD  

*

V

GS

= – 5

V

for logic le

v

el and

 

– 3

V

dri

v

e de

v

ices  

Fig. 14 – For P-Channel  

7

SI2309DS  

SOT-23 (TO-236): 3-LEAD  

b

3

E

1

E

1

2

e

S

e

1

D

0.10 mm  

0.004″  

C

C

0.25 mm  

q

A

2

A

G

au

ge Pl

a

ne  

S

e

a

ting Pl

a

ne  

S

e

a

ting Pl

a

ne  

C

A

1

L

1

L

MILLIMETERS  

INCHES  

Dim  

Min  

0.89  

0.01  

Max  

1.12  

0.10  

Min  

0.0

3

5  

0.0004  

Max  

0.044  

0.004  

A

A

1  

A

2  

0.88  

0.

3

5  

0.085  

2.80  

2.10  

1.20  

1.02  

0.50  

0.18  

3

.04  

2.64  

1.40  

0.0

3

46  

0.014  

0.00

3  

0.110  

0.08

3  

0.047  

0.040  

0.020  

0.007  

0.120  

0.104  

0.055  

b

c

D

E

E

1  

e

0.95 BSC  

1.90 BSC  

0.0

3

74 Ref  

e

1  

0.0748 Ref  

L

0.40  

0.60  

8°  

0.016  

0.024  

8°  

L

1  

0.64 Ref  

0.50 Ref  

0.025 Ref  

0.020 Ref  

S

q

3

°  

3

°  

ECN: S-0

3

946-Rev. K, 09-Jul-01  

DWG: 5479  

8

SI2309DS  

RECOMMENDED MINIMUM

P

A

DS FOR SO

T

–

23  

0.037  

0.022  

(0.950)  

(0.559)  

0.053  

(1.341)  

0.097  

(2.459)  

Recommended Minimum Pads  

Dimensions in Inches/(mm)  

9

SI2309DS  

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without notice.  

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a

iwan VBsemi Electronics Co., Ltd., branches, agents, employees, and all persons acting on its or their  

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a

iwan VBsemi”), assumes no responsibility for any errors, inaccuracies or  

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Statement on certain types of applications are based on knowledge of the product is often used in a typical  

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Taiwan VBsemi Electronics Co., Ltd., hereby certify that all of the products

RoHS compliant and meets the definition of restrictions under Directive of the

2011/65 / EU, 2011 Nian. 6. 8 Ri Yue restrict the use of certain hazardous substances in electrical and  

tw

)  

Please note that some documents may still refer to Taiwan VBsemi RoHS Directive 2002/95 / EC. We  

confirm that all products identified as consistent with the Directive 2002/95 / EC European Directive  

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10