VBsemi-Elec-VBZP50N50S
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VBZP50N50S
N-Channel 500V
(
D-S
)
Super Junction Power MOSFET
FEATURES
• Low Gate Charge Q
g
Results in Simple Drive
Requirement
PRODUCT SUMMARY
V
DS
(V)
500
Available
R
DS(on)
(
)
V
GS
= 10 V
0.080
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Q
g
(Max.) (nC)
Q
gs
(nC)
350
85
• Fully Characterized Capacitance and Avalanche Voltage
and Current
Q
gd
(nC)
180
Configuration
Single
• Low R
DS(on)
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
D
• Uninterruptible Power Supply
Super-247
• High Speed Power Switching
• Hard Switched and High Frequency Circuits
G
S
D
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
500
30
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
V
V
GS
T
C
= 25 °C
40
Continuous Drain Current
V
GS
at 10 V
I
D
T
C
= 100 °C
25
A
Pulsed Drain Current
a
I
DM
180
Linear Derating Factor
4.3
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
E
AS
I
AR
910
40
51
E
AR
mJ
W
Maximum Power Dissipation
T
C
= 25 °C
P
D
530
Peak Diode Recovery dV/dt
c
dV/dt
T
J
, T
stg
9.0
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
– 55 to + 150
300
d
°C
for 10 s
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting
T
J
= 25 °C, L = 0.82 mH, R
g
= 25
, I
AS
= 47 A (see fig. 12c).
c. I
SD
47 A, dI/dt
230 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6
mm from case.
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1
VBZP50N50S
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
40
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
R
thJA
R
thCS
R
thJC
–
0.24
–
–
°C/W
0.23
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
500
–
–
–
V
V/°C
V
V
DS
Temperature Coefficient
–
3.0
–
0.60
Gate-Source Threshold Voltage
Gate-Source Leakage
–
5.0
100
50
250
–
V
GS
V
DS
= 500 V, V
GS
= 0 V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 28 A
b
V
DS
= 50 V, I
D
= 28 A
=
30 V
–
nA
–
–
Zero Gate Voltage Drain Current
I
DSS
μA
V
–
–
0.080
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
23
–
S
Input Capacitance
C
iss
C
oss
C
rss
–
–
–
–
–
–
–
–
–
–
–
–
–
8310
960
120
10170
240
440
–
–
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
Output Capacitance
–
Reverse Transfer Capacitance
–
pF
V
DS
= 1.0 V, f = 1.0 MHz
DS
= 400 V, f = 1.0 MHz
V
DS
= 0 V to 400 V
c
–
Output Capacitance
C
oss
V
GS
= 0 V
V
–
–
Effective Output Capacitance
Total Gate Charge
C
oss
eff.
Q
g
350
85
180
–
I
D
= 47 A, V
DS
= 400 V,
see fig. 6 and 13
b
Gate-Source Charge
Gate-Drain Charge
Q
gs
Q
gd
t
d(on)
t
r
–
nC
ns
–
Turn-On Delay Time
Rise Time
V
GS
= 10 V
25
140
55
–
V
DD
= 250 V, I
D
= 47 A,
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
R
G
= 1.0
, see fig. 10
b
–
74
–
Drain-Source Body Diode Characteristics
D
MOSFET symbol
showing the
integral reverse
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
I
S
–
–
–
–
47
A
G
I
SM
190
S
p – n junction diode
Body Diode Voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 47 A, V
GS
= 0 V
b
–
–
–
–
–
1.5
940
21
–
V
ns
μC
A
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Body Diode Recovery Current
Forward Turn-On Time
620
14
Q
rr
T
J
= 25 °C, I
F
= 47 A, dI/dt = 100 A/μs
b
I
RRM
t
on
38
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
400 μs; duty cycle
2 %.
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
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2
VBZP50N50S
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1000
1000
100
10
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
100
10
°
T =
150 C
J
BOTTOM4.5V
1
°
T =
25 C
J
1
4.5V
0.1
20µs PULSE WIDTH
V
= 50V
DS
°
T =
25 C
J
20µs PULSE WIDTH
0.01
0.1
0.1
1
10
100
4
5
6
7
8
9
10 11 12
V
, Drain-to-Source Voltage (V)
V
, Gate-to-Source Voltage (V)
DS
GS
Fig. 3 – Typical Transfer Characteristics
Fig. 1 – Typical Output Characteristics
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
100
10
VGS
15V
48A
=
I
D
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM4.5V
4.5V
1
20µs PULSE WIDTH
°
V
=
1
0V
GS
T =
150 C
J
0.1
0.1
-60 -40 -20
0
20 40 60 80
100 120 140 160
°
1
10
100
T ,
Junction Temperature (
C)
J
V
, Drain-to-Source Voltage (V)
DS
Fig. 2 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
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VBZP50N50S
1000
100
10
1000000
V
C
= 0V,
f = 1 MHZ
= C
+ C
, C
GS
SHORTED
iss
gs
gd ds
C
= C
100000
10000
1000
100
rss
gd
C
= C
+ C
ds gd
oss
°
T =
150 C
J
Ciss
°
T =
25 C
J
Coss
Crss
1
V
= 0 V
GS
10
0.1
0.2
0.7
1.2
1.7
2.2
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
1000
20
I
D
=
48A
OPERATION IN THIS AREA LIMITED
V
V
V
= 400V
= 250V
= 100V
BY R
DS
DS
DS
DS(on)
15
10
5
100
10
1
10us
100us
1ms
°
T =
25 C
J
10ms
C
°
T =
150 C
Single Pulse
0
0
50
100
150
200
250
300
350
10
100
1000
Q ,
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig. 8 – Maximum Safe Operating Area
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
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4
VBZP50N50S
R
D
V
DS
50
40
30
20
10
0
V
GS
D.U.T.
R
G
+
V
–
DD
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Fig. 10a – Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
25
50
75
100
125
°
150
T ,
Case Temperature (
C)
C
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 10b – Switching Time Waveforms
1
D = 0.50
0.1
0.20
0.10
0.05
P
2
DM
0.01
0.02
0.01
t
1
SINGLE PULSE
(THERMAL RESPONSE)
t
2
Notes:
1. Duty factor D
=
t
/ t
1
2. Peak T
=
P
x Z
+ T
C
J
DM
thJC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
VBZP50N50S
V
DS
15 V
t
p
Driver
L
V
DS
D.U.T
R
G
+
–
V
A
DD
I
AS
I
AS
20 V
t
p
0.01
Ω
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
2000
I
D
TOP
22A
30A
BOTTOM 47A
1500
1000
500
0
25
50
75
100
125
150
°
Starting T
, Junction Temperature
( C)
J
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 k
Ω
Q
G
10 V
12 V
0.2 µF
0.3 µF
Q
GS
Q
GD
+
–
V
DS
D.U.T.
V
G
V
GS
3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
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6
VBZP50N50S
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
Circuit layout con
s
ideration
s
•
Low
s
tray inductance
•
G
round plane
D.U.T.
•
Low leakage inductance
current tran
s
former
–
+
–
–
+
R
g
•
dV/dt controlled by R
g
•
Driver
s
ame type a
s
D.U.T.
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
+
–
V
DD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 14 – For N-Channel
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TO-274AA (High Voltage)
A
A
B
E
D2
E1
E4
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25)
M
M
B A
b4
b2
Lead Tip
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
A
MIN.
4.70
1.50
2.25
1.30
1.80
3.00
0.38
19.80
MAX.
MIN.
MAX.
0.209
0.098
0.104
0.063
0.087
0.128
0.035
0.819
DIM.
D1
D2
E
MIN.
15.50
0.70
MAX.
16.10
MIN.
MAX.
0.634
0.051
0.634
0.547
5.30
2.50
2.65
1.60
2.20
3.25
0.89
20.80
0.185
0.059
0.089
0.051
0.071
0.118
0.015
0.780
0.610
0.028
0.594
0.524
A1
A2
b
1.30
16.10
13.90
15.10
13.30
E1
e
b2
b4
c
(1)
D
5.45 BSC
0.215 BSC
L
13.70
1.00
2.00
14.70
1.60
3.00
0.539
0.039
0.079
0.579
0.063
0.118
L1
R
ECN: X17-0056-Rev. B, 27-Mar-17
DWG: 5975
Notes
•
•
Dimensioning and tolerancing per ASME Y14.5M-1994
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at
the outer extremes of the plastic body
Outline conforms to JEDEC
®
outline to TO-274AA
•
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8
Disclaimer
All products due to improve reliability, function or design or for other reasons, product specifications and
data are subject to change without notice.
Taiwan VBsemi Electronics Co., Ltd., branches, agents, employees, and all persons acting on its or their
representatives (collectively, the “
T
aiwan VBsemi”), assumes no responsibility for any errors, inaccuracies or
incomplete data contained in the table or any other any disclosure of any information related to the
product.(www.VBsemi.com)
Taiwan VBsemi makes no guarantee, representation or warranty on the product for any particular purpose of
any goods or continuous production.
T
o
t
he maximum extent permitted by applicable law on
T
aiwan VBsemi
relinquished: (1) any application and all liability arising out of or use of any products; (2) any and all liability,
including but not limited to special, consequential damages or incidental ; (3) any and all implied warranties,
including a particular purpose, non-infringement and merchantability guarantee.
Statement on certain types of applications are based on knowledge of the product is often used in a typical
application of the general product VBsemi
T
aiwan demand that the Taiwan VBsemi of. Statement on whether the
product is suitable for a particular application is non-binding. It is the customer’s responsibility to verify specific
product features in the products described in the specification is appropriate for use in a particular application.
Parameter data sheets and technical specifications can be provided may vary depending on the application and
performance over time. All operating parameters, including typical parameters must be made by customer’s
technical experts validated for each customer application. Product specifications do not expand or modify
T
aiwan
VBsemi purchasing terms and conditions, including but not limited to warranty herein.
Unless expressly stated in writing,
T
aiwan VBsemi products are not intended for use in medical, life saving,
or life sustaining applications or any other application. Wherein VBsemi product failure could lead to personal
injury or death, use or sale of products used in
T
aiwan VBsemi such applications using client did not express their
own risk. Contact your authorized
T
aiwan VBsemi people who are related to product design applications and
other terms and conditions in writing.
The information provided in this document and the company’s products without a license, express or implied,
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names and trademarks referred to herein are trademarks of their respective representatives will be all.
Material Category Policy
Taiwan VBsemi Electronics Co., Ltd., hereby certify that all of the products are determined to be
oHS compliant and meets the definition of restrictions under Directive of the European Parliament
2011/65 / EU, 2011 Nian. 6. 8 Ri Yue restrict the use of certain hazardous substances in electrical and
electronic equipment (EEE) – modification, unless otherwise specified as inconsistent.(www.VBsemi.com)
Please note that some documents may still refer to Taiwan VBsemi RoHS Directive 2002/95 / EC. We
confirm that all products identified as consistent with the Directive 2002/95 / EC European Directive
2011/65 /.
Taiwan VBsemi Electronics Co., Ltd. hereby certify that all of its products comply identified as
halogen-free halogen-free standards required by the JEDEC JS709A. Please note that some Taiwanese
VBsemi documents still refer to the definition of IEC 61249-2-21, and we are sure that all products
conform to confirm compliance with IEC 61249-2-21 standard level JS709A.
