Vishay-Intertech-IRF840SPBF

Part #Vishay-Intertech-IRF840SPBF
Download 
Vishay-Intertech-IRF840SPBF
IRF840S, SiHF840S  
Vishay Siliconix  
Power MOSFET  
FEATURES  
• Surface-mount  
D
D

2

PAK (TO-263)  
• Available in tape and reel  
• Dynamic dV/dt rating  
• Repetitive avalanche rated  
• Fast switching  
Available  
Available  
G
• Ease of paralleling  
• Simple drive requirement  
• Material
 
categorization: for definitions of compliance  
D
G
S
S
Note  
N-Channel MO
S
FET  
*
This datasheet provides information about parts that are  
RoHS-compliant and / or parts that are non RoHS-compliant.
 
For  
example, parts with lead (Pb) terminations are not RoHS-compliant.  
Please see the information / tables in this datasheet for details  
PRODUCT SUMMARY  
V

DS

(V)  
DESCRIPTION  
500  
Third generation power MOSFETs from Vishay provide the  
designer with the best combination of fast switching,  
ruggedized device design, low on-resistance and  
cost-effectiveness.  
The D

2

PAK (TO-263) is a surface-mount power package  
capable of accommodating die size up to HEX-4. It provides  
the highest power capability and the lowest possible  
on-resistance in any existing surface-mount package. The  
D

2

PAK (TO-263) is suitable for high current applications  
because of its low internal connection resistance and can  
dissipate up to 2.0 W in a typical surface mount application.  
R

DS(on)

(
Ω
)  
V

GS

= 10 V  
0.85  
Q

g

max. (nC)  
63  
9.3  
Q

gs

(nC)  

gd

(nC)  
Q
32  
Configuration  
Single  
ORDERING INFORMATION  
Package  
D

2

PAK (TO-263)  
SiHF840S-GE3  
IRF840SPbF  
D

2

PAK (TO-263)  
SiHF840STRL-GE3

a  

IRF840STRLPbF

a  

D

2

PAK (TO-263)  
SiHF840STRR-GE3

a  

IRF840STRRPbF

a  

Lead (Pb)-free and Halogen-free  
Lead (Pb)-free  
Note  
a. See
 
device orientation  
ABSOLUTE MAXIMUM RATINGS
(T

C

= 25 °C, unless otherwise noted)  
PARAMETER  
SYMBOL  
LIMIT  
500  
UNIT  
Drain-Source Voltage  
Gate-Source Voltage  
V

DS  

V
V

GS  

20  
T

C

= 25 °C  
8.0  
Continuous Drain Current  
V

GS

at 10 V  
I

D  

T

C

= 100 °C  
5.1  
A
Pulsed Drain Current

a  

I

DM  

32  
Linear Derating Factor  
1.0  
W/°C  
Linear Derating Factor (PCB mount)

e  

Single Pulse Avalanche Energy

b  

Avalanche Current

a  

0.025  
510  
E

AS  

I

AR  

mJ  
A
8.0  
Repetitive Avalanche Energy

a  

E

AR  

13  
mJ  
Maximum Power Dissipation  
T

C

= 25 °C  
125  
P

D  

W
V/ns  
°C  
Maximum Power Dissipation (PCB mount)

e  

Peak Diode Recovery dV/dt

c  

T

A

= 25 °C  
3.1  
dV/dt  
3.5  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak temperature)

d  

T

J

, T

stg  

-55 to +150  
300  
For 10 s  
Notes  
a. Repetitive
 
rating; pulse width limited by maximum junction temperature (see fig. 11)  
b. V

DD

= 50 V, starting T

J

= 25 °C, L = 14 mH, R

g

= 25
Ω
, I

AS

= 8.0 A (see fig. 12)  
c. I

SD

≤
8.0 A, dI/dt
≤
100 A/μs, V

DD

≤
V

DS

, T

J

≤
150 °C  
d. 1.6
 
mm from case  
e. When
 
mounted on 1″ square PCB (FR-4 or G-10 material)  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
1
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

IRF840S, SiHF840S  
Vishay Siliconix  
THERMAL RESISTANCE RATINGS  
PARAMETER  
SYMBOL  
TYP.  
MAX.  
UNIT  
Maximum Junction-to-Ambient  
R

thJA  

R

thJA  

R

thJC  

–
62  
Maximum Junction-to-Ambient  
(PCB mount)

a  

–
–
40  
°C/W  
Maximum Junction-to-Case (Drain)  
1.0  
Note  
a. When
 
mounted on 1″ square PCB (FR-4 or G-10 material)  
SPECIFICATIONS
(T

J

= 25 °C, unless otherwise noted)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
Static  
Drain-Source Breakdown Voltage  
V

DS  

Δ
V

DS

/T

J  

V

GS(th)  

I

GSS  

V

GS

= 0, I

D

= 250 μA  
Reference to 25 °C, I

D

= 1 mA  
V

DS

= V

GS

, I

D

= 250 μA  
500  
–
–
–
V
V/°C  
V
V

DS

Temperature Coefficient  
–
2.0  
–
0.78  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
–
–
–
–
–
–
4.0  
100  
25  
250  
0.85  
–
V

GS  

V

DS

= 500 V, V

GS

= 0 V  
V

DS

= 400 V, V

GS

= 0 V, T

J

= 125 °C  
V

GS

= 10 V  
I

D

= 4.8 A

b  

V

DS

= 50 V, I

D

= 4.8 A

b  

=
20 V  
nA  
–
Zero Gate Voltage Drain Current  
I

DSS  

μA  
–
Drain-Source On-State Resistance  
Forward Transconductance  
Dynamic  
R

DS(on)  

g

fs  

–
Ω
4.9  
S
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Turn-On Delay Time  
Rise Time  
C

iss  

C

oss  

C

rss  

Q

g  

–
–
–
–
–
–
–
–
–
–
1300  
310  
120  
–
–
–
V

GS

= 0 V,  

DS

= 25 V,  
f = 1.0 MHz, see fig. 5  
V
pF  
–
63  
9.3  
32  
–
I

D

= 8.0 A, V

DS

= 400 V,  
see fig. 6 and 13

b  

Q

gs  

Q

gd  

t

d(on)  

t

r  

V

GS

= 10 V  
–
nC  
–
14  
23  
49  
20  
–
V

DD

= 250 V, I

D

= 8.0 A,  
ns  
R

g

= 9.1
Ω
, R

D

= 31
Ω
, see fig. 10

b  

Turn-Off Delay Time  
Fall Time  
t

d(off)  

t

f  

–
–
D
Between lead,  
Internal Drain Inductance  
Internal Source Inductance  
L

D  

–
4.5  
–
6 mm (0.25″) from  
package and center of  
die contact  
nH  
G
L

S  

R

g  

–
7.5  
–
–
S
Gate Input Resistance  
f = 1 MHz, open drain  
0.6  
2.8  
Ω
Drain-Source Body Diode Characteristics  
MOSFET symbol  
showing the  
integral reverse  
D
Continuous Source-Drain Diode Current  
Pulsed Diode Forward Current

a  

I

S  

–
–
–
–
8.0  
32  
A
G
I

SM  

p – n junction diode  
S
Body Diode Voltage  
V

SD  

t

rr  

T

J

= 25 °C, I

S

= 8.0 A, V

GS

= 0 V

b  

–
–
–
–
2.0  
970  
8.9  
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Forward Turn-On Time  
460  
4.2  
ns  
μC  
T

J

= 25 °C, I

F

= 8.0 A, dI/dt = 100 A/μs

b  

Q

rr  

t

on  

Intrinsic turn-on time is negligible (turn-on is dominated by L

S

and L

D

)  
Notes  
a. Repetitive
 
rating; pulse width limited by maximum junction temperature (see fig. 11)  
b. Pulse
 
width
≤
300 μs; duty cycle
≤
2 %  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
2
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

IRF840S, SiHF840S  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
V

GS  

15 V  
10 V  
I

D

= 8.0 A  
V

GS

= 10 V  
T
o
p  
8.0 V  
7.0 V  
6.0 V  
5.5 V  
5.0 V  
10

1  

Bottom 4.5 V  
4.5 V  
10

0  

20 µs Pulse Width  
T

C

=
25 °C  
10

0  

10

1  

– 60 – 40 – 20  
0
20 40 60 80
 
100 120 140 160  
V

DS

, Drain-to-Source Voltage (V)  
91071_01  
T

J

,
Junction
T
e
mperature (°C)  
91071_04  
Fig. 1 – Typical Output Characteristics, T

C

= 25 °C  
Fig. 4 – Normalized On-Resistance vs. Temperature  
2500  
V

GS  

V

GS

= 0
V
, f = 1
M
Hz  
T
o
p  
15 V  
10 V  
8.0 V  
7.0 V  
6.0 V  
5.5 V  
5.0 V  
C

iss

= C

gs

+ C

gd

, C

ds

Shorted  
C

rss

= C

gd  

C

oss

= C

ds

+ C

gd  

10

1  

2000  
C

iss  

1500  
1000  
500  
4.5 V  
Bottom 4.5
 
V  
C

oss  

10

0  

C

rss  

20 µs Pulse Width  
T

C

=
150 °C  
0
10

0  

10

1  

10

0  

10

1  

V

DS

,

Drain-to-Source Voltage (V)  
91071_02  
V

DS

,
Drain-to-Source Voltage (V)  
91071_05  
Fig. 2 – Typical Output Characteristics, T

C

= 150 °C  
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage  
20  
I

D

= 8.0 A  
150
°
C  
10

1  

V

DS

= 400 V  

DS

= 250 V  

DS

= 100 V  
16  
12  
V
V
25
°
C  
8
4
0
10

0  

20 µs Pulse Width  
V

DS

=
50 V  
For test circuit  
see figure 13  
4
5
6
7
8
9
10  
0
30  
75  
15  
45  
60  
91071_03  
V

GS

,

Gate-to-Source Voltage (V)  
Fig. 3 – Typical Transfer Characteristics  
Q

G

,
T
o
tal Gate Charge (nC)  
91071_06  
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
3
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

IRF840S, SiHF840S  
Vishay Siliconix  
8.0  
6.0  
4.0  
2.0  
0.0  
10

1  

150
°
C  
25
°
C  
V

GS

= 0 V  
1.4  
1.2  
10

0  

0.4  
0.6  
0.8  
1.0  
25  
50  
75  
100  
125  
150  
V

SD

, Source-to-Drain Voltage (V)  
91071_07  
T

C

, Case
T
e
mperature (°C)  
91071_09  
Fig. 7 – Typical Source-Drain Diode Forward Voltage  
Fig. 9 – Maximum Drain Current vs. Case Temperature  
R

D  

10

2  

V

DS  

Operation in this area limited  
5
by R

DS(on)  

V

GS  

D.U.T.  
10
µs  
2
R

g  

+
V
10  
–
DD  
100
µs  
5
10 V  
Pulse width
≤
1 µs  
Duty factor
≤
0.1 %  
2
1
ms  
1
10
ms  
Fig. 10a – Switching Time Test Circuit  
5
T

C

= 25
°
C  
T

J

= 150
°
C  
2
V

DS  

Single Pulse  
0.1  
0.1  
90 %  
2
5
2
5
2
5
2
5
2
5
10

3  

10  
10

4  

10

2  

1
V

DS

, Drain-to-Source Voltage (V)  
91071_08  
Fig. 8 – Maximum Safe Operating Area  
10 %  
V

GS  

t

d(on)

t

r  

t

d(off)

t

f  

Fig. 10b – Switching Time Waveforms  
10  
1
D = 0.5  
0.2  
0.1  
0.1  
10

-2  

10

-3  

P

DM  

0.05  
0.02  
0.01  
Single Pulse  
(Thermal Response)  
t

1  

t

2  

Notes:  
1. Duty
 
Factor, D = t

1

/t

2  

2. Peak
 
T

j

= P

DM

x Z

thJC

+ T

C  

10

-5  

10

-4  

10

-3  

10

-2  

0.1  
1
10  
10

2  

t

1

, Rectangular Pulse Duration (s)  
91071_11  
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
4
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

IRF840S, SiHF840S  
Vishay Siliconix  
L
V

DS  

V

DS  

Vary t

p

to obtain  
required I

AS  

t

p  

V

DD  

D.U.T.  
I

AS  

R

g  

+
–
V

DD  

V

DS  

10 V  
0.01
Ω  
t

p  

I

AS  

Fig. 12a – Unclamped Inductive Test Circuit  
Fig. 12b – Unclamped Inductive Waveforms  
1200  
1000  
800  
I

D  

3.6 A  
5.1 A  
T
o
p  
Bottom 8.0
 
A  
600  
400  
200  
V

DD

= 50 V  
0
125  
Starting T
 
, Junction
T
e
mperature (°C)  
25  
75  
100  
150  
50  
91071_12c  
J
Fig. 12c – Maximum Avalanche Energy vs. Drain Current  
Current regulator  
Same type as D.U.T.  
50 k
Ω  
Q

G  

10 V  
12 V  
0.2 µF  
0.3 µF  
Q

GS  

Q

GD  

+
–
V

DS  

D.U.T.  
V

G  

V

GS  

3 mA  
Charge  
I

G  

I

D  

Current sampling resistors  
Fig. 13a – Basic Gate Charge Waveform  
Fig. 13b – Gate Charge Test Circuit  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
5
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

IRF840S, SiHF840S  
Vishay Siliconix  
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit  
+
Circuit layout con
s
ideration
s  
•
Low
s
tray inductance  
•
G
round plane  
D.U.T.  
•
Low leakage inductance  
current tran
s
former  
–
+
–
–
+
R

g  

•
dV/dt controlled by R

g  

+
•
Driver
s
ame type a
s
D.U.T.  
•
I

S
D

controlled by duty factor “D”  
•
D.U.T. – device under te
s
t  
V

DD  

–
Driver gate drive  
P.W.  
P.W.  
D =  
Period  
Period  
V

GS

= 10 V

a  

D.U.T. l

S
D

waveform  
D.U.T. V

D
S

waveform  
Rever
s
e  
recovery  
current  
Body diode forward  
current  
dI/dt  
Diode recovery  
dV/dt  
V

DD  

Re-applied  
voltage  
Body diode forward drop  
Inductor current  
I

S
D  

Ripple
≤
5 %  
Note  
a. V

GS

= 5 V for logic level device
s  
Fig. 14 – For N-Channel  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see

.  
S21-0904-Rev. E, 30-Aug-2021  
Document Number: 91071  
6
For technical questions, contact:

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH
A
T

Package Information  
Vishay Siliconix  
TO-263AB (HIGH VOLTAGE)  
A
B
(Dat
u
m A)  
3
4
A
A
E
c2  
H
L1  
4
Ga
u
ge  
plane  
0° to
8
°  
4
B
5
Detail A  
Seating plane  
D
H
L
C
C
A1  
L3  
L4  
Detail “A”  
1
2
3
L2  
Rotated 90° CW  
B
B
scale
8
:1  
A
2 x
b
2  
2 x
b  
c
E
M
M
B
0.010  
A
M
0.004  
B
2 x e  
Base  
metal  
5
D1  
4
Plating  
(c)  
b
1,
b
3  
5
c1  
(
b
,
b
2)  
Lead tip  
4
E1  
Section B – B and C – C  
Scale: none  
V
ie
w
A – A  
MILLIMETERS  
INCHES  
MILLIMETERS  
INCHES  
DIM.  
A
MIN.  
4.06  
0.00  
0.51  
0.51  
1.14  
1.14  
0.38  
0.38  
1.14  
8.38  
MAX.  
4.83  
0.25  
0.99  
0.89  
1.78  
1.73  
0.74  
0.58  
1.65  
9.65  
MIN.  
0.160  
0.000  
0.020  
0.020  
0.045  
0.045  
0.015  
0.015  
0.045  
0.330  
MAX.  
0.190  
0.010  
0.039  
0.035  
0.070  
0.068  
0.029  
0.023  
0.065  
0.380  
DIM.  
D1  
E
MIN.  
6.86  
MAX.  
MIN.  
MAX.  
–
10.67  
–
0.270  
0.380  
0.245  
–
0.420  
–
A1  
b
9.65  
6.22  
E1  
e
b1  
b2  
b3  
c
2.54 BSC  
0.100 BSC  
H
14.61  
15.88  
2.79  
1.65  
1.78  
0.575  
0.625  
0.110  
0.066  
0.070  
L
1.78  
0.070  
L1  
L2  
L3  
L4  
–
–
–
–
c1  
c2  
D
0.25 BSC  
0.010 BSC  
4.78  
5.28  
0.188  
0.208  
ECN: S-82110-Rev. A, 15-Sep-08  
D
W
G: 5970  
Notes  
1. Dimensioning and tolerancing per ASME Y14.5M-1994.  
2. Dimensions are shown in millimeters (inches).  
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the  
outmost extremes of the plastic body at datum A.  
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.  
5. Dimension b1 and c1 apply to base metal only.  
6. Datum A and B to be determined at datum plane H.  
7. Outline conforms to JEDEC outline to TO-263AB.  
Document Number: 91364  
Revision: 15-Sep-08  
1

AN826  
Vishay Siliconix  
2
RECOMMENDED MINIMUM PADS FOR D PAK:
 
3-Lead  
0.420  
(10.668)  
0.145  
(3.683)  
0.135  
(3.429)  
0.200  
0.050  
(5.080)  
(1.257)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
Document Number:
 
73397  
11-Apr-05  
1

Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product  
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in  
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating  
parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts.  
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited  
to the warranty expressed therein.  
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and  
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of  
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.  
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website  
or for that of subsequent links.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please  
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED  
Revision: 09-Jul-2021  
Document Number: 91000  
1