Vishay-Intertech-IRFB13N50APBF
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IRFB13N50A
Vishay Siliconix
Power MOSFET
FEATURES
D
• Lower gate charge Q
g
results in simpler drive
requirements
TO-220AB
Available
• Improved gate, avalanche, and dynamic dV/dt
Available
ruggedness
G
• Fully characterized capacitance and avalanche
voltage
S
D
• Material
categorization: for definitions of compliance
S
G
N-Channel MO
S
FET
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant.
For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
V
DS
(V)
500
R
DS(on)
(
Ω
)
V
GS
= 10 V
0.450
APPLICATIONS
Q
g
max. (nC)
81
20
36
• Switch mode power supply (SMPS)
• Uninterruptible power supplies
• High speed power switching
Q
gs
(nC)
gd
(nC)
Q
Configuration
Single
ORDERING INFORMATION
Package
TO-220AB
Lead (Pb)-free
IRFB13N50APbF
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
500
30
UNIT
Drain-source voltage
Gate-source voltage
V
DS
V
V
GS
T
C
= 25 °C
14
Continuous drain current
V
GS
at 10 V
I
D
T
C
= 100 °C
9.1
A
Pulsed drain current
a
I
DM
56
Linear derating factor
2.0
W/°C
mJ
A
Single pulse avalanche energy
b
Repetitive avalanche current
a
Repetitive avalanche energy
a
Maximum power dissipation
E
AS
I
AR
560
14
E
AR
25
mJ
W
T
C
= 25 °C
P
D
250
9.2
Peak diode recovery dV/dt
c
dV/dt
T
J
, T
stg
V/ns
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
d
-55 to +150
300
10
°C
For 10 s
lbf · in
N · m
Mounting torque
6-32 or M3 screw
1.1
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting
T
J
= 25 °C, L = 5.7 mH, R
g
= 25
Ω
, I
AS
=14 A, dV/dt = 7.6 V/ns (see fig. 12a)
c. I
SD
≤
14 A, dI/dt
≤
250 A/μs, V
DD
≤
V
DS
, T
J
≤
150 °C
d. 1.6
mm from case
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFB13N50A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
62
UNIT
Maximum junction-to-ambient
Case-to-sink, flat, greased surface
Maximum junction-to-case (drain)
R
thJA
R
thCS
R
thJC
–
0.50
–
–
°C/W
0.50
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-source breakdown voltage
V
DS
Δ
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
500
–
–
–
V
V/°C
V
V
DS
temperature coefficient
–
2.0
–
0.55
Gate-source threshold voltage
Gate-source leakage
–
–
–
–
–
–
4.0
100
25
V
GS
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 8.4 A
b
V
DS
= 50 V, I
D
= 8.4 A
=
30 V
nA
–
Zero gate voltage drain current
I
DSS
μA
–
250
0.450
–
Drain-source on-state resistance
Forward transconductance
Dynamic
R
DS(on)
g
fs
–
Ω
8.1
S
Input capacitance
C
iss
C
oss
C
rss
–
–
1910
290
11
2730
82
160
–
–
–
V
GS
= 0 V,
Output capacitance
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
Reverse transfer capacitance
–
–
pF
V
DS
= 1.0 V, f = 1.0 MHz
–
–
Output capacitance
C
oss
V
GS
= 0 V
V
DS
= 400 V, f = 1.0 MHz
–
–
Effective output capacitance
Total gate charge
C
oss
eff.
Q
g
V
DS
= 0 V to 400 V
c
–
–
–
81
20
36
–
I
D
= 14 A, V
DS
= 400 V,
see fig. 6 and 13
b
Gate-source charge
Gate-drain charge
Q
gs
Q
gd
t
d(on)
t
r
–
–
nC
–
–
Turn-on delay time
Rise time
V
GS
= 10 V
–
15
39
39
31
–
V
DD
= 250 V, I
D
= 14 A,
R
g
= 7.5
Ω
,
–
–
ns
Turn-off delay time
Fall time
t
d(off)
t
f
–
–
see fig. 10
b
–
–
Gate input resistance
Drain-Source Body Diode Characteristics
R
g
f = 1 MHz, open drain
0.5
2.1
Ω
D
MOSFET symbol
showing the
integral reverse
p – n junction diode
Continuous source-drain diode current
Pulsed diode forward current
a
I
S
–
–
–
–
14
56
A
G
I
SM
S
Body diode voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 14 A, V
GS
= 0 V
b
–
–
–
–
–
1.5
550
6.5
31
V
ns
μC
A
Body diode reverse recovery time
Body diode reverse recovery charge
Body diode reverse recovery current
Forward turn-on time
370
4.4
21
T
J
= 25 °C, I
F
= 14 A,
Q
rr
T
J
= 125 °C, dI/dt = 100 A/μs
b
I
RRM
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse
width
≤
300 μs; duty cycle
≤
2 %
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFB13N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
2
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
I
D
= 14 A
V
GS
= 10 V
GS
T
o
p
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
10
1
Bottom
4.5 V
0.1
10
-2
20 µs Pulse Width
T
J
=
25 °C
10
2
– 60 – 40 – 20
0
20 40 60 80
100 120 140 160
0.1
1
10
T
J
,
Junction
T
e
mperature (°C)
91095_04
V
DS
, Drain-to-Source Voltage (V)
91095_01
91095_02
91095_03
Fig. 1 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
10
2
10
1
10
5
V
GS
15 V
10 V
V
GS
= 0
V
, f = 1
M
Hz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
T
o
p
10
4
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
C
oss
= C
ds
+ C
gd
C
iss
10
3
C
oss
4.5 V
Bottom
10
2
C
rss
10
20 µs Pulse Width
T
J
=
150 °C
0.1
1
10
2
1
10
10
2
10
3
0.1
1
10
V
DS
,
Drain-to-Source Voltage (V)
V
DS
,
Drain-to-Source Voltage (V)
91095_05
Fig. 2 – Typical Output Characteristics
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
10
2
10
1
12.5
I
D
= 14 A
V
DS
= 400 V
10
7.5
5
T
J
= 150
°
C
V
DS
= 250 V
V
DS
= 100 V
T
J
= 25
°
C
2.5
0
20 µs Pulse Width
DS
=
50 V
V
0.1
4
6
8
10
12
14
16
0
24
60
12
36
48
V
GS
,
Gate-to-Source Voltage (V)
Q
G
,
T
o
tal Gate Charge (nC)
91095_06
Fig. 3 – Typical Transfer Characteristics
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFB13N50A
Vishay Siliconix
R
D
10
2
10
V
DS
V
GS
D.U.T.
R
G
T
J
= 150
°
C
+
–
V
DD
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
T
J
= 25
°
C
1
Fig. 10a – Switching Time Test Circuit
V
GS
= 0 V
1.4
1.1
0.1
V
DS
0.2
0.5
0.8
90 %
V
SD
, Source-to-Drain Voltage (V)
91095_07
Fig. 7 – Typical Source-Drain Diode Forward Voltage
10 %
V
GS
10
3
t
d(on)
t
r
t
d(off)
t
f
Operation in this area limited
by R
DS(on)
Fig. 10b – Switching Time Waveforms
10
2
100
µs
1
ms
10
1
10
ms
T
C
= 25
°
C
T
J
= 150
°
C
Single Pulse
0.1
10
10
2
10
3
10
4
V
DS
, Drain-to-Source Voltage (V)
Fig. 8 – Maximum Safe Operating Area
91095_08
15
12
9
6
3
0
25
50
75
100
125
150
T
C
, Case
T
e
mperature (°C)
91095_09
Fig. 9 – Maximum Drain Current vs. Case Temperature
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFB13N50A
Vishay Siliconix
1
D = 0.50
0.20
0.1
0.10
0.05
P
DM
0.02
0.01
Single Pulse
(Thermal Response)
10
-2
t
1
t
2
Notes:
1. Duty
Factor, D = t
1
/t
2
2. Peak
T
J
= P
DM
x Z
thJC
+ T
C
10
-3
10
-5
10
-4
10
-3
10
-2
0.1
1
t
1
, Rectangular Pulse Duration (s)
91095_11
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
1150
I
D
15 V
TOP
6.3A
8.9A
14A
920
BOTTOM
Driver
L
V
DS
690
D.U.T.
R
G
+
–
V
A
DD
I
AS
20 V
460
230
0
0.01
Ω
t
p
Fig. 12a – Unclamped Inductive Test Circuit
V
DS
t
p
25
50
75
100
125
150
Starting Tj, Junction Temperature (°C)
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
I
AS
Fig. 12b – Unclamped Inductive Waveforms
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFB13N50A
Vishay Siliconix
Current regulator
Same type as D.U.T.
50 k
Ω
Q
G
V
GS
12 V
0.2 µF
0.3 µF
Q
GS
Q
GD
+
V
DS
D.U.T.
–
V
G
V
GS
3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
Circuit layout con
s
ideration
s
D.U.T.
•
•
•
Low
s
tray inductance
G
round plane
Low leakage inductance
current tran
s
former
–
+
–
–
+
R
g
•
•
dV/dt controlled by R
g
Driver
s
ame type a
s
D.U.T.
+
–
V
DD
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
Driver gate drive
P.W.
D =
Period
Period
P.W.
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
S21-0340-Rev. C, 12-Apr-2021
Document Number: 91095
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
TO-220-1
A
E
F
Ø P
1
3
2
*
M
b(1)
C
b
e
J(1)
e(1)
MILLIMETERS
INCHES
DIM.
MIN.
4.24
0.69
1.14
0.36
14.33
9.96
2.41
4.88
1.14
6.10
2.41
13.36
3.33
3.53
2.54
MAX.
4.65
1.02
1.78
0.61
15.85
10.52
2.67
5.28
1.40
6.71
2.92
14.40
4.04
3.94
3.00
MIN.
MAX.
0.183
0.040
0.070
0.024
0.624
0.414
0.105
0.208
0.055
0.264
0.115
0.567
0.159
0.155
0.118
A
b
0.167
0.027
0.045
0.014
0.564
0.392
0.095
0.192
0.045
0.240
0.095
0.526
0.131
0.139
0.100
b(1)
c
D
E
e
e(1)
F
H(1)
J(1)
L
L(1)
Ø P
Q
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
•
Revison: 04-Nov-2021
Document Number: 66542
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 01-Jan-2022
Document Number: 91000
1
