Vishay-Intertech-IRFP460APBF
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IRFP460A, SiHFP460A
Vishay Siliconix
Power MOSFET
FEATURES
• Low Gate Charge Q
g
Results in Simple Drive
Requirement
• Improved
Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
PRODUCT SUMMARY
V
DS
(V)
500
A
v
aila
b
le
R
DS(on)
(
Ω
)
V
GS
= 10 V
0.27
RoHS*
Q
g
(Max.) (nC)
105
26
COMPLIANT
Q
Q
gs
(nC)
gd
(nC)
42
Configuration
Single
• Effective
C
oss
Specified
• Compliant
to RoHS Directive 2002/95/EC
D
APPLICATIONS
TO-247
• Switch
Mode Power Supply (SMPS)
• Uninterruptable
Power Supply
• High
Speed Power Switching
G
TYPICAL SMPS TOPOLOGIES
• Full
Bridge
• PFC
Boost
S
D
S
N
-Channel MOSFET
G
ORDERING INFORMATION
Package
TO-247
IRFP460APbF
SiHFP460A-E3
IRFP460A
Lead (Pb)-free
SnPb
SiHFP460A
ABSOLUTE MAXIMUM RATINGS
T
C
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
500
V
V
GS
30
T
C
= 25 °C
20
Continuous Drain Current
V
GS
at 10 V
I
D
T
C
= 100 °C
13
A
Pulsed Drain Current
a
I
DM
80
Linear Derating Factor
2.2
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
E
AS
I
AR
960
20
E
AR
28
280
mJ
W
Maximum Power Dissipation
T
C
= 25 °C
P
D
Peak Diode Recovery dV/dt
c
dV/dt
T
J
, T
stg
3.8
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
– 55 to + 150
300
d
°C
for 10 s
6-32 or M3 screw
10
lbf · in
N · m
Mounting Torque
1.1
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting
T
J
= 25 °C, L = 4.3 mH, R
g
= 25
Ω
, I
AS
= 20 A (see fig. 12).
c. I
SD
≤
20 A, dI/dt
≤
125 A/µs, V
DD
≤
V
DS
, T
J
≤
150 °C.
d. 1.6
mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
1
IRFP460A, SiHFP460A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
40
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
R
thJA
R
thCS
R
thJC
–
0.24
–
–
°C/W
0.45
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
Δ
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 µA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 µA
500
–
–
–
V
–
2.0
–
0.61
V/°C
V
–
–
–
–
–
–
4.0
100
25
250
0.27
–
V
GS
V
DS
= 500 V, V
GS
= 0 V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 12 A
b
V
DS
= 50 V, I
D
= 12 A
b
=
30 V
nA
–
Zero Gate Voltage Drain Current
I
DSS
µA
V
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
Ω
11
S
Input Capacitance
C
iss
C
oss
C
rss
–
–
–
3100
480
18
–
–
–
V
GS
= 0 V,
DS
= 25 V,
f = 1.0 MHz, see fig. 5
Output Capacitance
V
Reverse Transfer Capacitance
pF
V
DS
= 1.0 V, f = 1.0 MHz
4430
130
140
–
Output Capacitance
C
oss
V
GS
= 0 V
V
DS
= 400 V, f = 1.0 MHz
V
DS
= 0 V to 400 V
c
Effective Output Capacitance
Total Gate Charge
C
oss
eff.
Q
g
–
–
–
–
–
–
–
105
I
D
= 20 A, V
DS
= 400 V,
see fig. 6 and 13
b
Gate-Source Charge
Gate-Drain Charge
Q
gs
Q
gd
t
d(on)
t
r
V
GS
= 10 V
–
26
42
–
nC
ns
–
Turn-On Delay Time
Rise Time
18
55
–
V
DD
= 250 V, I
D
= 20 A,
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
R
G
= 4.3
Ω
, R
D
= 13
Ω
, see fig. 10
b
45
–
39
–
Drain-Source Body Diode Characteristics
MOSFET symbol
showing the
integral reverse
p – n junction diode
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
I
S
–
–
–
–
20
80
D
A
G
I
SM
S
Body Diode Voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 20A, V
GS
= 0 V
b
–
–
–
–
1.8
710
7.5
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
480
5.0
ns
µC
T
J
= 25 °C, I
F
= 20 A, dI/dt = 100 A/µs
b
Q
rr
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
≤
300 µs; duty cycle
≤
2 %.
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
2
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
10
2
10
2
10
1
V
GS
15
V
10
V
8
.0
V
7.0
V
6.0
V
5.5
V
5.0
V
T
o
p
150
°
C
10
1
25
°
C
Bottom 4.5
V
4.5
V
20
µ
s P
u
lse
W
idth
V
DS
=
50
V
20
µ
s P
u
lse
W
idth
T
C
=
25 °C
0.1
0.1
10
10
2
4.0
5.0
6.0
7.0
8
.0
9.0
0.1
1
V
DS
, Drain-to-So
u
rce
V
oltage (
V
)
91234_01
91234_03
V
GS
,
Gate-to-So
u
rce
V
oltage (
V
)
Fig. 1 – Typical Output Characteristics
Fig. 3 – Typical Transfer Characteristics
10
2
10
1
3.0
2.5
2.0
1.5
V
GS
15
V
10
V
8
.0
V
7.0
V
6.0
V
5.5
V
5.0
V
I
D
= 20 A
T
o
p
V
GS
= 10
V
Bottom 4.5
V
1.0
0.5
4.5
V
20
µ
s P
u
lse
W
idth
T
C
=
150 °C
0.0
10
10
2
60
120
140 160
1
– 60 – 40 – 20
0
20 40
8
0 100
V
DS
,
Drain-to-So
u
rce
V
oltage (
V
)
T
J
,
J
u
nction
T
e
mperat
u
re (°C)
91234_02
91234_04
Fig. 2 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
3
IRFP460A, SiHFP460A
Vishay Siliconix
10
5
10
2
10
1
V
GS
= 0
V
, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
10
4
10
3
10
2
10
150
°
C
C
iss
25
°
C
C
oss
C
rss
V
GS
= 0
V
1.2 1.4 1.6
0.1
1
10
10
2
10
3
1
1.0
0.2
0.4
0.6
0.
8
V
DS
,
Drain-to-So
u
rce
V
oltage (
V
)
V
SD
, So
u
rce-to-Drain
V
oltage (
V
)
91234_05
91234_07
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
10
3
20
I
D
= 20 A
Operation in this area limited
b
y R
DS(on)
V
DS
= 400
V
16
12
V
DS
= 250
V
10
2
V
DS
= 100
V
10
µ
s
8
100
µ
s
10
1
ms
4
T
C
= 25
°
C
T
J
= 150
°
C
Single P
u
lse
For test circ
u
it
see fig
u
re 13
10
ms
0
1
10
2
10
3
10
10
4
0
40
100
20
60
8
0
V
DS
, Drain-to-So
u
rce
V
oltage (
V
)
Q
G
,
T
o
tal Gate Charge (nC)
91234_06
91234_0
8
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 – Maximum Safe Operating Area
4
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
R
D
V
DS
V
GS
D.U.T.
20
15
10
R
G
+
–
V
DD
10
V
P
u
lse
w
idth
≤
1
µ
s
D
u
ty factor
≤
0.1
%
Fig. 10a – Switching Time Test Circuit
V
DS
5
0
90
%
25
50
75
100
125
150
10
%
T
C
, Case
T
e
mperat
u
re (°C)
91234_09
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 10b – Switching Time Waveforms
1
D = 0.5
0.1
10
-2
10
-3
0.2
0.1
P
DM
0.05
0.02
0.01
t
1
Single P
u
lse
(Thermal Response)
t
2
N
otes:
1. D
u
ty Factor, D = t
1
/t
2
2. Peak
T
j
= P
DM
x Z
thJC
+ T
C
10
-5
10
-4
10
-3
10
-2
0.1
1
t
1
, Rectang
u
lar P
u
lse D
u
ration (S)
91234_11
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
DS
15 V
t
p
Driver
L
V
DS
D.U.T.
I
AS
R
G
+
–
V
A
DD
I
AS
20 V
0.01
Ω
t
p
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
5
IRFP460A, SiHFP460A
Vishay Siliconix
2400
620
600
5
8
0
560
540
I
D
8
.9 A
13 A
Bottom 20
A
T
o
p
2000
1600
1200
8
00
400
0
125
Starting T
, J
u
nction
T
e
mperat
u
re (°C)
16
25
75
100
150
0
8
12
20
50
4
91234_12c
I
, A
v
alanche C
u
rrent (A)
91234_12d
J
A
V
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Fig. 12d – Typical Drain-to-Source Voltage vs.
Avalanche Current
C
u
rrent reg
u
lator
Same type as D.U.T.
50 k
Ω
Q
G
10
V
12
V
0.2
µ
F
0.3
µ
F
Q
GS
Q
GD
+
–
V
DS
D.U.T.
V
G
V
GS
3 mA
Charge
I
G
I
D
C
u
rrent sampling resistors
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
6
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
Circ
u
it layo
u
t considerations
•
Lo
w
stray ind
u
ctance
•
Gro
u
nd plane
D.U.T.
•
Lo
w
leakage ind
u
ctance
c
u
rrent transformer
–
+
–
–
+
R
G
•
d
V
/dt controlled
b
y R
G
+
–
•
Dri
v
er same type as D.U.T.
•
I
SD
controlled
b
y d
u
ty factor “D”
•
D.U.T. – de
v
ice
u
nder test
V
DD
Dri
v
er gate dri
v
e
P.
W
.
P.
W
.
Period
Period
D =
V
= 10
V
*
GS
D.U.T. I
w
a
v
eform
SD
Re
v
erse
reco
v
ery
c
u
rrent
Body diode for
w
ard
c
u
rrent
dI/dt
D.U.T.
V w
a
v
eform
DS
Diode reco
v
ery
d
V
/dt
V
DD
Re-applied
v
oltage
Body diode for
w
ard drop
Ripple
≤
5
%
Ind
u
ctor c
u
rrent
I
SD
*
V
GS
= 5
V
for logic le
v
el de
v
ices
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
7
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
7
M
ØP
M
D B
(Datum B)
ØP1
B
R/2
A2
A
E/2
S
Ø k
3
D2
Q
4
4
2 x R
(2)
D1
D
L
4
D
1
2
3
Thermal pad
5
L1
C
4
E1
A
See view B
M
M
0.01 D
B
2 x b2
3 x b
View A – A
C
2 x
e
A1
b4
M
M
0.10 C
A
(b1, b3, b5)
(b, b2, b4)
Planting
Base metal
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D D
E
E
(c)
c1
C
C
(4)
Section C – C, D – D, E – E
View B
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MIN.
0.020
0.602
0.540
DIM.
A
A1
A2
b
b1
b2
b3
b4
b5
c
MIN.
4.58
2.21
1.17
0.99
0.99
1.53
1.65
2.42
2.59
0.38
0.38
19.71
13.08
MAX.
5.31
2.59
2.49
1.40
1.35
2.39
2.37
3.43
3.38
0.86
0.76
20.82
–
MIN.
0.180
0.087
0.046
0.039
0.039
0.060
0.065
0.095
0.102
0.015
0.015
0.776
0.515
MAX.
0.209
0.102
0.098
0.055
0.053
0.094
0.093
0.135
0.133
0.034
0.030
0.820
–
DIM.
D2
E
E1
e
Ø k
L
L1
N
Ø P
Ø P1
Q
R
S
MIN.
0.51
15.29
13.72
MAX.
MAX.
0.051
0.625
–
1.30
15.87
–
5.46 BSC
0.254
0.215 BSC
0.010
14.20
3.71
16.25
4.29
0.559
0.146
0.640
0.169
7.62 BSC
3.51
0.300 BSC
3.66
7.39
5.69
5.49
0.138
–
0.209
0.178
0.144
0.291
0.224
0.216
–
c1
D
D1
5.31
4.52
5.51 BSC
0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″).
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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statements about the suitability of products for a particular application.
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
