Vishay-Intertech-IRFP460LCPBF
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IRFP460LC, SiHFP460LC
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• Ultra
Low Gate Charge
• Reduced
Gate Drive Requirement
• Enhanced
30 V V
GS
Rating
• Reduced
C
iss
, C
oss
, C
rss
• Isolated
Central Mounting Hole
• Dynamic
dV/dt Rating
V
DS
(V)
500
A
v
aila
b
le
R
DS(on)
(
Ω
)
V
GS
= 10 V
0.27
RoHS*
Q
g
(Max.) (nC)
120
32
COMPLIANT
Q
Q
gs
(nC)
gd
(nC)
49
Configuration
Single
• Repetitive
Avalanche Rated
• Lead
(Pb)-free Available
D
DESCRIPTION
TO-247
This new series of low charge Power MOSFETs achieve
significantly lower gate charge over conventional MOSFETs.
Utilizing advanced Power MOSFETs technology the device
improvements allow for reduced gate drive requirements,
faster switching speeds and increased total system savings.
These device improvements combined with the proven
ruggedness and reliabiltity of Power MOSFETs offer the
designer a new standard in power transistors for switching
applications.
G
S
D
S
N
-Channel MOSFET
G
The TO-247 package is preferred for commercial-industrial
applications where higher power levels preclude the use of
TO-220 devices. The TO-247 is similar but superior to the
earlier TO-218 package because its isolated mounting hole.
ORDERING INFORMATION
Package
TO-247
IRFP460LCPbF
SiHFP460LC-E3
IRFP460LC
Lead (Pb)-free
SnPb
SiHFP460LC
ABSOLUTE MAXIMUM RATINGS
T
C
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
500
V
V
GS
30
T
C
= 25 °C
20
Continuous Drain Current
V
GS
at 10 V
I
D
T
C
= 100 °C
12
A
Pulsed Drain Current
a
I
DM
80
Linear Derating Factor
2.2
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
E
AS
I
AR
960
20
E
AR
28
280
mJ
W
Maximum Power Dissipation
T
C
= 25 °C
P
D
Peak Diode Recovery dV/dt
c
dV/dt
T
J
, T
stg
3.5
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
– 55 to + 150
300
d
°C
for 10 s
10
lbf · in
N · m
Mounting Torque
6-32 or M3 screw
1.1
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 25 V, starting T
J
= 25 °C, L = 4.3 mH, R
G
= 25
Ω
, I
AS
= 20 A (see fig. 12).
c. I
SD
≤
20 A, dI/dt
≤
160 A/µs, V
DD
≤
V
DS
, T
J
≤
150 °C.
d. 1.6
mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
1
IRFP460LC, SiHFP460LC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
R
thJA
R
thCS
R
thJC
–
0.24
–
–
–
°C/W
0.45
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
Δ
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 µA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 µA
500
–
–
–
V
V/°C
V
–
2.0
–
0.59
–
–
–
–
–
–
4.0
100
25
250
0.27
–
V
GS
V
DS
= 500 V, V
GS
= 0 V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 12 A
b
V
DS
= 50 V, I
D
= 12 A
b
=
20 V
nA
–
Zero Gate Voltage Drain Current
I
DSS
µA
V
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
Ω
12
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
C
iss
C
oss
C
rss
Q
g
–
–
–
–
–
–
–
–
–
–
3600
440
39
–
–
V
GS
= 0 V,
V
DS
= 25 V,
–
pF
f = 1.0 MHz, see fig. 5
–
120
32
49
–
I
D
= 20 A, V
DS
= 400 V,
see fig. 6 and 13
b
Q
gs
Q
gd
t
d(on)
t
r
V
GS
= 10 V
–
nC
–
18
77
40
43
–
V
DD
= 250 V, I
D
= 20 A
ns
R
G
= 4.3
Ω
, R
D
= 12
Ω
, see fig. 10
b
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
–
–
D
Between lead,
Internal Drain Inductance
L
D
L
S
–
–
5.0
13
–
–
6 mm (0.25″) from
package and center of
die contact
nH
G
Internal Source Inductance
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
MOSFET symbol
showing the
integral reverse
p – n junction diode
D
I
S
–
–
–
–
20
80
A
G
Pulsed Diode Forward Current
a
I
SM
S
Body Diode Voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 20 A, V
GS
= 0 V
b
–
–
–
–
1.8
860
9.9
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
570
6.6
ns
µC
T
J
= 25 °C, I
F
= 20 A, dI/dt = 100 A/µs
b
Q
rr
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
≤
300 µs; duty cycle
≤
2 %.
2
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
Fig. 1 – Typical Output Characteristics, T
C
= 25 °C
Fig. 3 – Typical Transfer Characteristics
Fig. 2 – Typical Output Characteristics, T
= 150 °C
Fig. 4 – Normalized On-Resistance vs. Temperature
C
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
3
IRFP460LC, SiHFP460LC
Vishay Siliconix
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 – Maximum Safe Operating Area
4
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
–
DD
10
V
P
u
lse
w
idth
≤
1
µ
s
D
u
ty factor
≤
0.1
%
Fig. 10a – Switching Time Test Circuit
V
DS
90
%
10
%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 10b – Switching Time Waveforms
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
V
DS
V
DS
V
ary t
p
to o
b
tain
re
qu
ired I
AS
t
p
V
DD
D.U.T.
R
G
+
–
V
DD
V
DS
I
AS
10
V
0.01
Ω
t
p
I
AS
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
5
IRFP460LC, SiHFP460LC
Vishay Siliconix
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
C
u
rrent reg
u
lator
Same type as D.U.T.
50 k
Ω
Q
G
V
GS
12
V
0.2
µ
F
0.3
µ
F
Q
GS
Q
GD
+
–
V
DS
D.U.T.
V
G
V
GS
3 mA
Charge
I
G
I
D
C
u
rrent sampling resistors
Fig. 13b – Gate Charge Test Circuit
Fig. 13a – Basic Gate Charge Waveform
6
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
Circ
u
it layo
u
t considerations
•
Lo
w
stray ind
u
ctance
•
Gro
u
nd plane
D.U.T.
•
Lo
w
leakage ind
u
ctance
c
u
rrent transformer
–
+
–
–
+
R
G
•
d
V
/dt controlled
b
y R
G
+
–
•
Dri
v
er same type as D.U.T.
•
I
SD
controlled
b
y d
u
ty factor “D”
•
D.U.T. – de
v
ice
u
nder test
V
DD
Dri
v
er gate dri
v
e
P.
W
.
P.
W
.
Period
Period
D =
V
= 10
V
*
GS
D.U.T. I
w
a
v
eform
SD
Re
v
erse
reco
v
ery
c
u
rrent
Body diode for
w
ard
c
u
rrent
dI/dt
D.U.T.
V w
a
v
eform
DS
Diode reco
v
ery
d
V
/dt
V
DD
Re-applied
v
oltage
Body diode for
w
ard drop
Ripple
≤
5
%
Ind
u
ctor c
u
rrent
I
SD
*
V
GS
= 5
V
for logic le
v
el de
v
ices
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
7
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
7
M
ØP
M
D B
(Datum B)
ØP1
B
R/2
A2
A
E/2
S
Ø k
3
D2
Q
4
4
2 x R
(2)
D1
D
L
4
D
1
2
3
Thermal pad
5
L1
C
4
E1
A
See view B
M
M
0.01 D
B
2 x b2
3 x b
View A – A
C
2 x
e
A1
b4
M
M
0.10 C
A
(b1, b3, b5)
(b, b2, b4)
Planting
Base metal
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D D
E
E
(c)
c1
C
C
(4)
Section C – C, D – D, E – E
View B
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MIN.
0.020
0.602
0.540
DIM.
A
A1
A2
b
b1
b2
b3
b4
b5
c
MIN.
4.58
2.21
1.17
0.99
0.99
1.53
1.65
2.42
2.59
0.38
0.38
19.71
13.08
MAX.
5.31
2.59
2.49
1.40
1.35
2.39
2.37
3.43
3.38
0.86
0.76
20.82
–
MIN.
0.180
0.087
0.046
0.039
0.039
0.060
0.065
0.095
0.102
0.015
0.015
0.776
0.515
MAX.
0.209
0.102
0.098
0.055
0.053
0.094
0.093
0.135
0.133
0.034
0.030
0.820
–
DIM.
D2
E
E1
e
Ø k
L
L1
N
Ø P
Ø P1
Q
R
S
MIN.
0.51
15.29
13.72
MAX.
MAX.
0.051
0.625
–
1.30
15.87
–
5.46 BSC
0.254
0.215 BSC
0.010
14.20
3.71
16.25
4.29
0.559
0.146
0.640
0.169
7.62 BSC
3.51
0.300 BSC
3.66
7.39
5.69
5.49
0.138
–
0.209
0.178
0.144
0.291
0.224
0.216
–
c1
D
D1
5.31
4.52
5.51 BSC
0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″).
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
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Such statements are not binding
statements about the suitability of products for a particular application.
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particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
