Vishay-Intertech-IRFPS40N50LPBF
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PD- 95141
IRFPS40N50LPbF
SMPS MOSFET
HEXFET
®
Power MOSFET
Applications
•
Zero Voltage Switching SMPS
•
Telecom and Server Power Supplies
•
Uninterruptible Power Supplies
•
Motor Control applications
•
Lead-Free
Trr
typ.
V
DSS
R
DS(on)
I
D
typ.
500V
170ns 46A
0.087Ω
Features and Benefits
•
SuperFast body diode eliminates the need for external
diodes in ZVS applications.
•
Lower Gate charge results in simpler drive requirements.
•
Enhanced dv/dt capabilities offer improved ruggedness.
•
Higher Gate voltage threshold offers improved noise
immunity
.
Super
–
247™
Absolute Maximum Ratings
Parameter
Max.
46
Units
A
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V
29
I
DM
180
540
Pulsed Drain Current
P
D
@T
C
= 25°C
Power Dissipation
W
Linear Derating Factor
Gate-to-Source Voltage
4.3
W/°C
V
V
GS
±30
dv/dt
T
J
Peak Diode Recovery dv/dt
Operating Junction and
34
V/ns
-55 to
+ 150
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
––– –––
46
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
A
showing the
I
Pulsed Source Current
––– ––– 180
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
T =
25°C, I
= 46A, V
= 0V
J S GS
Diode Forward Voltage
Reverse Recovery Time
––– ––– 1.5
––– 170 250
––– 220 330
V
SD
T =
25°C, I
= 46A
ns
rr
J
F
T
J
= 125°C, di/dt = 100A/µs
Q
T =
25°C, I
= 46A, V
= 0V
––– 705
1060 nC
Reverse Recovery Charge
rr
J
S
GS
T
J
= 125°C, di/dt = 100A/µs
––– 1.3
2.0
I
RRM
T =
25°C
J
Reverse Recovery Current
Forward Turn-On Time
––– 9.0 –––
A
t
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
1
09/14/04
IRFPS40N50LPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
500
–––
–––
V
V
GS
= 0V, I
D
= 250µA
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
Breakdown Voltage Temp. Coefficient
––– 0.60 –––
Static Drain-to-Source On-Resistance
––– 0.087
0.100
V/°C
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 28A
Ω
V
V
GS(th)
Gate Threshold Voltage
3.0
–––
–––
–––
–––
–––
–––
–––
–––
5.0
50
V
DS
= V
GS
, I
D
= 250µA
I
DSS
Drain-to-Source Leakage Current
µA
mA
nA
V
DS
= 500V, V
GS
= 0V
2.0
100
V
DS
= 400V, V
GS
= 0V, T
J
= 125°C
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= 30V
––– -100
V
GS
= -30V
––– 0.90 –––
Ω
f = 1MHz, open drain
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 46A
I
D
= 46A
21
–––
–––
–––
–––
27
–––
380
80
S
Q
g
–––
–––
–––
–––
–––
–––
–––
Q
gs
Q
gd
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC
V
DS
= 400V
190
–––
–––
–––
–––
V
GS
= 10V, See Fig. 7 & 15
V
DD
= 250V
t
d(on)
t
r
170
50
ns
I
D
= 46A
t
d(off)
Turn-Off Delay Time
Fall Time
R
G
= 0.85
Ω
GS
= 10V, See Fig. 14a & 14b
t
f
69
V
C
iss
Input Capacitance
––– 8110 –––
V
GS
= 0V
C
oss
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Effective Output Capacitance
–––
–––
960
130
–––
–––
V
DS
= 25V
C
rss
ƒ = 1.0MHz, See Fig. 5
C
oss
V
GS
= 0V, VDS = 1.0V, ƒ = 1.0MHz
V
GS
= 0V, VDS = 400V, ƒ = 1.0MHz
V
GS
= 0V,V
DS
= 0V to 400V
––– 11200 –––
pF
C
oss
–––
–––
–––
240
440
310
–––
–––
–––
C
oss
eff.
C
oss
eff. (ER)
(Energy Related)
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
920
46
Units
mJ
A
Symbol
Single Pulse Avalanche Energy
E
AS
Avalanche Current
I
AR
Repetitive Avalanche Energy
E
AR
54
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.23
–––
40
Units
Junction-to-Case
R
θ
JC
R
θ
CS
R
θ
JA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.24
–––
°C/W
Notes:
Pulse width
≤
400µs; duty cycle
≤
2%.
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff.(ER) is a fixed capacitance that stores the same energy
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
Starting T
J
= 25°C, L = 0.86mH, R
G
= 25
Ω
,
I
AS
= 46A. (See Figure 12).
.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
R
θ
is measured at T
J
approximately 90°C
I
SD
≤
46A, di/dt
≤
550A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
150°C.
,
2
IRFPS40N50LPbF
1000
1000
100
10
VGS
VGS
TOP
15V
TOP
15V
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
100
10
BOTTOM4.5V
BOTTOM4.5V
4.5V
1
4.5V
1
0.1
20µs PULSE WIDTH
20µs PULSE WIDTH
°
T =
150 C
J
°
T =
25 C
J
0.1
0.1
0.01
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
3.0
47A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
°
T =
150 C
J
°
T =
25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
=
1
0V
GS
0.1
-60 -40 -20
0
20 40 60 80
100 120 140 160
°
4
5
6
7
8
9
10
11
T ,
Junction Temperature (
C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
vs. Temperature
3
IRFPS40N50LPbF
40
35
30
25
20
15
10
5
1000000
V
= 0V,
f = 1 MHZ
= C
+ C
, C
GS
C
SHORTED
iss
gs
gd ds
C
= C
100000
10000
1000
100
rss
gd
C
= C
+ C
ds gd
oss
Ciss
Coss
Crss
10
0
1
10
100
1000
0
100
V
200
300
400
500
600
V
, Drain-to-Source Voltage (V)
Drain-to-Source Voltage (V)
DS
DS,
Fig 5.
Typical Capacitance vs.
Fig 6.
Typ. Output Capacitance
Drain-to-Source Voltage
Stored Energy vs. V
DS
1000
100
10
20
15
10
5
I =
47A
D
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
°
T =
150 C
J
°
T =
25 C
J
1
V
= 0 V
GS
0.1
0.2
0
0.7
1.2
1.7
2.2
0
100
200
300
400
V
,Source-to-Drain Voltage (V)
SD
Q ,
Total Gate Charge (nC)
G
Fig 8.
Typical Source-Drain Diode
Fig 7.
Typical Gate Charge vs.
Forward Voltage
Gate-to-Source Voltage
4
IRFPS40N50LPbF
R
D
50
40
30
20
10
0
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
°
T ,
Case Temperature (
C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9.
Maximum Drain Current vs.
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
2
DM
0.01
0.001
0.02
0.01
t
1
SINGLE PULSE
(THERMAL RESPONSE)
t
2
Notes:
1. Duty factor D
=
t
/ t
1
2. Peak T
=
P
x Z
+ T
C
J
DM
thJC
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFPS40N50LPbF
1000
2000
1500
1000
500
0
I
D
OPERATION IN THIS AREA LIMITED
TOP
21A
30A
BY R
DS(on)
BOTTOM 46A
100
10
1
10us
100us
1ms
°
T =
25 C
10ms
C
J
°
T =
150 C
Single Pulse
10
100
1000
25
50
75
100
125
150
V
, Drain-to-Source Voltage (V)
DS
°
Starting T
, Junction Temperature(
C)
J
Fig 13.
Maximum Avalanche Energy
Fig 12.
Maximum Safe Operating
vs. Drain Current
Area
15V
V
(BR)DSS
t
p
DRIVER
L
V
DS
D.U.T
AS
R
G
+
–
V
DD
I
A
20V
0.01
Ω
t
p
I
AS
Fig 14b.
Unclamped Inductive Waveforms
Fig 14a.
Unclamped Inductive Test Circuit
Current Regulator
Same Type as D.U.
T
.
Q
G
50K
Ω
.2
µ
F
12V
V
GS
.3
µ
F
Q
Q
GD
GS
+
V
DS
D.U.
T
.
–
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 15b.
Basic Gate Charge Waveform
Fig 15a.
Gate Charge Test Circuit
6
IRFPS40N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
–
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 16.
For N-Channel HEXFET
®
Power MOSFETs
7
IRFPS40N50LPbF
Case Outline and Dimensions — Super-247
Super-247 (TO-274AA) Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE “C”
PART NUMBER
INTERNATIONAL RECTIFIER
LOGO
IRFPS37N50A
719C
17
89
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
ASSEMBLY LOT CODE
Note: “P” in assembly line position
indicates “Lead-Free”
TOP
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
