Vishay-Intertech-SI1416EDH-T1-GE3
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New Product
Si1416EDH
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
V
DS
(V)
R
DS(on)
(
Ω
)
I
D
(A)
a
3.9
Q
g
(Typ.)
Definition
0.058 at V
GS
= 10 V
0.064 at V
GS
= 4.5 V
0.077 at V
GS
= 2.5 V
•
•
•
•
TrenchFET
®
Power MOSFET
Typical ESD Protection 1500 V in HBM
100 % R
g
Tested
30
3.9
3.5 nC
3.9
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
Portable Devices such as Smart Phones and Tablet PCs
•
SOT-363
SC-70 (6-LEADS)
– DC/DC Converters
– High Frequency Switching
– OVP Switch
D
D
D
G
1
2
3
6
D
D
S
– Load Switch
Markin
g
Code
G
5
4
AR XX
Lot Tracea
b
ility
and Date Code
Part # Code
Top
V
ie
w
Orderin
g
Information:
Si1416EDH-T1-GE3 (Lead (P
b
)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Parameter
Symbol
Limit
30
Unit
V
DS
Drain-Source Voltage
Gate-Source Voltage
V
V
GS
12
T
C
= 25 °C
3.9
a
3.9
a
3.9
a, b, c
3.9
a, b, c
15
2.3
a
1.3
b, c
2.8
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Continuous Drain Current (T
J
= 150 °C)
I
D
A
I
DM
I
S
Pulsed Drain Current (t = 300 µs)
T
C
= 25 °C
T
A
= 25 °C
Continuous Source-Drain Diode Current
T
C
= 25 °C
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
1.8
Maximum Power Dissipation
P
D
W
1.56
b, c
1.0
b, c
T
J
, T
stg
Operating Junction and Storage
T
e
mperature Range
– 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
b, d
Symbol
Typical
60
Maximum
Unit
R
thJA
t
≤
5 s
80
45
°C/W
R
thJF
Steady State
34
Maximum Junction-to-Foot (Drain)
Notes:
a. Package limited, T
C
= 25 °C.
b. Surface mounted on 1″ x 1″ FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 125 °C/W.
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
1
This document is subject to change without notice.
New Product
Si1416EDH
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
V
DS
T
e
mperature Coefficient
V
DS
V
GS
= 0
V
,
I
D
= 250 µA
I
D
= 250 µA
30
V
mV/°C
V
Δ
V
DS
/T
J
Δ
V
GS(th)
/T
J
V
GS(th)
34
V
GS(th)
T
e
mperature Coefficient
– 3.3
Gate-Source Threshold Voltage
0.6
10
1.4
0.5
20
1
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0
V
,
V
GS
DS
= 0
V
,
V
GS
=
=
4.5 V
12 V
Gate-Source Leakage
I
GSS
V
µA
V
DS
= 30
V
,
V
GS
= 0 V
DS
= 30
V
,
V
GS
= 0
V
,
T
J
= 55 °C
V
DS
≥
5
V
,
V
GS
= 10 V
V
GS
= 10
V
,
I
D
= 3.1 A
V
GS
= 4.5
V
,
I
D
= 2 A
Zero Gate Voltage Drain Current
On-State Drain Current
a
I
DSS
10
V
I
D(on)
A
Ω
S
0.047
0.052
0.062
13
0.058
0.064
0.077
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
= 2.5
V
,
I
D
= 1 A
Forward
T
r
ansconductance
a
g
fs
V
DS
= 15
V
,
I
D
= 3.1 A
Dynamic
b
V
DS
= 15
V
,
V
GS
= 10
V
,
I
D
= 4 A
7.5
3.5
1.8
0.7
3.3
20
12
T
o
tal Gate Charge
Q
g
5.5
nC
Gate-Source Charge
Q
gs
Q
gd
R
g
V
DS
= 15
V
,
V
GS
= 4.5
V
,
I
D
= 4 A
f = 1 MHz
Gate-Drain Charge
Gate Resistance
0.6
6.6
40
120
50
90
5
Ω
T
u
rn-On Delay Time
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Rise Time
60
V
DD
= 15
V
,
R
L
= 4.7
Ω
I
D
≅
3.2 A, V
GEN
= 4.5
V
,
R
g
= 1
Ω
T
u
rn-Off DelayTime
25
Fall Time
45
ns
T
u
rn-On Delay Time
1.5
30
Rise Time
60
30
100
V
DD
= 15
V
,
R
L
= 4.7
Ω
I
D
≅
3.2 A, V
GEN
= 10
V
,
R
g
= 1
Ω
T
u
rn-Off DelayTime
15
Fall Time
50
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
3.9
15
A
I
S
= 3.2 A, V
GS
= 0 V
0.87
10
1.2
20
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Q
rr
t
a
4
10
I
F
= 3.2 A, dI/dt = 100 A/µs, T
J
= 25 °C
5.3
4.6
ns
t
b
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
This document is subject to change without notice.
New Product
Si1416EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T =
25 °C, unless otherwise noted)
A
1.500
1.200
0.900
0.600
0.300
0.000
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
T
J
= 150
°
C
T
J
= 25
°
C
T
J
= 25
°
C
0
3
6
9
12
15
0
3
6
9
12
15
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-Source Voltage (V)
Gate Current vs. Gate-to-Source Voltage
Gate Current vs. Gate-to-Source Voltage
15
12
9
5
4
3
2
1
0
V
GS
= 10 V thru 3 V
V
GS
= 2 V
T
C
= 25
°
C
6
T
C
= 125
°
C
3
T
C
= – 55
°
C
1.5 2.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.200
0.160
0.120
0.080
0.040
0.000
450
400
350
300
250
200
150
100
50
C
iss
V
GS
= 2.5 V
V
GS
= 4.5 V
V
GS
= 10 V
C
rss
C
oss
0
0
5
10
15
20
25
30
0
3
6
9
12
15
V
DS
– Drain-to-Source Voltage (V)
I
D
– Drain Current (A)
On-Resistance vs. Drain Current
Transconductance
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
3
This document is subject to change without notice.
New Product
Si1416EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T =
25 °C, unless otherwise noted)
A
10
8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
D
= 4 A
V
DS
= 7.5 V
V
GS
= 10 V, 4.5 V, I
D
= 3.2 A
6
V
DS
= 15 V
V
GS
= 2.5 V, I
D
= 1 A
V
DS
= 24 V
4
2
0
0
2
4
6
8
– 50
– 25
0
25
50
75
100 125 150
Q
g
– Total Gate Charge (nC)
T
J
– Junction Temperature (
°
C)
Gate Charge
Normalized On-Resistance vs. Junction Temperature
0.160
100
10
1
0.140
0.120
0.100
0.080
0.060
0.040
0.020
0.000
I
D
= 3.2 A
T
J
= 150
°
C
T
J
= 125
°
C
T
J
= 25
°
C
T
J
= 25
°
C
0.1
0
2
4
6
8
10
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
– Gate-to-Source Voltage (V)
V
SD
– Source-to-Drain Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
10
8
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
6
4
I
D
= 250 μA
2
0
0.001
0.01
0.1
1
10
100
1000
– 50
– 25
0
25
50
75
100 125 150
Time (s)
T
J
– Temperature (
°
C)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
4
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
This document is subject to change without notice.
New Product
Si1416EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T =
25 °C, unless otherwise noted)
A
100
Limited by R
DS(on)
*
10
1
100 μs
1 ms
10 ms
0.1
100 ms
1 s, 10 s
DC
T
A
= 25
°
C
Single Pulse
BVDSS Limited
10
0.01
0.1
1
100
V
DS
– Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
6
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
Package Limited
0
25
50
75
100
125
150
25
50
75
100
125
150
T
L
– Lead Temperature (
°
C)
T
L
– Lead Temperature (
°
C)
Power Derating
Current Derating*
* The power dissipation P
D
is based on T
J(max)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
5
This document is subject to change without notice.
New Product
Si1416EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T =
25 °C, unless otherwise noted)
A
1
Duty Cycle = 0.5
0.2
0.1
N
otes:
P
DM
0.1
0.05
t
1
t
2
t
t
0.02
1
2
1. D
u
ty Cycle, D =
2. Per Unit Base = R
= 125 °C/
W
thJA
(t)
3. T
– T
= P
Z
JM
A
DM thJA
Single Pulse
0.01
4. S
u
rface Mo
u
nted
0.0001
0.001
0.01
0.1
1
10 100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
Document Number: 67580
S11-0611-Rev. A, 04-Apr-11
This document is subject to change without notice.
Package Information
Vishay Siliconix
SCĆ70: 6ĆLEADS
MILLIMETERS
INCHES
Dim Min
Nom Max Min Nom
Max
6
1
5
2
4
3
0.90
–
–
1.10
0.10
1.00
0.30
0.25
2.20
2.40
1.35
0.035
–
–
–
0.043
0.004
0.039
0.012
0.010
0.087
0.094
0.053
A
E
E
1
–
A
1
0.80
–
0.031
0.006
0.004
0.071
0.071
0.045
–
A
2
0.15
–
–
b
-B-
0.10
–
–
c
e
b
1.80
2.00
2.10
1.25
0.65BSC
1.30
0.20
7
_
Nom
0.079
0.083
0.049
0.026BSC
0.051
0.008
7
_
Nom
D
e
1
1.80
E
-A-
D
1.15
E
1
c
e
1.20
1.40
0.30
0.047
0.004
0.055
0.012
A
e
1
A
2
1
0.10
L
L
A
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
Document Number: 71154
06-Jul-01
1
AN815
Vishay Siliconix
Single-Channel LITTLE FOOT
R
SC-70 6-Pin MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
EVALUATION BOARDS ꢀ SINGLE SC70-6
The new single 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance
as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small
to medium load applications where a
miniaturized package is required. Devices in this package
come in a range
of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the single-channel version.
The evaluation board (EVB) measures 0.6 inches by
0.5 inches. The copper pad traces are the same as in Figure 2.
The board allows examination from the outer pins to 6-pin DIP
connections, permitting test sockets to be used in evaluation
testing. See
Figure 3.
52 (mil)
BASIC PAD PATTERNS
6
5
2
4
3
See Application Note 826,
Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
pad layout and dimensions. These pad patterns are sufficient
for the low to medium power applications for which this
package is intended. Increasing the drain pad pattern yields a
reduction in
thermal resistance and is a preferred footprint.
The availability of four drain leads rather than the traditional
single drain lead allows a better thermal path from the package
to the PCB and external environment.
96 (mil)
71 (mil)
26 (mil)
1
13 (mil)
0, 0 (mil)
18 (mil)
26 (mil)
PIN-OUT
16 (mil)
Figure
1 shows the pin-out description and Pin 1
FIGURE 2.
SC-70 (6 leads) Single
identification.The pin-out of this device allows the use of four
pins as drain leads, which helps to reduce on-resistance and
junction-to-ambient thermal resistance.
SOT-363
SC-70 (6-LEADS)
The thermal performance of the single 6-pin SC-70 has been
measured on the EVB, comparing both the copper and
Alloy 42
leadframes. This test was first conducted on the
traditional Alloy 42 leadframe and was then repeated using the
1-inch
2
PCB with dual-side copper coating.
D
D
G
1
2
3
6
5
D
D
S
4
T
o
p View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
Document Number:
71334
12-Dec-03
1
AN815
Vishay Siliconix
Front of Board SC70-6
Back of Board SC70-6
vishay.com
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(Package Performance)
COOPER LEADFRAME
Room Ambient 25
_
C
Elevated Ambient 60
_
C
The junction to foot thermal resistance is a useful method of
comparing different packages thermal performance.
T
J(max)
*
T
A
T
J(max)
*
T
A
P
D
+
P
D
+
R
q
JA
R
q
JA
150
o
C
*
60
o
C
124
o
C
ń
W
150
o
C
*
25
o
C
124
o
C
ń
W
P
D
+
P
D
+
A helpful way of presenting the thermal performance of the
6-Pin SC-70 copper leadframe device is to compare it to the
traditional Alloy 42 version.
P
D
+
726 mW
P
D
+
1.01 W
As can be seen from the calculations above, the compact 6-pin
SC-70 copper leadframe LITTLE FOOT power MOSFET can
handle up to 1 W under the stated conditions.
Thermal performance for the 6-pin SC-70 measured as
junction-to-foot thermal resistance, where the “foot” is the
drain lead of the device at the bottom where it meets the PCB.
The junction-to-foot thermal resistance is typically 40
_
C/W in
the copper leadframe and 163
_
C/W in the Alloy 42 leadframe
— a four-fold improvement. This improved performance is
obtained by the enhanced thermal conductivity of copper over
Alloy 42.
Testing
To
f
urther aid comparison of copper and Alloy 42 leadframes,
Figure 5 illustrates single-channel 6-pin SC-70 thermal
performance on two different board sizes and two different pad
patterns. The measured steady-state values of R
q
JA
for the
two leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Power Dissipation
Alloy 42
Copper
The typical R
q
JA
for the single 6-pin SC-70 with copper
leadframe is 103
_
C/W steady-state, compared with 212
_
C/W
for the Alloy 42 version. The figures are based on the 1-inch
2
FR4 test board. The following example shows how the thermal
resistance impacts power dissipation for the two different
leadframes at varying ambient temperatures.
1) Minimum recommended pad pattern on
the EVB board V (see Figure 3.
329.7
_
C/W
208.5
_
C/W
2
2) Industry standard 1-inch
PCB with
211.8
_
C/W
103.5
_
C/W
maximum copper both sides.
The results indicate that designers can reduce thermal
resistance (R
q
JA
) by 36% simply by using the copper
leadframe device rather than the Alloy 42 version. In this
example, a 121
_
C/W reduction was achieved without an
increase in board area. If increasing in board size is feasible,
a further 105
_
C/W reduction could be obtained by utilizing a
1-inch
2
square PCB area.
ALLOY 42 LEADFRAME
Room Ambient 25
_
C
Elevated Ambient 60
_
C
T
J(max)
*
T
A
R
q
JA
T
J(max)
*
T
A
R
q
JA
P
D
+
P
D
+
The copper leadframe versions have the following suffix:
150
o
C
*
25
o
C
212
o
C
ń
W
150
o
C
*
25
o
C
212
o
C
ń
W
P
D
+
P
D
+
Single:
Dual:
Si14xxEDH
Si19xxEDH
P
D
+
590 mW
P
D
+
425 mW
Complementary: Si15xxEDH
Document Number:
71334
12-Dec-03
2
AN815
Vishay Siliconix
250
200
150
400
320
240
Alloy
42
Alloy
42
160
80
100
50
Copper
100
Copper
0
0
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
10
10
10
10
10
1
10
1000
10
10
10
10
10
1
10
100
1000
Time (Secs)
Time (Secs)
2
FIGURE 4.
Leadframe Comparison on EVB
FIGURE 5.
Leadframe Comparison on Alloy 42 1-inch
PCB
Document Number:
71334
12-Dec-03
3
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
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