Vishay-Intertech-SI1422DH-T1-GE3

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Vishay-Intertech-SI1422DH-T1-GE3
New Product  
Si1422DH  
Vishay Siliconix  
N-Channel 12 V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
•
Halogen-free According to IEC 61249-2-21  
V

DS

(V)  
R

DS(on)

(
Ω
)  
I

D

(A)

a  

Q

g

(Typ.)  
Definition  
TrenchFET

®

Power MOSFET  
0.026 at V

GS

= 4.5 V  
0.030 at V

GS

= 2.5 V  
0.036 at V

GS

= 1.8 V  
4
4
4
•
•
•
100 % R
 
Tested  
12  
7.5 nC  
g
Compliant to RoHS Directive 2002/95/EC  
APPLICATIONS  
•
Load Switch, PA Switch and Battery Switch for Portable  
Devices  
SOT-363  
SC-70 (6-LEADS)  
•
•
High Frequency dc-to-dc Converters  
Low On-Resistance Switching  
D
D
D
G
1
2
3
6
D
D
S
Marking Code  
5
4
AO XX  
G
Lot Traceability  
and Date Code  
Part # Code  
Top View  
Ordering Information:
Si1422DH-T1-GE3 (Lead (Pb)-free and Halogen-free)  
S
N-Channel MOSFET  
ABSOLUTE MAXIMUM RATINGS
T =
 
25 °C, unless otherwise noted  
A
Parameter  
Symbol  
Limit  
12  
Unit  
V

DS  

Drain-Source Voltage  
Gate-Source Voltage  
V
V

GS  

8
4

a  

4

a  

T

F

= 25 °C  
T

F

= 70 °C  
T

A

= 25 °C  
T

A

= 70 °C  
Continuous Drain Current (T

J

= 150 °C)  
I

D  

4

b, c  

4

b, c  

20  
2.3

a  

1.3

b, c  

A
I

DM  

I

S  

Pulsed Drain Current  
T

F

= 25 °C  
T

A

= 25 °C  
T

F

= 25 °C  
T

F

= 70 °C  
T

A

= 25 °C  
T

A

= 70 °C  
Continuous Source-Drain Diode Current  
2.8  
1.8  
1.56

b, c  

Maximum Power Dissipation  
P

D  

W
1.0

b, c  

Operating Junction and Storage
T
e
mperature Range  
Soldering Recommendations (Peak
T
e
mperature)  
T

J

, T

stg  

– 55 to 150  
260  
°C  
THERMAL RESISTANCE RATINGS  
Parameter  
Maximum Junction-to-Ambient

b, d  

Symbol  
R

thJA  

Typical  
Maximum  
Unit  
t
≤
5 s  
60  
34  
80  
45  
°C/W  
Steady State  
R

thJF  

Maximum Junction-to-Foot (Drain)  
Notes:  
a. T

F

= 25 °C, package limited.  
b. Surface mounted on 1″ x 1″ FR4 board.  
c. t
 
= 5 s.  
d. Maximum under steady state conditions is 125 °C/W.  
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  
1

New Product  
Si1422DH  
Vishay Siliconix  
SPECIFICATIONS
T =
 
25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
V

DS  

Δ
V

DS

/T

J  

Δ
V

GS(th)

/T

J  

V

GS(th)  

V

GS

= 0
V
,
I

D

= 250 µA  
I

D

= 250 µA  
Drain-Source Breakdown Voltage  
12  
V
V

DS

T
e
mperature Coefficient  
11  
mV/°C  
V

GS(th)

T
e
mperature Coefficient  
– 2.7  
V

DS

= V

GS

, I

D

= 250 µA  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
0.4  
15  
1.0  
100  
1
V
I

GSS  

V

DS

= 0
V
,
V

GS  

=
8 V  
nA  
V

DS

= 12
V
,
V

GS

= 0 V  
V

DS

= 12
V
,
V

GS

= 0
V
,
T

J

= 55 °C  
V

DS

≥
5
V
,
V

GS

= 4.5 V  
V

GS

= 4.5
V
,
I

D

= 5.1 A  
V

GS

= 2.5
V
,
I

D

= 4.7 A  
V

GS

= 1.8
V
,
I

D

= 2.5 A  
V

DS

= 10
V
,
I

D

= 5.1 A  
I

DSS  

Zero Gate Voltage Drain Current  
On-State Drain Current

a  

µA  
A
10  
I

D(on)  

0.021  
0.024  
0.029  
30  
0.026  
0.030  
0.036  
Drain-Source On-State Resistance

a  

Forward
T
r
ansconductance

a  

R

DS(on)  

Ω
g

fs  

S
Dynamic

b  

C

iss  

C

oss  

C

rss  

Input Capacitance  
Output Capacitance  
Reverse
T
r
ansfer Capacitance  
725  
195  
90  
V

DS

= 6
V
,
V

GS

= 0
V
, f = 1
M
Hz  
V

DS

= 6
V
,
V

GS

= 8
V
,
I

D

= 9 A  
pF  
13.1  
7.5  
1.1  
0.8  
2.5  
10  
20  
12  
Q

g  

T
o
tal Gate Charge  
nC  
Q

gs  

Q

gd  

R

g  

Gate-Source Charge  
Gate-Drain Charge  
Gate Resistance  
T
u
rn-On Delay Time  
Rise Time  
V

DS

= 6
V
,
V

GS

= 4.5
V
,
I

D

= 9 A  
f = 1 MHz  
0.5  
5
Ω
t

d(on)  

t

r  

t

d(off)  

t

f  

t

d(on)  

t

r  

t

d(off)  

t

f  

15  
15  
30  
15  
10  
15  
30  
15  
10  
V

DD

= 6
V
,
R

L

= 0.83
Ω  
I

D

≅
7.2 A, V

GEN

= 4.5
V
,
R

g

= 1
Ω  
T
u
rn-Off Delay Time  
Fall Time  
20  
10  
ns  
T
u
rn-On Delay Time  
Rise Time  
5
10  
V

DD

= 6
V
,
R

L

= 0.83
Ω  
I

D

≅
7.2 A, V

GEN

= 8
V
,
R

g

= 1
Ω  
T
u
rn-Off Delay Time  
Fall Time  
20  
10  
Drain-Source Body Diode Characteristics  
Continuous Source-Drain Diode Current  
Pulse Diode Forward Current  
I

S  

I

SM  

V

SD  

t

rr  

T

C

= 25 °C  
4
20  
1.2  
30  
8
A
I

S

= 7.2 A, V

GS

= 0 V  
Body Diode Voltage  
0.8  
15  
4
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Reverse Recovery Fall Time  
ns  
nC  
Q

rr  

t

a  

I

F

= 7.2 A, dI/dt = 100 A/µs, T

J

= 25 °C  
8
ns  
t

b  

Reverse Recovery Rise Time  
7
Notes:  
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
2
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  

New Product  
Si1422DH  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted  
20  
10  
8
V
= 5 V thru 2 V  
GS  
16  
12  
8
V
= 1.5 V  
GS  
6
T
= 25 °C  
C
4
T
= 125 °C  
C
4
2
V
= 1 V  
GS  
T
= – 55 °C  
C
0
0
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
0.0  
0.3  
V
0.6  
0.9  
1.2  
1.5  
– Gate-to-Source Voltage (V)  
V
– Drain-to-Source Voltage (V)  
GS  
DS  
Transfer Characteristics  
Output Characteristics  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
1000  
800  
600  
400  
200  
0
C
iss  
V
= 1.8 V  
GS  
V
= 2.5 V  
GS  
C
oss  
V
= 4.5 V  
GS  
C
rss  
0
2
4
6
8
10  
12  
0
4
8
12  
16  
20  
I
– Drain Current (A)  
V
– Drain-to-Source Voltage (V)  
D
DS  
Capacitance  
On-Resistance vs. Drain Current  
8
6
4
2
0
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
V
= 2.5
V
,
1
.8 V  
GS  
V
= 6 V  
I
= 9 A  
DS  
D
I
= 5.1 A  
D
V
= 3 V  
DS  
V
= 4.5 V  
GS  
V
= 9.6 V  
DS  
0
3
6
9
12  
15  
–
5
0 –
 
25  
0
25  
50  
75  
100 125 150  
T
– Junction
T
e
mperature (°C)  
J
Q
–
T
o
tal Gate Charge (nC)  
g
On-Resistance vs. Junction Temperature  
Gate Charge  
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  
3

New Product  
Si1422DH  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
100  
I
= 5.1 A  
D
T
= 125 °C  
J
10  
T
= 25 °C  
T
= 150 °C  
T
= 25 °C  
J
J
J
1
0.1  
0
1
2
3
4
5
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
– Gate-to-Source Voltage (V)  
GS  
V
– Source-to-Drain Voltage (V)  
SD  
On-Resistance vs. Gate-to-Source Voltage  
Soure-Drain Diode Forward Voltage  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
30  
25  
20  
15  
10  
5
I
= 250 μA  
D
0
– 50
 
– 25  
0
25  
50  
75  
100 125 150  
0.001  
0.01  
0.1  
1
10  
100  
1000  
T
– Temperature(°C)  
Time (s)  
J
Single Pulse Power, Junction-to-Ambient  
Threshold Voltage  
100  
Limited by R  
*
DS(on)  
100 μs  
10  
1
1 ms  
10 ms  
100 ms  
1 s, 10 s  
DC  
T
= 25 °C  
A
0.1  
Single Pulse  
BVDSS Limited  
0.01  
0.1  
1
10  
100  
V
– Drain-to-Source Voltage (V)  
DS  
* V  
> minimum V
 
at which R  
is specified  
DS(on)  
GS  
GS  
Safe Operating Area, Junction-to-Ambient  
4
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  

New Product  
Si1422DH  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
10  
8
6
Package Limited  
4
2
0
25  
50  
75  
100  
125  
150  
0
25  
50  
75  
100  
125  
150  
T
– Case
T
e
mperature (°C)  
T
– Foot
T
e
mperature (°C)  
C
F
Current Derating*  
Power Derating  
* The power dissipation P

D

is based on T

J(max)

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper  
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package  
limit.  
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  
5

New Product  
Si1422DH  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
Notes:  
P
DM  
0.05  
t
1
0.02  
t
2
t
1
1. Duty Cycle, D =  
t
2
2. Per Unit Base = R  
= 125 °C/W  
thJA  
(t)  
3. T
 
– T
 
= P  
Z
JM  
A
DM thJA  
Single Pulse  
0.01  
4. Surface Mounted  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
100  
1000  
10  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.05  
0.02  
0.1  
Single Pulse  
0.01  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
1
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Foot  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see

.  
6
Document Number: 66701  
S10-1287-Rev. A, 31-May-10  

Package Information  
Vishay Siliconix  
SCĆ70: 6ĆLEADS  
MILLIMETERS  
INCHES  
Dim Min  
Nom Max Min Nom
 
Max  
6
1
5
2
4
3
0.90  
–
–
1.10  
0.10  
1.00  
0.30  
0.25  
2.20  
2.40  
1.35  
0.035  
–
–
–
0.043  
0.004  
0.039  
0.012  
0.010  
0.087  
0.094  
0.053  
A
E
E
1
–
A

1  

0.80  
–
0.031  
0.006  
0.004  
0.071  
0.071  
0.045  
–
A

2  

0.15  
–
–
b
-B-  
0.10  
–
–
c
e
b
1.80  
2.00  
2.10  
1.25  
0.65BSC  
1.30  
0.20  
7
_
Nom  
0.079  
0.083  
0.049  
0.026BSC  
0.051  
0.008  
7
_
Nom  
D
e
1
1.80  
E
-A-  
D
1.15  
E

1  

c
e
1.20  
1.40  
0.30  
0.047  
0.004  
0.055  
0.012  
A
e

1  

A
2
1
0.10  
L
L
A
ECN: S-03946—Rev. B, 09-Jul-01  
DWG: 5550  
Document Number: 71154  
06-Jul-01  
1

AN815  
Vishay Siliconix  
Single-Channel LITTLE FOOT
R
SC-70 6-Pin MOSFET  
Copper Leadframe Version  
Recommended Pad Pattern and Thermal Performance  
INTRODUCTION  
EVALUATION BOARDS ꢀ SINGLE SC70-6  
The new single 6-pin SC-70 package with a copper leadframe  
enables improved on-resistance values and enhanced  
thermal performance
 
as compared to the existing 3-pin and  
6-pin packages with Alloy 42 leadframes. These devices are  
intended for small
 
to medium load applications where a  
miniaturized package is required. Devices in this package  
come in a range
 
of on-resistance values, in n-channel and  
p-channel versions. This technical note discusses pin-outs,  
package outlines, pad patterns, evaluation board layout, and  
thermal performance for the single-channel version.  
The evaluation board (EVB) measures 0.6 inches by  
0.5 inches. The copper pad traces are the same as in Figure 2.  
The board allows examination from the outer pins to 6-pin DIP  
connections, permitting test sockets to be used in evaluation  
testing. See
 
Figure 3.  
52 (mil)  
BASIC PAD PATTERNS  
6
5
2
4
3
See Application Note 826,
Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Siliconix  
MOSFE
T
s, (

) for the basic  
pad layout and dimensions. These pad patterns are sufficient  
for the low to medium power applications for which this  
package is intended. Increasing the drain pad pattern yields a  
reduction in
 
thermal resistance and is a preferred footprint.  
The availability of four drain leads rather than the traditional  
single drain lead allows a better thermal path from the package  
to the PCB and external environment.  
96 (mil)  
71 (mil)  
26 (mil)  
1
13 (mil)  
0, 0 (mil)  
18 (mil)  
26 (mil)  
PIN-OUT  
16 (mil)  
Figure  
1 shows the pin-out description and Pin 1  
FIGURE 2.  
SC-70 (6 leads) Single  
identification.The pin-out of this device allows the use of four  
pins as drain leads, which helps to reduce on-resistance and  
junction-to-ambient thermal resistance.  
SOT-363  
SC-70 (6-LEADS)  
The thermal performance of the single 6-pin SC-70 has been  
measured on the EVB, comparing both the copper and  
Alloy 42
 
leadframes. This test was first conducted on the  
traditional Alloy 42 leadframe and was then repeated using the  
1-inch

2

PCB with dual-side copper coating.  
D
D
G
1
2
3
6
5
D
D
S
4
T
o
p View  
FIGURE 1.  
For package dimensions see outline drawing SC-70 (6-Leads)  
Document Number:
 
71334  
12-Dec-03  
1

AN815  
Vishay Siliconix  
Front of Board SC70-6  
Back of Board SC70-6  
vishay.com  
FIGURE 3.  
THERMAL PERFORMANCE  
Junction-to-Foot Thermal Resistance  
(Package Performance)  
COOPER LEADFRAME  
Room Ambient 25
_
C  
Elevated Ambient 60
_
C  
The junction to foot thermal resistance is a useful method of  
comparing different packages thermal performance.  
T

J(max)

*
T

A  

T

J(max)

*
T

A  

P

D  

+
P

D  

+
R
q

JA  

R
q

JA  

150

o

C
*
60

o

C  
124

o

C
ń
W  
150

o

C
*
25

o

C  
124

o

C
ń
W  
P

D  

+
P

D  

+
A helpful way of presenting the thermal performance of the  
6-Pin SC-70 copper leadframe device is to compare it to the  
traditional Alloy 42 version.  
P

D

+
726 mW  
P

D

+
1.01 W  
As can be seen from the calculations above, the compact 6-pin  
SC-70 copper leadframe LITTLE FOOT power MOSFET can  
handle up to 1 W under the stated conditions.  
Thermal performance for the 6-pin SC-70 measured as  
junction-to-foot thermal resistance, where the “foot” is the  
drain lead of the device at the bottom where it meets the PCB.  
The junction-to-foot thermal resistance is typically 40
_
C/W in  
the copper leadframe and 163
_
C/W in the Alloy 42 leadframe  
— a four-fold improvement. This improved performance is  
obtained by the enhanced thermal conductivity of copper over  
Alloy 42.  
Testing  
To
f
urther aid comparison of copper and Alloy 42 leadframes,  
Figure 5 illustrates single-channel 6-pin SC-70 thermal  
performance on two different board sizes and two different pad  
patterns. The measured steady-state values of R
q

JA

for the  
two leadframes are as follows:  
LITTLE FOOT 6-PIN SC-70  
Power Dissipation  
Alloy 42  
Copper  
The typical R
q

JA

for the single 6-pin SC-70 with copper  
leadframe is 103
_
C/W steady-state, compared with 212
_
C/W  
for the Alloy 42 version. The figures are based on the 1-inch

2  

FR4 test board. The following example shows how the thermal  
resistance impacts power dissipation for the two different  
leadframes at varying ambient temperatures.  
1) Minimum recommended pad pattern on  
the EVB board V (see Figure 3.  
329.7
_
C/W  
208.5
_
C/W  
2
2) Industry standard 1-inch
 
PCB with  
211.8
_
C/W  
103.5
_
C/W  
maximum copper both sides.  
The results indicate that designers can reduce thermal  
resistance (R
q

JA

) by 36% simply by using the copper  
leadframe device rather than the Alloy 42 version. In this  
example, a 121
_
C/W reduction was achieved without an  
increase in board area. If increasing in board size is feasible,  
a further 105
_
C/W reduction could be obtained by utilizing a  
1-inch

2

square PCB area.  
ALLOY 42 LEADFRAME  
Room Ambient 25
_
C  
Elevated Ambient 60
_
C  
T

J(max)

*
T

A  

R
q

JA  

T

J(max)

*
T

A  

R
q

JA  

P

D  

+
P

D  

+
The copper leadframe versions have the following suffix:  
150

o

C
*
25

o

C  
212

o

C
ń
W  
150

o

C
*
25

o

C  
212

o

C
ń
W  
P

D  

+
P

D  

+
Single:  
Dual:  
Si14xxEDH  
Si19xxEDH  
P

D

+
590 mW  
P

D

+
425 mW  
Complementary: Si15xxEDH  
Document Number:
 
71334  
12-Dec-03  
2

AN815  
Vishay Siliconix  
250  
200  
150  
400  
320  
240  
Alloy  
42  
Alloy  
42  
160  
80  
100  
50  
Copper  
100  
Copper  
0
0
-5  
-4  
-3  
-2  
-1  
-5  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
10  
1
10  
1000  
10  
10  
10  
10  
10  
1
10  
100  
1000  
Time (Secs)  
Time (Secs)  
2
FIGURE 4.  
Leadframe Comparison on EVB  
FIGURE 5.  
Leadframe Comparison on Alloy 42 1-inch
 
PCB  
Document Number:
 
71334  
12-Dec-03  
3

Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM
P
A
DS FOR SC-70: 6-Lead  
0.067  
(1.702)  
0.016  
0.026  
0.010  
(0.406)  
(0.648)  
(0.241)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
18  
Document Number: 72602  
Revision: 21-Jan-08  

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Revision: 08-Feb-17  
Document Number: 91000  
1