Vishay-Intertech-SI1553CDL-T1-GE3
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Si1553CDL
Vishay Siliconix
N- and P-Channel 20 V (D-S) MOSFET
FEATURES
• TrenchFET
®
power MOSFET
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
(
Ω
)
I
D
(A)
a
Q
g
(TYP.)
• 100 % R
g
tested
0.390 at V
GS
= 4.5 V
0.510 at V
GS
= 2.7 V
0.578 at V
GS
= 2.5 V
0.850 at V
GS
= -4.5 V
1.350 at V
GS
= -2.7 V
1.480 at V
GS
= -2.5 V
0.7
• Material categorization:
for definitions of compliance please see
N-Channel
P-Channel
20
0.5
0.5
0.55
0.95
-0.5
-0.5
-0.3
-20
APPLICATIONS
• Load switch
S
OT-
3
6
3
• DC/DC converter
S
C-70 Dual (6 lea
d
s)
S
2
D
1
S
2
4
G
2
5
D
1
6
G
2
G
1
3
D
2
2
G
1
1
S
1
D
2
S
1
Top View
N-Channel MOSFET
P-Channel MOSFET
Marking Code
: RH
Ordering Information
:
Si1553CDL-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
20
-20
V
V
GS
12
T
C
= 25 °C
C
= 70 °C
0.7
0.6
0.7
b, c
0.5
b, c
0.3
-0.5
-0.4
-0.4
b, c
-0.4
b, c
-0.3
T
Continuous Drain Current (T
J
= 150 °C)
I
D
T
A
= 25 °C
T
A
= 70 °C
A
T
C
= 25 °C
Source-Drain Current Diode Current
Pulsed Drain Current (t = 300 μs)
I
S
T
A
= 25 °C
0.2
b, c
-0.2
b, c
I
DM
2
-1
T
C
= 25 °C
C
= 70 °C
0.34
0.34
T
0.22
0.22
Maximum Power Dissipation
P
D
W
T
A
= 25 °C
T
A
= 70 °C
0.29
b, c
0.18
b, c
0.29
b, c
0.18
b, c
Operating Junction and Storage Temperature Range
T
J
, T
stg
-55 to 150
°C
THERMAL RESISTANCE RATINGS
N-CHANNEL
TYP. MAX.
365 438
308 370
P-CHANNEL
PARAMETER
SYMBOL
UNIT
TYP.
365
308
MAX.
438
370
Maximum Junction-to-Ambient
b, d
Maximum Junction-to-Foot (Drain)
t
≤
10 s
R
thJA
R
thJF
°C/W
Steady State
Notes
a. Based
on T
C
= 25 °C.
b. Surface
mounted on 1″ x 1″ FR4 board.
c. t
= 10 s.
d. Maximum
under steady state conditions is 486 °C/W (N-Channel) and 486 °C/W (P-Channel).
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
a
MAX.
UNIT
Static
V
GS
= 0 V, I
D
= 250 μA
V
GS
= 0 V, I
D
= -250 μA
I
D
= 250 μA
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
20
–
–
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
Δ
V
DS
/T
J
Δ
V
GS(th)
/T
J
V
GS(th)
V
-20
–
–
–
–
24
I
D
= -250 μA
–
-13
–
mV/°C
I
D
= 250 μA
–
-1.8
–
I
D
= -250 μA
–
2.3
–
V
DS
= V
GS
, I
D
= 250 μA
V
DS
= V
GS
, I
D
= -250 μA
0.6
–
1.5
-1.5
100
100
1
V
-0.6
–
–
–
–
I
GSS
V
DS
= 0 V, V
GS
=
12 V
nA
–
V
DS
= 20 V, V
GS
= 0 V
–
–
–
V
DS
= -20 V, V
GS
= 0 V
–
-1
Zero Gate Voltage Drain Current
On-State Drain Current
b
I
DSS
μA
A
V
DS
= 20 V, V
GS
= 0 V, T
J
= 55 °C
–
–
10
V
DS
= -20 V, V
GS
= 0 V, T
J
= 55 °C
DS
= 5 V, V
GS
= 5 V
–
–
-10
–
V
2
-1
–
–
I
D(on)
V
DS
= -5 V, V
GS
= -5 V
V
GS
= 4.5 V, I
D
= 0.7 A
–
–
0.325
0.708
0.425
1.130
0.462
1.230
1.5
0.8
0.390
0.850
0.510
1.350
0.578
1.480
–
V
GS
= -4.5 V, I
D
= -0.4 A
–
V
GS
= 2.7 V, I
D
= 0.4 A
–
Drain-Source On-State Resistance
b
R
DS(on)
Ω
V
GS
= -2.7 V, I
D
= -0.2 A
–
V
GS
= 2.5 V, I
D
= 0.4 A
–
V
GS
= -2.5V, I
D
= -0.2 A
–
V
DS
= 15 V, I
D
= 0.7 A
V
DS
= -15 V, I
D
= -0.5 A
–
Forward Transconductance
b
Dynamic
a
g
fs
S
–
–
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
–
–
38
43
–
Input Capacitance
C
iss
C
oss
C
rss
–
N-Channel
DS
= 10 V, V
GS
= 0 V, f = 1 MHz
V
–
14
–
Output Capacitance
pF
–
16
–
–
P-Channel
DS
= -10 V, V
GS
= 0 V, f = 1 MHz
V
–
6
Reverse Transfer Capacitance
–
10
–
V
DS
= 10 V, V
GS
= 10 V, I
D
= 0.7 A
DS
= -10 V, V
GS
= -10 V, I
D
= -0.5 A
–
1.2
1.9
0.55
0.95
0.15
0.25
0.15
0.25
7.2
10.3
1.8
3
V
–
Total Gate Charge
Q
g
–
1.1
1.5
–
–
N-Channel
V
DS
= 10 V, V
GS
= 4.5 V I
D
= 0.5 A
nC
–
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Q
gs
Q
gd
R
g
–
–
P-Channel
DS
= -10 V, V
GS
= -4.5 V, I
D
= -0.4 A
V
–
–
–
–
1.5
2.1
14.4
20.6
f = 1 MHz
Ω
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Dynamic
a
SYMBOL
TEST CONDITIONS
MIN.
TYP.
a
MAX.
UNIT
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
4
Turn-On Delay Time
Rise Time
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
2
4
N-Channel
DD
= 10 V, R
L
= 20
Ω
I
D
≅
0.5 A, V
GEN
= 10 V, R
g
= 1
Ω
14
9
21
18
20
20
14
14
24
23
33
23
33
20
20
16
V
11
10
7
P-Channel
DD
= -10 V, R
L
= 25
Ω
I
D
≅
-0.4 A, V
GEN
= -10 V, R
g
= 1
Ω
Turn-Off Delay Time
Fall Time
V
7
ns
16
15
22
15
22
12
13
8
Turn-On Delay Time
Rise Time
N-Channel
DD
= 10 V, R
L
= 20
Ω
I
D
≅
0.5 A, V
GEN
= 4.5 V, R
g
= 1
Ω
V
P-Channel
DD
= -10 V, R
L
= 25
Ω
I
D
≅
-0.4 A, V
GEN
= -4.5 V, R
g
= 1
Ω
Turn-Off Delay Time
Fall Time
V
Drain-Source Body Diode Characteristics
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3
-0.3
2
Continuous Source-Drain Diode
Current
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
A
–
Pulse Diode Forward Current
a
Body Diode Voltage
–
-1
1.2
-1.2
15
20
2
I
S
= 0.5 A
I
S
= -0.4 A
0.8
-0.8
8
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
12
1
N-Channel
I
F
= 0.5 A, dI/dt = 100 A/μs, T
J
= 25 °C
Q
rr
t
a
5
10
–
4
P-Channel
I
F
= -0.4 A, dI/dt = -100 A/μs, T
J
= 25 °C
9
–
ns
4
–
t
b
3
–
Notes
a. Guaranteed
by design, not subject to production testing.
b. Pulse
test; pulse width
≤
300 μs, duty cycle
≤
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
2
1.5
1
V
GS
= 5 V thru 3 V
V
GS
= 2.5 V
T
C
= 25
°
C
V
GS
= 2 V
0.5
0
T
C
= 125
°
C
V
GS
= 1.5 V
T
C
= – 55
°
C
0
0.5
1
1.5
2
0
0.5
1
1.5
2
V
D
S
– Drain-to-
S
ource Voltage (V)
V
GS
–
G
ate-to-
S
ource Voltage (V)
Output Characteristics
Transfer Characteristics
50
40
30
20
10
0
0.7
0.6
0.5
0.4
0.3
0.2
C
i
ss
V
GS
= 2.5 V
V
GS
=2.7 V
C
o
ss
V
GS
= 4.5 V
C
r
ss
0
5
10
15
20
0
0.5
1
1.5
2
V
D
S
– Drain-to-
S
ource Voltage (V)
I
D
– Drain Current (A)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
10
1.7
1.5
1.3
1.1
0.9
0.7
I
D
= 0.7 A
I
D
= 0.7 A
V
D
S
= 10 V
8
6
4
2
0
V
GS
= 4.5 V
V
D
S
= 5 V
V
D
S
= 16 V
V
GS
= 2.7 V
– 50
– 25
0
25
50
75
100 125 150
0
0.3
0.6
0.9
1.2
T
J
– Junction Temperature (
°
C)
Q
g
– Total
G
ate Charge (nC)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 67693
S14-1130-Rev. B, 02-Jun-14
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
0.8
0.7
0.6
0.5
0.4
0.3
0.2
I
D
= 0.7 A
T
J
= 150
°
C
T
J
= 125
°
C
T
J
= 25
°
C
1
T
J
= 25
°
C
0.1
0.0
0.3
0.6
0.9
1.2
1.5
2
4
5
V
GS
–
G
ate-to-
S
ource Voltage (V)
V
S
D
–
S
ource-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
1.1
1
6.4
4.8
3.2
1.6
0
0.9
0.8
0.7
0.6
I
D
= 250 μA
– 50
– 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
T
J
– Temperature (
°
C)
Time (
s
)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
10
*
Limited by R
D
S
(on)
1
100 μ
s
1 m
s
10 m
s
0.1
100 m
s
T
C
= 25
°
C
S
ingle Pul
s
e
1
s
10
s
, DC
BVD
SS
Limited
0.01
0.1
1
10
100
V
D
S
– Drain-to-
S
ource Voltage (V)
* V
GS
> minimum V
GS
at which R
D
S
(on)
i
s s
pecified
Safe Operating Area, Junction-to-Ambient
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
T
C
– Ca
s
e Temperature (
°
C)
Current Derating*
0.45
0.36
0.27
0.18
0.09
0
0.32
0.24
0.16
0.08
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Ca
s
e Temperature (
°
C)
T
A
– Ambient Temperature (
°
C)
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
* The power dissipation P
D
is based on T
J (max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
0.2
0.1
Note
s
:
P
DM
0.1
0.05
t
1
t
2
0.02
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Ba
s
e = R
= 486 °C/W
thJA
(t)
3. T
– T
= P
Z
DM thJA
S
ingle Pul
s
e
JM
A
4.
S
urface Mounted
0.01
0.0001
0.001
0.01
0.1
1
10
100
Sq
uare Wave Pul
s
e Duration (
s
)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
S
ingle Pul
s
e
0.01
0.0001
0.001
0.01
0.1
1
10
Sq
uare Wave Pul
s
e Duration (
s
)
Normalized Thermal Transient Impedance, Junction-to-Foot
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
7
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
0.2
0.15
0.1
V
GS
= 5 V thru 3 V
V
GS
= 2.5 V
T
C
= 25
°
C
V
GS
= 2 V
0.05
0
T
C
= 125
°
C
V
GS
= 1.5 V
T
C
= – 55
°
C
0
0.5
1
1.5
2
0
0.5
1
1.5
2
V
GS
–
G
ate-to-
S
ource Voltage (V)
V
D
S
– Drain-to-
S
ource Voltage (V)
Output Characteristics
Transfer Characteristics
1.8
1.5
1.2
0.9
0.6
0.3
80
60
40
20
0
V
GS
= 2.5 V
V
GS
= 2.7 V
C
i
ss
V
GS
= 4.5 V
C
o
ss
C
r
ss
0
5
10
15
20
0
0.2
0.4
0.6
0.8
1
V
D
S
– Drain-to-
S
ource Voltage (V)
I
D
– Drain Current (A)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.6
1.4
1.2
1.0
0.8
0.6
10
I
D
= 0.5 A
8
6
4
2
0
V
D
S
= 10 V
V
GS
= 4.5 V
V
D
S
= 5 V
V
D
S
= 16 V
V
GS
= 2.7 V
– 50
– 25
0
25
50
75
100 125 150
0
0.5
1
1.5
2
Q
g
– Total
G
ate Charge (nC)
T
J
– Junction Temperature (
°
C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 67693
S14-1130-Rev. B, 02-Jun-14
8
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
2
10
I
D
= 0.4 A
1.5
1
T
J
= 150
°
C
T
J
= 125
°
C
1
T
J
= 25
°
C
0.5
0
T
J
= 25
°
C
0.1
0.0
0.3
0.6
0.9
1.2
1.5
0
2
4
6
8
V
S
D
–
S
ource-to-Drain Voltage (V)
V
GS
–
G
ate-to-
S
ource Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
1.2
1.05
0.9
6.4
4.8
3.2
1.6
0
I
D
= 250 μA
0.75
0.6
– 50
– 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
Time (
s
)
T
J
– Temperature (
°
C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
10
Limited by R
D
S
(on)
*
1
1 m
s
10 m
s
0.1
0.01
100 m
s
1
s
10
s
, DC
T
C
= 25
°
C
S
ingle Pul
s
e
BVD
SS
Limited
0.001
0.1
1
10
100
V
D
S
– Drain-to-
S
ource Voltage (V)
* V
GS
> minimum V
GS
at which R
D
S
(on)
i
s s
pecified
Safe Operating Area, Junction-to-Ambient
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
9
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.6
0.45
0.3
0.15
0
0
25
50
75
100
125
150
T
C
– Ca
s
e Temperature (
°
C)
Current Derating*
0.45
0.36
0.27
0.18
0.09
0
0.32
0.24
0.16
0.08
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Ca
s
e Temperature (
°
C)
T
A
– Ambient Temperature (
°
C)
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
* The power dissipation P
D
is based on T
J (max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
10
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si1553CDL
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
0.2
0.1
Note
s
:
P
DM
0.1
0.05
t
1
t
2
0.02
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Ba
s
e = R
= 486 °C/W
thJA
(t)
3. T
– T
= P
Z
S
ingle Pul
s
e
JM
A
DM thJA
4.
S
urface Mounted
0.01
0.0001
0.001
0.01
0.1
1
10
100
Sq
uare Wave Pul
s
e Duration (
s
)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
S
ingle Pul
s
e
0.01
0.0001
0.001
0.01
0.1
1
10
Sq
uare Wave Pul
s
e Duration (
s
)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
S14-1130-Rev. B, 02-Jun-14
Document Number: 67693
11
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
SCĆ70: 6ĆLEADS
MILLIMETERS
INCHES
Dim Min
Nom Max Min Nom
Max
6
1
5
2
4
3
0.90
–
–
1.10
0.10
1.00
0.30
0.25
2.20
2.40
1.35
0.035
–
–
–
0.043
0.004
0.039
0.012
0.010
0.087
0.094
0.053
A
E
E
1
–
A
1
0.80
–
0.031
0.006
0.004
0.071
0.071
0.045
–
A
2
0.15
–
–
b
-B-
0.10
–
–
c
e
b
1.80
2.00
2.10
1.25
0.65BSC
1.30
0.20
7
_
Nom
0.079
0.083
0.049
0.026BSC
0.051
0.008
7
_
Nom
D
e
1
1.80
E
-A-
D
1.15
E
1
c
e
1.20
1.40
0.30
0.047
0.004
0.055
0.012
A
e
1
A
2
1
0.10
L
L
A
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
Document Number: 71154
06-Jul-01
1
AN814
Vishay Siliconix
Dual-Channel LITTLE FOOT
R
SC-70 6-Pin MOSFET
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
This technical note discusses the pin-outs, package outlines,
applications for which this package is intended. For the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 20% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB).
pad patterns, evaluation board layout, and thermal
performance for dual-channel LITTLE FOOT power
MOSFE
T
s
i
n the SC-70 package. These new Vishay Siliconix
devices are intended for small-signal applications where a
miniaturized package is needed and low levels of current
(around 250 mA) need to be switched, either directly or by
using a level shift configuration. Vishay provides these devices
with a range of on-resistance specifications in 6-pin versions.
The new 6-pin SC-70 package enables improved
on-resistance values and enhanced thermal performance.
EVALUATION BOARDS FOR THE DUAL
SC70-6
The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches
by 0.5 inches. The copper pad traces are the same as
described in the previous section,
Basic Pad Patterns
. The
board allows interrogation from the outer pins to 6-pin DIP
connections permitting test sockets to be used in evaluation
testing.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
The thermal performance of the dual SC-70 has been
measured on the EVB with the results shown below. The
minimum recommended footprint on the evaluation board was
compared with the industry standard 1-inch square FR4 PCB
with copper on both sides of the board.
SOT-363
SC-70 (6-LEADS)
S
1
G
1
D
2
1
2
3
6
5
D
1
THERMAL PERFORMANCE
G
2
Junction-to-Foot Thermal Resistance
(the Package Performance)
4
S
2
Thermal performance for the dual SC-70 6-pin package
measured as junction-to-foot thermal resistance is 300
_
C/W
typical, 350
_
C/W maximum. The “foot” is the drain lead of the
device as it connects with the body. Note that these numbers
are somewhat higher than other LITTLE FOOT devices due to
the limited thermal performance of the Alloy 42 lead-frame
compared with a standard copper lead-frame.
T
o
p View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
The typical R
θ
JA
for the dual 6-pin SC-70 is 400
_
C/W steady
state. Maximum ratings are 460
_
C/W for the dual. All figures
based on the 1-inch square FR4 test board. The following
example shows how the thermal resistance impacts power
dissipation for the dual 6-pin SC-70 package at two different
ambient temperatures.
BASIC PAD PATTERNS
See Application Note 826,
Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay
Siliconix
SC-70. This basic pad pattern is sufficient for the low-power
Document Number:
71237
12-Dec-03
1
AN814
Vishay Siliconix
500
400
300
SC-70 (6-PIN)
Dual EVB
Room Ambient 25
_
C
Elevated Ambient 60
_
C
T
J(max)
*
T
A
T
J(max)
*
T
A
P
D
+
P
D
+
R
q
JA
R
q
JA
150
o
C
*
60
o
C
400
o
C
ń
W
150
o
C
*
25
o
C
400
o
C
ń
W
P
D
+
P
D
+
200
100
P
D
+
312 mW
P
D
+
225 mW
NOTE: Although
they are intended for low-power applications,
devices in the 6-pin SC-70 will handle power dissipation in
excess of 0.2 W.
1” Square FR4 PCB
0
-5
-4
-3
-2
-1
10
10
10
10
10
Time (Secs)
1
10
100
1000
Testing
FIGURE 2.
Comparison of Dual SC70-6 on EVB and 1”
Square FR4 PCB.
To aid comparison further, Figure 2 illustrates the dual-channel
SC-70 thermal performance on two different board sizes and
two different pad patterns. The results display the thermal
performance out to steady state. The measured steady state
values of R
θ
JA
for the dual 6-pin SC-70 are as follows:
The results show that if the board area can be increased and
maximum copper traces are added, the thermal resistance
reduction is limited to 20%.
This fact confirms that the power
dissipation is restricted with the package size and the Alloy 42
leadframe.
LITTLE FOOT SC-70 (6-PIN)
1) Minimum recommended pad pattern (see
Figure 2) on the EVB of 0.5 inches x
0.6 inches.
ASSOCIATED DOCUMENT
518
_
C/W
413
_
C/W
Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper
Leadframe Version, REcommended Pad Pattern and Thermal
2) Industry standard 1” square PCB with
maximum copper both sides.
Document Number:
71237
12-Dec-03
2
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2019 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2019
Document Number: 91000
1
