Vishay-Intertech-SI2316BDS-T1-GE3

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Vishay-Intertech-SI2316BDS-T1-GE3
Si2316BDS  
Vishay Siliconix  
N-Channel 30-V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
•
Halogen-free According to IEC 61249-2-21  
I

D

(A)

a  

4.5  
Definition  
V

DS

(V)  
R

DS(on)

(
Ω
)  
Q

g

(Typ)  
•
•
•
•
TrenchFET

®

Power MOSFET  
PWM Optimized  
0.050 at V

GS

= 10 V  
0.080 at V

GS

= 4.5 V  
3.16 nC  
30  
3.4  
100 % R
 
tested  
g
Compliant to RoHS Directive 2002/95/EC  
APPLICATIONS  
•
Battery Switch  
•
DC/DC Converter  
TO-236  
(SOT-23)  
G
S
1
2
3
D
T
o
p
V
ie
w  
Si2316DS (M6)*  
*Marking Code  
Orderin
g
Information:
Si2316BDS-T1-E3 (Lead (P
b
)-free)  
Si2316BDS-T1-GE3 (Lead (P
b
)-free and Halogen-free)  
ABSOLUTE MAXIMUM RATINGS
T =
 
25 °C, unless otherwise noted  
A
Unit  
Parameter  
Symbol  
Limit  
30  
Drain-Source Voltage  
Gate-Source Voltage  
V

DS  

V
V

GS  

20  
T
T

C

= 25 °C  

C

= 70 °C  
4.5  
3.6  
Continuous Drain Current (T

J

= 150 °C)  
I

D  

3.9

b, c  

3.13

b, c  

20  
T

A

= 25 °C  
T

A

= 70 °C  
A
Pulsed Drain Current  
I

DM  

I

S  

T

C

= 25 °C  
T

A

= 25 °C  
T

C

= 25 °C  
1.39  
1.04

b, c  

1.66  
Continuous Source-Drain Diode Current  
T

C

= 70 °C  
1.06  
W
Maximum Power Dissipation  
P

D  

1.25

b, c  

0.8

b, c  

– 55 to 150  
T

A

= 25 °C  
T

A

= 70 °C  
°C  
Operating Junction and Storage
T
e
mperature Range  
T

J

, T

stg  

THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
R

thJA  

Typical  
80  
Maximum  
Unit  
Maximum Junction-to-Ambient

b, d  

Maximum Junction-to-Foot (Drain)  
≤
5 s  
Steady State  
100  
75  
°C/W  
R

thJF  

60  
Notes:  
a. Based on T

C

= 25 °C.  
b. Surface mounted on 1″ x 1″ FR4 moard.  
c. t
 
= 5 s.  
d. Maximum
 
under Steady State conditions is 130 °C/W.  
Document Number: 70445  
S09-1503-Rev. B, 10-Aug-09  
1

Si2316BDS  
Vishay Siliconix  
MOSFET SPECIFICATIONS
T =
 
25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
Drain-Source Breakdown Voltage  
V

DS  

V

DS

= 0
V
,
I

D

= 250 µA  
30  
V
V

DS

T
e
mperature Coefficient  
Δ
V

DS

/T

J  

23.92  
5.2  
mV/°C  
I

D

= 250 µA  
V

GS(th)

T
e
mperature Coefficient  
Δ
V
/T  
GS(th) J  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
V

GS(th)  

I

GSS  

V

DS

= V

GS

, I

D

= 250 µA  
1
3
V
V

DS

= 0
V
,
V

GS  

=
20 V  
100  
1
nA  
V

DS

= 30
V
,
V

GS

= 0 V  

DS

= 30
V
,
V

GS

= 0
V
,
T

J

= 55 °C  
V

DS

≥
5
V
,
V

GS

= 10 V  
V

GS

= 10
V
,
I

D

= 3.9 A  
Zero Gate Voltage Drain Current  
On-State Drain Current

a  

I

DSS  

I

D(on)  

R

DS(on)  

g

fs  

µA  
A
V
10  
20  
0.041  
0.064  
6
0.050  
0.080  
Drain-Source On-State Resistance

a  

Ω
S
V

GS

= 4.5
V
,
I

D

= 3.3 A  
V

DS

= 15
V
,
I

D

= 3.9 A  
Forward
T
r
ansconductance

a  

Dynamic

b  

Input Capacitance  
C

iss  

C

oss  

C

rss  

350  
65  
Output Capacitance  
Reverse
T
r
ansfer Capacitance  
V

DS

= 15
V
,
V

GS

= 0
V
, f = 1
M
Hz  
pF  
37  
V

DS

= 15
V
,
V

GS

= 10
V
,
I

D

= 3.9 A  
6.35  
3.16  
1.56  
1.1  
2.6  
4.5  
11  
9.6  
4.8  
T
o
tal Gate Charge  
Q

g  

nC  
Ω
Gate-Source Charge  
Q

gs  

Q

gd  

R

g  

V

DS

= 15
V
,
V

GS

= 4.5
V
,
I

D

= 3.9 A  
f = 1 MHz  
Gate-Drain Charge  
Gate Resistance  
3.9  
6.75  
16.5  
18  
T
u
rn-On Delay Time  
t

d(on)  

t

r  

t

d(off)  

t

f  

t

d(on)  

t

r  

t

d(off)  

t

f  

Rise Time  
V

DD

= 15
V
,
R

L

= 4.8
Ω  
ns  
I

D

≅
3.13 A, V

GEN

= 10
V
,
R

G

= 1
Ω  
T
u
rn-Off Delay Time  
12  
Fall Time  
7
10.5  
30  
T
u
rn-On Delay Time  
20  
Rise Time  
65  
98  
V

DD

= 15
V
,
R

L

= 6.25
Ω  
ns  
A
I

D

=
2.4 A, V

GEN

= 4.5
V
,
R

g

= 1
Ω  
T
u
rn-Off Delay Time  
11  
17  
Fall Time  
23  
35  
Drain-Source Body Diode Characteristics  
Continuous Source-Drain Diode Current  
Pulse Diode Forward Current

a  

Body Diode Voltage  
I

S  

I

SM  

V

SD  

t

rr  

T

C

= 25 °C  
I

S

= 2.0 A  
1.39  
20  
0.8  
10  
4
1.2  
15  
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Reverse Recovery Fall Time  
Reverse Recovery Rise Time  
ns  
nC  
Q

rr  

t

a  

6
I

F

= 2.0 A, dI/dt = 100 A/µs, T

J

= 25 °C  
6.6  
3.5  
ns  
t

b  

Notes:  
a. Pulse
 
test; pulse width
≤
300 µs, duty cycle
≤
2 %.  
b. Guaranteed
 
by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
2
Document Number: 70445  
S09-1503-Rev. B, 10-Aug-09  

Si2316BDS  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
 
25 °C, unless otherwise noted  
20  
3
2
1
0
V
GS  
= 10
V
thr
u
5
V  
15  
10  
5
V
GS  
= 4
V  
T
J
= 25 °C  
T
J
= 125 °C  
V
GS  
= 3
V  
T
J
= – 55 °C  
4
0
0
1
2
3
4
5
0
1
2
3
5
V
DS  
– Drain-to-So
u
rce
V
oltage (
V
)  
V
GS  
– Gate-to-So
u
rce
V
oltage (
V
)  
Output Characteristics  
Transfer Characteristics  
0.20  
0.16  
0.12  
0.0
8  
0.04  
0.00  
500  
400  
300  
200  
100  
0
V
GS  
= 4.5
V  
C
iss  
C
oss  
V
GS  
= 10
V  
C
rss  
0
4
8
12  
16  
20  
0
6
12  
1
8  
24  
30  
I
D
– Drain C
u
rrent (A)  
V
DS  
– Drain-to-So
u
rce
V
oltage (
V
)  
On-Resistance vs. Drain Current and Gate Voltage  
Capacitance  
10  
1.
8  
1.6  
1.4  
1.2  
1.0  
0.
8  
0.6  
I
D
= 3.9 A  
V
= 10
V
, I
 
= 3.9 A  
D
GS  
8
V
DS  
= 16
V  
6
V
DS  
= 24
V  
4
V
= 4.5
V
, I
 
= 3.3 A  
GS  
D
2
0
0
2
4
6
8
– 50
 
– 25  
0
25  
50  
75  
100 125 150  
Q
g
–
T
o
tal Gate Charge (nC)  
T –
 
J
u
nction
T
e
mperat
u
re (°C)  
J
Gate Charge  
On-Resistance vs. Junction Temperature  
Document Number: 70445  
S09-1503-Rev. B, 10-Aug-09  
3

Si2316BDS  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
 
25 °C, unless otherwise noted  
0.12  
0.09  
0.06  
0.03  
0.00  
100  
I
D
= 4.1 A  
10  
T
= 125 °C  
A
T
J
= 150 °C  
1
0.1  
T
= 25 °C  
J
T
A
= 25 °C  
0.01  
0
2
4
6
8
10  
0.0  
0.2  
0.4  
0.6  
0.
8  
1.0  
1.2  
V
GS  
– Gate-to-So
u
rce
V
oltage (
V
)  
V
SD  
– So
u
rce-to-Drain
V
oltage (
V
)  
On-Resistance vs. Gate-to-Source Voltage  
Source-Drain Diode Forward Voltage  
2.6  
2.4  
2.2  
2.0  
1.
8  
1.6  
1.4  
10  
8
T
= 25 °C  
A
6
4
2
0
Single Pulse  
I
D
= 250
µ
A  
– 50
 
– 25  
0
25  
50  
75  
100 125 150  
0.01  
0.1  
1
10  
100  
600  
Time (s)  
T
J
–
T
e
mperat
u
re (
 
C)  
Threshold Voltage  
Single Pulse Power  
100  
R
DS(on)  
Limited*  
10  
10 ms  
1
100 ms  
1 s  
10 s  
0.1  
DC  
T
A
= 25 °C  
Single P
u
lse  
0.01  
0.001  
0.1  
1
10  
100  
V
DS  
– Drain-to-So
u
rce
V
oltage (
V
)  
*
V  
GS  
minim
u
m
V
at
w
hich R  
is specified  
GS  
DS(on)  
Safe Operating Area  
4
Document Number: 70445  
S09-1503-Rev. B, 10-Aug-09  

Si2316BDS  
Vishay Siliconix  
TYPICAL CHARACTERISTICS
 
25 °C, unless otherwise noted  
5
2.0  
1.6  
1.2  
0.
8  
0.4  
0.0  
4
3
2
1
0
0
25  
50  
75  
100  
125  
150  
0
25  
50  
T –
 
Case
T
e
mperat
u
re (°C)  
C
75  
100  
125  
150  
T
C
– Case
T
e
mperat
u
re (°C)  
Current Derating*  
Power Derating, Junction-to-Foot  
*The power dissipation P

D

is based on T

J(max.)

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper  
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package  
limit.  
2
1
Duty Cycle = 0.5  
0.2  
Notes:  
0.1  
P
DM  
0.1  
0.05  
0.02  
t
1
t
2
t
t
1
2
1. Duty Cycle, D =  
2. Per Unit Base = R  
= 130 °C/W  
thJA  
(t)  
3. T  
T
A
= P
 
Z  
DM thJA  
JM  
Single Pulse  
4. Surface Mounted  
0.01  
–
4  
10  
–
3  
10  
–
2  
10  
–
1  
10  
1
10  
100  
600  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see

.  
Document Number: 70445  
S09-1503-Rev. B, 10-Aug-09  
5

Package Information  
Vishay Siliconix  
SOT-23 (TO-236): 3-LEAD  
b
3
E
1
E
1
2
e
S
e
1
D
0.10 mm  
0.004″  
C
C
0.25 mm  
q
A
2
A
G
au
ge Pl
a
ne  
S
e
a
ting Pl
a
ne  
S
e
a
ting Pl
a
ne  
C
A
1
L
L
1
MILLIMETERS  
INCHES  
Dim  
Min  
0.89  
0.01  
Max  
1.12  
0.10  
Min  
0.0
3
5  
0.0004  
Max  
0.044  
0.004  
A
A

1  

A

2  

0.88  
0.
3
5  
0.085  
2.80  
2.10  
1.20  
1.02  
0.50  
0.18  
3
.04  
2.64  
1.40  
0.0
3
46  
0.014  
0.00
3  
0.110  
0.08
3  
0.047  
0.040  
0.020  
0.007  
0.120  
0.104  
0.055  
b
c
D
E
E

1  

e
0.95 BSC  
1.90 BSC  
0.0
3
74 Ref  
e

1  

0.0748 Ref  
L
0.40  
0.60  
8°  
0.016  
0.024  
8°  
L

1  

0.64 Ref  
0.50 Ref  
0.025 Ref  
0.020 Ref  
S
q
3
°  
3
°  
ECN: S-0
3
946-Rev. K, 09-Jul-01  
DWG: 5479  
Document Number: 71196  
09-Jul-01  
1

AN807  
Vishay Siliconix  
Mounting LITTLE FOOT

R

SOT-23 Power MOSFETs  
Wharton McDaniel  
Surface-mounted LITTLE FOOT power MOSFE
T
s use integrated  
circuit and small-signal packages which have been been modified  
to provide the heat transfer capabilities required by power devices.  
Leadframe materials and design, molding compounds, and die  
attach materials have been changed, while the footprint of the  
packages remains the same.  
ambient air. This pattern uses all the available area underneath the  
body for this purpose.  
0.114  
2.9  
0.081  
2.05  
See Application Note 826,
Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Siliconix  
MOSFE
T
s, (

), for the basis  
of the pad design for a LITTLE FOOT SOT-23 power MOSFET  
footprint .
 
In converting this footprint to the pad set for a power  
device, designers must make two connections: an electrical  
connection and a thermal connection, to draw heat away from the  
package.  
0.150  
3.8  
0.059  
1.5  
0.0394  
1.0  
0.037  
0.95  
FIGURE 1.
Footprint With Copper Spreading  
The electrical connections for the SOT-23 are very simple.
 
Pin 1 is  
the gate, pin 2 is the source, and pin 3 is the drain.
 
As in the other  
LITTLE FOOT packages, the drain pin serves the additional  
function of providing the thermal connection from the package to  
the PC board.
 
The total cross section of a copper trace connected  
to the drain may be adequate to carry the current required for the  
application, but it may be inadequate thermally.
 
Also, heat spreads  
in a circular fashion from the heat source.
 
In this case the drain pin  
is the heat source when looking at heat spread on the PC board.  
Since surface-mounted packages are small, and reflow soldering  
is the most common way in which these are affixed to the PC  
board, “thermal” connections from the planar copper to the pads  
have not been used.
 
Even if additional planar copper area is used,  
there should be no problems in the soldering process.
 
The actual  
solder connections are defined by the solder mask openings.
 
By  
combining the basic footprint with the copper plane on the drain  
pins, the solder mask generation occurs automatically.  
Figure 1 shows the
 
footprint with copper spreading for the SOT-23  
package. This
 
pattern shows the starting point for utilizing the  
board area available for the heat spreading copper.
 
T
o
c
reate this  
pattern, a plane of copper overlies the drain pin and provides  
planar copper to draw heat from the drain lead and start the  
process of spreading the heat so it can be dissipated into the  
A final item to keep in mind is the width of the power traces.
 
The  
absolute minimum power trace width must be determined by the  
amount of current it has to carry.
 
For thermal reasons, this  
minimum width should be at least 0.020 inches.
 
The use of wide  
traces connected to the drain plane provides a low-impedance  
path for heat to move away from the device.  
Document Number:
 
70739  
26-Nov-03  
1

Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM
P
A
DS FOR SO
T
–
23  
0.037  
0.022  
(0.950)  
(0.559)  
0.053  
(1.341)  
0.097  
(2.459)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
Document Number: 72609  
Revision: 21-Jan-08  
25  

Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product.
 
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of  
typical requirements that are often placed on Vishay products in generic applications.
 
Such statements are not binding  
statements about the suitability of products for a particular application.
 
It is the customer’s responsibility to validate that a  
particular product with the properties described in the product specification is suitable for use in a particular application.  
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over  
time. All
 
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts.
 
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.  
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for  
such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document  
or by any conduct of Vishay.
 
Product names and markings noted herein may be trademarks of their respective owners.  
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED  
Revision: 08-Feb-17  
Document Number: 91000  
1