Vishay-Intertech-Si2318CDS-T1-GE3
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New Product
Si2318CDS
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
V
DS
(V)
R
DS(on)
(
)
Q
g
(Typ.)
I
D
(A)
a
Definition
TrenchFET
®
Power MOSFET
100 % R
g
Tested
0.042 at V
GS
= 10 V
0.051 at V
GS
= 4.5 V
•
•
5.6
5.1
40
2.9 nC
•
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
•
•
DC/DC Converters
Load Switch
Portable and Consumer Applications
SO
T
–
23
D
(3)
G
S
1
Marking Code
P9 XXX
3
D
Lot Tracea
b
ility
and Date Code
G
2
(1)
Part # Code
(2)
T
o
p
V
ie
w
S
Orderin
g
Information:
Si2318CDS-T1-GE3 (Lead (P
b
)-free and Halogen-free)
N
-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Parameter
Symbol
Limit
40
Unit
Drain-Source Voltage
Gate-Source Voltage
V
DS
V
V
GS
20
5.6
a
4.5
4.3
b, c
3.5
b, c
20
T
T
T
C
= 25 °C
C
= 70 °C
A
= 25 °C
Continuous Drain Current (T
J
= 150 °C)
I
D
A
T
A
= 70 °C
Pulsed Drain Current
I
DM
I
S
T
C
= 25 °C
T
A
= 25 °C
C
= 25 °C
1.75
1.04
b, c
2.1
Continuous Source-Drain Diode Current
T
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
1.3
1.25
b, c
0.
8
b, c
Maximum Power Dissipation
P
D
W
Operating Junction and Storage
T
e
mperature Range
Soldering Recommendations (Peak
T
e
mperature)
T
J
, T
stg
– 55 to 150
260
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
R
thJA
R
thJF
Typical
8
0
Maximum
100
Unit
Maximum Junction-to-Ambient
b, d
t
5 s
Steady State
°C/W
Maximum Junction-to-Foot (Drain)
40
60
Notes:
a. Based on T
C
= 25 °C
b. Surface mounted on 1″ x 1″ FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 125 °C/W.
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
1
New Product
Si2318CDS
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
GS
= 0
V
,
I
D
= 250 µA
I
D
= 250 µA
Drain-Source Breakdown Voltage
40
V
V
DS
T
e
mperature Coefficient
39
mV/°C
V
GS(th)
T
e
mperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
– 4.7
V
DS
= V
GS
, I
D
= 250 µA
V
1.2
20
2.5
100
1
I
GSS
V
DS
= 0
V
,
V
GS
=
20 V
nA
V
DS
= 40
V
,
V
GS
= 0 V
V
DS
= 40
V
,
V
GS
= 0
V
,
T
J
= 70 °C
V
DS
5
V
,
V
GS
= 10 V
I
DSS
I
D(on)
R
DS(on)
g
fs
µA
A
Zero Gate Voltage Drain Current
On-State Drain Current
a
10
V
GS
10
V
,
I
D
= 4.3 A
0.035
0.041
17
0.042
0.051
Drain-Source On-State Resistance
a
Forward
T
r
ansconductance
a
S
V
GS
4.5
V
,
I
D
= 3.9 A
V
DS
= 20
V
,
I
D
= 4.3 A
Dynamic
b
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse
T
r
ansfer Capacitance
340
60
30
5.
8
2.9
1.1
0.9
3.3
12
50
10
8
V
DS
= 20
V
,
V
GS
= 0
V
, f = 1
M
Hz
pF
V
DS
= 20
V
,
V
GS
= 10
V
,
I
D
= 4.3 A
9
6
Q
g
T
o
tal Gate Charge
nC
Q
gs
Q
gd
R
g
Gate-Source Charge
V
DS
= 20
V
,
V
GS
= 4.5
V
,
I
D
= 4.3 A
f = 1 MHz
Gate-Drain Charge
Gate Resistance
0.6
6.6
20
75
20
16
14
30
21
16
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
T
u
rn-On Delay Time
V
DD
= 20
V
,
R
L
= 5.7
Rise Time
I
D
3.5 A, V
GEN
= 4.5
V
,
R
g
= 1
T
u
rn-Off Delay Time
Fall Time
ns
T
u
rn-On Delay Time
7
V
DD
= 20
V
,
R
L
= 5.7
Rise Time
20
14
8
I
D
3.5 A, V
GEN
= 10
V
,
R
g
= 1
T
u
rn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
1.75
20
A
I
S
= 3.5 A, V
GS
0 V
0.
8
5
15
7
1.2
23
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Q
rr
t
a
14
I
F
= 3.5 A, dI/dt = 100 A/µs, T
J
= 25 °C
11
4
ns
t
b
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
New Product
Si2318CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
20
5
4
3
2
1
0
V
= 10 V thru 4 V
GS
T
= – 55 °C
15
10
5
C
V
= 3 V
GS
T
= 25 °C
C
T
= 125 °C
C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.6
1.2
1.8
2.4
3.0
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
450
360
270
180
90
0.06
0.05
0.04
0.03
0.02
C
iss
V
= 4.5 V
= 10 V
GS
V
GS
C
oss
C
rss
0
0
5
10
15
20
0
5
10
15
20
I
D
– Drain Current (A)
On-Resistance vs. Drain Current and Gate Voltage
V
DS
– Drain-to-Source Voltage (V)
Capacitance
10
1.65
1.45
1.25
1.05
0.85
0.65
I
= 4.3 A
D
V
= 20 V
DS
8
V
= 10 V; I
= 4.3 A
D
GS
V
= 10 V
DS
6
V
= 32 V
DS
V
= 4.5 V; I
= 3.9 A
GS
D
4
2
0
0
1
2
3
4
5
6
– 50
– 25
0
25
50
75
100 125 150
Q
g
– Total Gate Charge (nC)
T
J
– Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Gate Charge
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
3
New Product
Si2318CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
100
0.10
0.08
0.06
0.04
0.02
I
= 4.3 A
D
T
= 150 °C
J
10
T
= 125 °C
J
T
= 25 °C
J
1
T
= 25 °C
J
0.1
2
4
6
8
10
0
0.3
0.6
0.9
1.2
V
SD
– Source-to-Drain Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
2.0
1.8
1.6
1.4
1.2
1.0
32
24
16
8
I
= 250 μA
D
0
– 50
– 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
100
T
J
– Temperature (°C)
Time (s)
Single Pulse Power (Junction-to-Ambient)
Threshold Voltage
100
Limited by R
*
DS(on)
10
1
100 μs
1 ms
10 ms
100 ms
0.1
T
= 25 °C
A
1 s, 10 s
DC
Single Pulse
BVDSS Limited
10
0.01
0.1
1
100
V
DS
– Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
4
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
New Product
Si2318CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
6.0
4.5
3.0
1.5
0
0
25
50
75
100
125
150
T
C
– Case Temperature (°C)
Current Derating*
2.5
2.0
1.5
1.0
0.5
0
1.2
0.9
0.6
0.3
0
0
0
25
50
T
C
– Case Temperature (°C)
Power Derating, Junction-to-Foot
75
100
125
150
25
50
75
100
125
150
T
A
– Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
5
New Product
Si2318CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
0.2
0.1
0.1
Notes:
P
DM
0.05
t
1
0.02
t
2
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Base = R
= 125 °C/W
thJA
(t)
3. T
– T
= P
Z
JM
A
DM thJA
Single Pulse
0.01
4. Surface Mounted
-4
-3
-2
-1
10
10
10
10
1
100
10 000
1000
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Duty Cycle = 0.5
0.2
0.1
0.02
Single Pulse
0.05
0.1
10
-4
-3
-2
-1
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for
Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
Document Number: 67030
S10-2250-Rev. A, 04-Oct-10
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E
1
E
1
2
e
S
e
1
D
0.10 mm
0.004″
C
C
0.25 mm
q
A
2
A
G
au
ge Pl
a
ne
S
e
a
ting Pl
a
ne
S
e
a
ting Pl
a
ne
C
A
1
L
L
1
MILLIMETERS
INCHES
Dim
Min
0.89
0.01
Max
1.12
0.10
Min
0.0
3
5
0.0004
Max
0.044
0.004
A
A
1
A
2
0.88
0.
3
5
0.085
2.80
2.10
1.20
1.02
0.50
0.18
3
.04
2.64
1.40
0.0
3
46
0.014
0.00
3
0.110
0.08
3
0.047
0.040
0.020
0.007
0.120
0.104
0.055
b
c
D
E
E
1
e
0.95 BSC
1.90 BSC
0.0
3
74 Ref
e
1
0.0748 Ref
L
0.40
0.60
8°
0.016
0.024
8°
L
1
0.64 Ref
0.50 Ref
0.025 Ref
0.020 Ref
S
q
3
°
3
°
ECN: S-0
3
946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
1
AN807
Vishay Siliconix
Mounting LITTLE FOOT
R
SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFE
T
s use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
See Application Note 826,
Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint .
In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1.
Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple.
Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain.
As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board.
The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally.
Also, heat spreads
in a circular fashion from the heat source.
In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used.
Even if additional planar copper area is used,
there should be no problems in the soldering process.
The actual
solder connections are defined by the solder mask openings.
By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
Figure 1 shows the
footprint with copper spreading for the SOT-23
package. This
pattern shows the starting point for utilizing the
board area available for the heat spreading copper.
T
o
c
reate this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
A final item to keep in mind is the width of the power traces.
The
absolute minimum power trace width must be determined by the
amount of current it has to carry.
For thermal reasons, this
minimum width should be at least 0.020 inches.
The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
Document Number:
70739
26-Nov-03
1
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications.
Such statements are not binding statements
about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application.
Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time.
All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part.
Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
1
