Vishay-Intertech-SI3421DV-T1-GE3
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Si3421DV
Vishay Siliconix
P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
•
•
TrenchFET
®
Power MOSFET
V
DS
(V)
R
DS(on)
(
) Max.
Q
g
(Typ.)
I
D
(A)
d,e
100 % R
g
and UIS Tested
Material categorization:
0.0192 at V
GS
= -10 V
0.0232 at V
GS
= -6 V
0.0270 at V
GS
= -4.5 V
-8
-8
-8
For definitions of compliance please see
-30
21 nC
A
v
aila
b
le
TSOP-6
Top View
APPLICATIONS
•
•
•
•
Load Switches
Adaptor Switch
DC/DC Converter
For Mobile Computing/Consumer
S
D
D
D
S
1
2
3
6
5
3 mm
D
G
G
Marking Code
BI XX
4
Lot Tracea
b
ility
and Date Code
2.85 mm
D
Part # Code
Ordering Information:
Si3421DV-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Parameter
Symbol
V
DS
Limit
-30
Unit
Drain-Source Voltage
Gate-Source Voltage
V
V
GS
20
-8
e
-8
e
-8.3
a, b
-6.7
a, b
-50
T
C
= 25 °C
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Continuous Drain Current (T
J
= 150 °C)
I
D
A
I
DM
I
S
Pulsed Drain Current (t = 100 µs)
T
C
= 25 °C
A
= 25 °C
-3.5
-1.7
a, b
Continuous Source-Drain Diode Current
T
I
AS
Avalanche Current
-15
L = 0.1 mH
E
AS
Single-Pulse Avalanche Energy
11.25
4.2
mJ
W
T
C
= 25 °C
T
C
= 70 °C
T
A
= 25 °C
2.7
P
D
Maximum Power Dissipation
2
a, b
1.3
a, b
T
A
= 70 °C
T
J
, T
stg
Operating Junction and Storage
T
e
mperature Range
-55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
R
thJA
R
thJF
Typical
40
Maximum
Unit
Maximum Junction-to-Ambient
a, c
t
10 s
Steady State
62.5
30
°C/W
Maximum Junction-to-Foot
25
Notes:
a. Surface
mounted on 1″ x 1″ FR4 board.
b. t
= 10 s.
c. Maximum
under steady state conditions is 110 °C/W.
d. Based
on T
C
= 25 °C.
e. Package
limited.
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
1
Si3421DV
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
GS
= 0
V
,
I
D
= -250 µA
I
D
= -250 µA
Drain-Source Breakdown Voltage
-30
V
V
DS
T
e
mperature Coefficient
-18
4.6
mV/°C
V
GS(th)
T
e
mperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
= V
GS
, I
D
= -250 µA
-1
-3
V
I
GSS
V
DS
= 0
V
,
V
GS
=
20 V
100
-1
nA
V
DS
= -30
V
,
V
GS
= 0 V
I
DSS
Zero Gate Voltage Drain Current
On-State Drain Current
a
µA
A
V
DS
= -30
V
,
V
GS
= 0
V
,
T
J
= 55 °C
-5
I
D(on)
V
DS
-10
V
,
V
GS
= -10 V
-30
V
GS
= -10
V
,
I
D
= -7 A
0.0160
0.0193
0.0225
30
0.0192
0.0232
0.0270
Drain-Source On-State Resistance
a
R
DS(on)
g
fs
V
GS
= -6
V
,
I
D
= -5 A
V
GS
= -4.5
V
,
I
D
= -3 A
Forward
T
r
ansconductance
a
Dynamic
b
V
DS
= -10
V
,
I
D
= -7 A
S
C
iss
C
oss
C
rss
Input Capacitance
2580
256
225
46
21
7
V
DS
= -15
V
,
V
GS
= 0
V
, f = 1
M
Hz
Output Capacitance
Reverse
T
r
ansfer Capacitance
pF
V
DS
= -15
V
,
V
GS
= -10
V
,
I
D
= -8.3 A
DS
= -15
V
,
V
GS
= -4.5
V
,
I
D
= -8.3 A
f = 1 MHz
69
32
Q
g
T
o
tal Gate Charge
nC
Q
gs
Q
gd
R
g
V
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
T
u
rn-On Delay Time
Rise Time
6.1
8
1.6
16
14
18
83
20
87
60
54
26
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
7
V
DD
= -15
V
,
R
L
= 2.24
9
I
D
-6.7 A, V
GEN
= -10
V
,
R
g
= 1
T
u
rn-Off DelayTime
Fall Time
55
13
58
40
36
17
ns
T
u
rn-On Delay Time
Rise Time
V
DD
= -15
V
,
R
L
= 2.24
I
D
-6.7 A, V
GEN
= -4.5
V
,
R
g
= 1
T
u
rn-Off DelayTime
Fall Time
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current
Pulse Diode Forward Current (t = 100 µs)
Body Diode Voltage
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
-3.5
-50
-1.2
33
A
I
S
= -6.7 A, V
GS
= 0 V
-0.85
21.5
12
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
ns
nC
Q
rr
t
a
20
I
F
= -6.7 A, dI/dt = 100 A/µs,
T
J
= 25 °C
10.5
11
ns
Reverse Recovery Rise Time
t
b
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
Si3421DV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
50
V
GS
= 10 V thru 5 V
V
GS
= 4.5 V
8
40
V
GS
= 4 V
6
4
2
0
30
20
10
0
T
C
= 25
°
C
T
C
= 125
°
C
V
GS
= 3 V
T
C
= – 55
2.8 3.5
0
0.5
1
1.5
2
0
0.7
1.4
2.1
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.038
0.032
0.026
0.02
3375
2700
2025
1350
675
C
iss
V
GS
= 4.5 V
V
GS
= 6 V
V
GS
= 10 V
0.014
0.008
C
oss
C
rss
0
0
10
20
30
40
50
0
6
12
18
24
30
V
DS
– Drain-to-Source Voltage (V)
I
D
– Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
1.5
1.3
1.1
0.9
0.7
10
8
V
DS
= 8 V
I
D
= 8.3 A
V
GS
, I
D
= 10 V/7 A; 6 V/5 A;
4.5 V/3 A
6
V
DS
= 15 V
V
DS
= 24 V
4
2
0
0
10
20
30
40
50
– 50
– 25
0
25
50
75
100 125 150
Q
g
– Total Gate Charge (nC)
T
J
– Junction Temperature (
°
C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
3
Si3421DV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.060
0.050
0.040
0.030
0.020
0.010
0.000
100
10
1
I
D
= 7 A
T
J
= 150
°
C
T
J
= 125
°
C
T
J
= 25
°
C
T
J
= 25
°
C
0.1
0.0
0.3
0.6
0.9
1.2
0
2
4
6
8
10
V
SD
– Source-to-Drain Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
50
40
30
20
2.25
2
I
D
= 250 μA
1.75
1.5
10
0
1.25
– 50
– 25
0
25
50
75
100 125 150
–
3
–
2
10
–
1
10
10
1
10
100
600
Time (s)
T
J
– Temperature (
°
C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
10
Limited by I
DM
Limited by R
DS(on)
*
100 μs
1 ms
1
10 ms
100 ms
0.1
0.01
10 s,
1 s
DC
T
A
= 25
°
C
BVDSS Limited
10
0.1
1
100
V
DS
– Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
Safe Operating Area
4
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
Si3421DV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
14
10.5
7
3.5
0
0
25
50
75
100
125
150
T
C
– Case Temperature (
°
C)
Current Derating*
5
4
3
2
1
0
1.4
1.1
0.7
0.4
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Case Temperature (
°
C)
T
A
– Ambient Temperature (
°
C)
Power, Junction-to-Foot
Power Derating, Junction-to-Ambient
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
5
Si3421DV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
2
1
D
u
ty Cycle = 0.5
0.2
N
otes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
1. D
u
ty Cycle, D =
0.02
2. Per Unit Base = R
= 90 °C/
W
thJA
(t)
3. T
JM
–
T =
P
Z
A
DM thJA
4. S
u
rface Mo
u
nted
Single P
u
lse
0.01
–
4
10
–
3
10
–
2
10
–
1
10
1
10
100
600
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
D
u
ty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single P
u
lse
0.01
–
4
–
3
–
2
–
1
10
10
10
10
1
10
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Document Number: 62921
S13-2289-Rev. A, 04-Nov-13
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
5
4
3
6
1
4
E
1
E
E
1
E
1
2
2
3
-B-
-B-
e
e
b
b
M
M
C
0.15
C
B
A
0.15
B A
5-LEAD TSOP
6-LEAD TSOP
4x
1
-A-
D
0.17 Ref
c
R
R
A
2
A
L
2
G
au
ge Pl
a
ne
S
e
a
ting Pl
a
ne
S
e
a
ting Pl
a
ne
L
0.0
8
C
A
1
-C-
(L )
1
4x
1
MILLIMETERS
INCHES
Dim
A
A
1
A
2
b
c
D
E
E
1
e
Min
Nom
–
Max
Min
0.036
0.0004
0.035
0.012
0.004
0.116
0.106
0.061
Nom
–
Max
0.91
0.01
0.90
0.30
0.10
2.95
2.70
1.55
1.10
0.10
1.00
0.45
0.20
3.10
2.9
8
1.70
0.043
0.004
0.039
0.01
8
0.00
8
0.122
0.117
0.067
–
–
–
0.32
0.15
3.05
2.
8
5
1.65
0.95 B
S
C
1.90
–
0.03
8
0.013
0.006
0.120
0.112
0.065
0.0374 B
S
C
0.075
–
1.
8
0
2.00
0.50
0.071
0.012
0.079
0.020
e
1
L
0.32
0.60 Ref
0.25 B
S
C
–
0.024 Ref
0.010 B
S
C
–
L
1
L
2
R
0.10
0
–
0.004
0
–
4
8
4
8
7
Nom
7 Nom
1
ECN: C-06593-Rev.
I, 1
8
-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
1
AN823
Vishay Siliconix
Mounting LITTLE FOOT
R
TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages.
Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFE
T
s
.
Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What
has remained the same is the footprint of the
packages.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used.
Even if additional planar copper area is
used, there should be no problems in the soldering process.
The
actual solder connections are defined by the solder mask
openings. By
combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package.
For the TSOP-6 package
In converting the footprint to the pad set for a power MOSFE
T
, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
A final item to keep in mind is the width of the power traces.
The
absolute minimum power trace width must be determined by the
amount of current it has to carry.
For thermal reasons, this
minimum width should be at least 0.020 inches.
The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
In the case of the TSOP-6 package, the electrical connections are
very simple.
Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together.
For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches
wide. Since
the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate.
The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance.
Also, heat
spreads in a circular fashion from the heat source.
In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Vishay Siliconix
surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAS
T
,
o
r pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package.
This pattern shows the starting point for
utilizing the board area available for the heat spreading copper.
T
o
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6.
The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air.
Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions.
This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
Ramp-Up Rate
+6
_
C/Second Maximum
120 Seconds Maximum
70
−
180 Seconds
240 +5/
−
0
_
C
0.074
1.875
T
e
mperature @ 155
”
15
_
C
T
e
mperature Above 180
_
C
Maximum
T
e
mperature
Time at Maximum
T
e
mperature
Ramp-Down Rate
0.014
0.35
0.122
3.1
0.026
0.65
20
−
40 Seconds
+6
_
C/Second Maximum
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 2.
Solder Reflow
T
e
mperature Profile
FIGURE 1.
Recommended Copper Spreading Footprint
Document Number:
71743
27-Feb-04
1
AN823
Vishay Siliconix
10 s (max)
255
−
260
_
C
1
X
4
_
C/s (max)
3-6
_
C/s (max)
217
_
C
140
−
170
_
C
60 s (max)
3
_
C/s (max)
60-120 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240
_
C is allowed.
FIGURE 3.
Solder Reflow
T
e
mperature and Time Durations
THERMAL PERFORMANCE
On-Resistance vs. Junction Temperature
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, R
q
jc
, or the
junction-to-foot thermal resistance, R
q
jf
. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted.
T
a
ble 1 shows the thermal performance
of the TSOP-6.
1.6
1.4
1.2
1.0
0.8
0.6
V
= 4.5 V
GS
I
D
= 6.1 A
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance R
q
30
_
C/W
jf
−
50
−
25
0
25
50
75
100 125 150
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
T
−
Junction
T
e
mperature (
_
C)
J
FIGURE 4.
Si3434DV
In any design, one must take into account the change in
MOSFET r
DS(on)
with temperature (Figure 4).
Document Number:
71743
27-Feb-04
2
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
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