Vishay-Intertech-SI3443CDV-T1-E3
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Si3443CDV
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
I
D
(A)
a
– 4.7
– 3.9
– 3.4
Definition
V
DS
(V)
R
DS(on)
(
)
Q
g
(Typ.)
•
•
•
•
TrenchFET
®
Power MOSFET
PWM Optimized
0.060 at V
GS
= – 4.5 V
0.084 at V
GS
= – 2.7 V
0.100 at V
GS
= – 2.5 V
100 % R
g
Tested
– 20
7.53 nC
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
•
HDD
Asynchronous Rectification
•
Load Switch for Portable Devices
TSOP-6
Top View
(4) S
1
2
3
6
3 mm
5
4
(3) G
Marking Code
AL XXX
Lot Tracea
b
ility
and Date Code
Part # Code
2.
8
5 mm
(1, 2, 5, 6) D
Orderin
g
Information:
Si3443CD
V
-T1-E3 (Lead (P
b
)-free)
Si3443CD
V
-T1-GE3 (Lead (P
b
)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Unit
Parameter
Symbol
Limit
– 20
12
Drain-Source Voltage
Gate-Source Voltage
V
DS
V
V
GS
T
T
T
C
= 25 °C
C
= 70 °C
A
= 25 °C
– 5.97
– 4.6
– 4.7
b, c
– 3.4
b, c
– 20
Continuous Drain Current (T
J
= 150 °C)
I
D
T
A
= 70 °C
A
I
DM
I
S
Pulsed Drain Current
T
C
= 25 °C
– 2.67
– 1.71
b, c
3.2
Continuous Source-Drain Diode Current
T
A
= 25 °C
T
C
= 25 °C
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
2.05
P
D
Maximum Power Dissipation
W
2
b, c
1.28
b, c
T
J
, T
stg
Operating Junction and Storage
T
e
mperature Range
– 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
b, d
Maximum Junction-to-Foot (Drain)
Symbol
R
thJA
Typical
51
Maximum
62.5
Unit
t
5 s
Steady State
°C/W
R
thJF
32
39
Notes:
a. Based
on T
C
= 25 °C.
b. Surface
mounted on 1″ x 1″ FR4 board.
c. t
= 5 s.
d. Maximum
under steady state conditions is 110 °C/W.
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
1
This document is subject to change without notice.
Si3443CDV
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
GS
= 0
V
,
I
D
= – 250 µA
I
D
= – 250 µA
Drain-Source Breakdown Voltage
– 20
V
V
DS
T
e
mperature Coefficient
– 18.8
3.25
mV/°C
V
GS(th)
T
e
mperature Coefficient
V
DS
= V
GS
, I
D
= – 250 µA
Gate-Source Threshold Voltage
Gate-Source Leakage
– 0.6
– 20
– 1.5
100
– 1
V
I
GSS
V
DS
= 0
V
,
V
GS
=
12 V
nA
V
DS
= – 20
V
,
V
GS
= 0 V
DS
= – 20
V
,
V
GS
= 0
V
,
T
J
= 55 °C
V
DS
– 5
V
,
V
GS
= – 4.5 V
V
GS
– 4.5
V
,
I
D
= – 4.7 A
V
GS
– 2.7
V
,
I
D
= – 3.9 A
V
GS
– 2.5
V
,
I
D
= – 3.4 A
V
DS
= – 10
V
,
I
D
= – 4.7 A
I
DSS
Zero Gate Voltage Drain Current
On-State Drain Current
a
µA
A
V
– 10
I
D(on)
0.0500 0.0600
0.0692 0.0840
0.0830 0.1000
15
Drain-Source On-State Resistance
a
R
DS(on)
Forward
T
r
ansconductance
a
g
fs
S
Dynamic
b
C
iss
C
oss
C
rss
Input Capacitance
610
132
105
V
DS
= – 10
V
,
V
GS
= 0
V
, f = 1
M
Hz
Output Capacitance
pF
Reverse
T
r
ansfer Capacitance
V
DS
= – 10
V
,
V
GS
= – 5
V
,
I
D
= – 4.7 A
8.26
7.53
1.53
2.37
8.5
27
12.4
11.3
Q
g
T
o
tal Gate Charge
nC
Q
gs
Q
gd
R
g
Gate-Source Charge
Gate-Drain Charge
V
DS
= – 10
V
,
V
GS
= – 4.5
V
,
I
D
= – 4.7 A
f = 1 MHz
Gate Resistance
1.7
12.75
41
t
d(on)
t
r
t
d(off)
t
f
T
u
rn-On Delay Time
Rise Time
59
88.5
45
V
DD
= – 10
V
,
R
L
= 2.12
ns
I
D
– 4.7 A, V
GEN
= – 4.5
V
,
R
g
= 1
T
u
rn-Off Delay Time
30
Fall Time
11
16.5
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
I
S
= – 1.7 A
– 2.67
– 20
– 1.2
30
A
Pulse Diode Forward Current
a
Body Diode Voltage
– 0.8
20
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Q
rr
t
a
9
13.5
I
F
= – 1.7 A, dI/dt = 100 A/µs, T
J
= 25 °C
15
ns
t
b
5.1
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
This document is subject to change without notice.
Si3443CDV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
20
16
12
8
4.0
3.2
2.4
1.6
0.
8
0.0
V
= 5
V
thr
u
3.5
V
GS
V
GS
= 3.0
V
V
= 2.5
V
GS
GS
T
C
= 125 °C
C
V
= 2.0
V
= 1.5
V
3
4
T
= – 55 °C
T
= 25 °C
C
V
GS
0
0
1
2
4
0.0
0.6
1.2
1.
8
2.4
3.0
V
GS
– Gate-to-So
u
rce
V
oltage (
V
)
V
DS
– Drain-to-So
u
rce
V
oltage (
V
)
Output Characteristics
Transfer Characteristics
0.20
0.15
0.10
0.05
0.00
1200
900
600
300
0
V
GS
= 2.5
V
C
iss
V
GS
= 4.5
V
C
oss
C
rss
0
4
8
12
16
20
0
4
8
12
16
20
I
D
– Drain C
u
rrent (A)
V
DS
– Drain-to-So
u
rce
V
oltage (
V
)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
5
1.4
1.2
1.0
0.
8
0.6
I
D
= 4.7 A
V
D
= 4.5
V
GS
= 4.7 A
I
4
3
2
1
0
V
D
= 2.5
V
GS
= 3.4 A
V
DS
= 10
V
V
DS
= 16
V
I
0
2
4
6
8
10
– 50
– 25
0
25
50
75
100 125 150
Q
–
T
o
tal Gate Charge (nC)
g
T
J
– J
u
nction
T
e
mperat
u
re (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
3
This document is subject to change without notice.
Si3443CDV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
0.15
0.12
0.09
0.06
0.03
0.00
I
D
= 4.7
A
1
T
A
= 125 °C
T
= 150 °C
J
T
= 25 °C
J
0.1
0.01
T
A
= 25 °C
0.001
0
1
2
3
4
5
0.0
0.2
0.4
0.6
0.
8
1.0
V
GS
– Gate-to-So
u
rce
V
oltage (
V
)
V
SD
– So
u
rce-to-Drain
V
oltage (
V
)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
50
40
1.5
1.3
1.1
0.9
0.7
0.5
30
20
10
I
D
= 250
µ
A
0
0.001
0.01
0.1
1
10
100
1000
– 50
– 25
0
25
50
75
100 125 150
Time (s)
T
–
T
e
mperat
u
re (°C)
J
Threshold Voltage
100
Single Pulse Power, Junction-to-Ambient
Limited
b
y R
DS(on)
*
10
10 ms
100 ms
1
1 s
10 s
DC
0.1
T
= 25 °C
A
0.01
Single P
u
lse
0.001
0.1
1
10
100
V
DS
– Drain-to-So
u
rce
V
oltage (
V
)
*
V
GS
minim
u
m
V
at
w
hich R
is specified
GS
DS(on)
Safe Operating Area
4
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
This document is subject to change without notice.
Si3443CDV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
8
6
4
2
0
4
3
2
1
0
0
25
50
75
100
125
150
0
25
50
T –
Case
T
e
mperat
u
re (°C)
C
75
100
125
150
T
– Case
T
e
mperat
u
re (°C)
C
Current Derating*
Power, Junction-to-Foot
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
5
This document is subject to change without notice.
Si3443CDV
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
D
u
ty Cycle = 0.5
0.2
N
otes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
0.02
1. D
u
ty Cycle, D =
2
2. Per Unit Base = R
= 110 °C/
W
thJA
(t)
3. T
– T
= P
JM
Z
A
DM thJA
Single P
u
lse
4. S
u
rface Mo
u
nted
0.01
-4
-3
-2
-1
10
10
10
10
1
10
100
1000
Sq
u
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
D
u
ty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single P
u
lse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Sq
u
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
Document Number: 74495
S12-0335-Rev. C, 13-Feb-12
This document is subject to change without notice.
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
5
4
3
6
1
4
E
1
E
E
1
E
1
2
2
3
-B-
-B-
e
e
b
b
M
M
C
0.15
C
B
A
0.15
B A
5-LEAD TSOP
6-LEAD TSOP
4x
1
-A-
D
0.17 Ref
c
R
R
A
2
A
L
2
G
au
ge Pl
a
ne
S
e
a
ting Pl
a
ne
S
e
a
ting Pl
a
ne
L
0.0
8
C
A
1
-C-
(L )
1
4x
1
MILLIMETERS
INCHES
Dim
A
A
1
A
2
b
c
D
E
E
1
e
Min
Nom
–
Max
Min
0.036
0.0004
0.035
0.012
0.004
0.116
0.106
0.061
Nom
–
Max
0.91
0.01
0.90
0.30
0.10
2.95
2.70
1.55
1.10
0.10
1.00
0.45
0.20
3.10
2.9
8
1.70
0.043
0.004
0.039
0.01
8
0.00
8
0.122
0.117
0.067
–
–
–
0.32
0.15
3.05
2.
8
5
1.65
0.95 B
S
C
1.90
–
0.03
8
0.013
0.006
0.120
0.112
0.065
0.0374 B
S
C
0.075
–
1.
8
0
2.00
0.50
0.071
0.012
0.079
0.020
e
1
L
0.32
0.60 Ref
0.25 B
S
C
–
0.024 Ref
0.010 B
S
C
–
L
1
L
2
R
0.10
0
–
0.004
0
–
4
8
4
8
7
Nom
7 Nom
1
ECN: C-06593-Rev.
I, 1
8
-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
1
AN823
Vishay Siliconix
Mounting LITTLE FOOT
R
TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages.
Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFE
T
s
.
Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What
has remained the same is the footprint of the
packages.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used.
Even if additional planar copper area is
used, there should be no problems in the soldering process.
The
actual solder connections are defined by the solder mask
openings. By
combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package.
For the TSOP-6 package
In converting the footprint to the pad set for a power MOSFE
T
, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
A final item to keep in mind is the width of the power traces.
The
absolute minimum power trace width must be determined by the
amount of current it has to carry.
For thermal reasons, this
minimum width should be at least 0.020 inches.
The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
In the case of the TSOP-6 package, the electrical connections are
very simple.
Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together.
For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches
wide. Since
the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate.
The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance.
Also, heat
spreads in a circular fashion from the heat source.
In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Vishay Siliconix
surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAS
T
,
o
r pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package.
This pattern shows the starting point for
utilizing the board area available for the heat spreading copper.
T
o
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6.
The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air.
Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions.
This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
Ramp-Up Rate
+6
_
C/Second Maximum
120 Seconds Maximum
70
−
180 Seconds
240 +5/
−
0
_
C
0.074
1.875
T
e
mperature @ 155
”
15
_
C
T
e
mperature Above 180
_
C
Maximum
T
e
mperature
Time at Maximum
T
e
mperature
Ramp-Down Rate
0.014
0.35
0.122
3.1
0.026
0.65
20
−
40 Seconds
+6
_
C/Second Maximum
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 2.
Solder Reflow
T
e
mperature Profile
FIGURE 1.
Recommended Copper Spreading Footprint
Document Number:
71743
27-Feb-04
1
AN823
Vishay Siliconix
10 s (max)
255
−
260
_
C
1
X
4
_
C/s (max)
3-6
_
C/s (max)
217
_
C
140
−
170
_
C
60 s (max)
3
_
C/s (max)
60-120 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240
_
C is allowed.
FIGURE 3.
Solder Reflow
T
e
mperature and Time Durations
THERMAL PERFORMANCE
On-Resistance vs. Junction Temperature
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, R
q
jc
, or the
junction-to-foot thermal resistance, R
q
jf
. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted.
T
a
ble 1 shows the thermal performance
of the TSOP-6.
1.6
1.4
1.2
1.0
0.8
0.6
V
= 4.5 V
GS
I
D
= 6.1 A
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance R
q
30
_
C/W
jf
−
50
−
25
0
25
50
75
100 125 150
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
T
−
Junction
T
e
mperature (
_
C)
J
FIGURE 4.
Si3434DV
In any design, one must take into account the change in
MOSFET r
DS(on)
with temperature (Figure 4).
Document Number:
71743
27-Feb-04
2
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
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typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2021
Document Number: 91000
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