Vishay-Intertech-SI5424DC-T1-GE3
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Si5424DC
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
FEATURES
•
TrenchFET
®
Power MOSFET
PRODUCT SUMMARY
I
D
(A)
a
•
Material categorization:
V
DS
(V)
R
DS(on)
(
)
Q
g
(Typ.)
0.024 at V
GS
= 10 V
0.030 at V
GS
= 4.5 V
6
For definitions of compliance please see
30
11 nC
6
APPLICATIONS
ChipFET 1206-8
•
Load Switch
1
– Notebook PC
D
D
D
D
D
D
Marking Code
D
G
AF
XXX
S
Lot Tracea
b
ility
G
and Date Code
Part # Code
Bottom
V
ie
w
Orderin
g
Information:
S
Si5424DC-T1-GE3 (Lead (P
b
)-free and Halogen-free)
N
-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Parameter
Symbol
V
DS
Limit
30
Unit
Drain-Source Voltage
Gate-Source Voltage
V
V
GS
25
6
a
6
a
6
a
6
a
40
5.2
a
2.1
b, c
16
T
C
= 25 °C
C
= 70 °C
T
I
D
Continuous Drain Current (T
J
= 150 °C)
T
A
= 25 °C
T
A
= 70 °C
A
I
DM
I
S
Pulsed Drain Current
T
C
= 25 °C
Continuous Source-Drain Diode Current
T
A
= 25 °C
L = 0.1 mH
T
C
= 25 °C
I
AS
Single Pulse Avalanche Current
Avalanche Energy
E
AS
12.8
6.25
4
2.5
b, c
1.6
b, c
mJ
W
T
C
= 70 °C
A
= 25 °C
Maximum Power Dissipation
a
P
D
T
T
A
= 70 °C
T
J
, T
stg
Operating Junction and Storage
T
e
mperature Range
Soldering Recommendations (Peak
T
e
mperature)
d, e
– 55 to 150
260
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
b, f
Maximum Junction-to-Foot (Drain)
Symbol
R
thJA
Typical
40
Maximum
Unit
t
5 s
Steady State
50
20
°C/W
R
thJF
15
Notes:
a. Package limited.
b. Surface mounted on 1” x 1” FR4 board.
c. t = 5 s.
d. See solder profile
(
www.vishay.com/doc?73257
)
. The ChipFET 1206-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum
under steady state conditions is 80 °C/W.
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
1
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5424DC
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
GS
= 0
V
,
I
D
= 250 µA
I
D
= 250 µA
Drain-Source Breakdown Voltage
30
V
V
DS
T
e
mperature Coefficient
19.4
– 4.6
mV/°C
V
GS(th)
T
e
mperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
V
DS
= V
GS
, I
D
= 250 µA
1.1
40
2.3
100
1
V
I
GSS
V
DS
= 0
V
,
V
GS
=
25 V
ns
V
DS
= 30
V
,
V
GS
= 0 V
DS
= 30
V
,
V
GS
= 0
V
,
T
J
= 55 °C
V
DS
5
V
,
V
GS
= 10 V
I
DSS
I
D(on)
R
DS(on)
g
fs
Zero Gate Voltage Drain Current
On-State Drain Current
a
µA
A
V
10
V
GS
10
V
,
I
D
= 4.8 A
0.020
0.024
17
0.024
0.030
Drain-Source On-State Resistance
a
S
V
GS
4.5
V
,
I
D
= 4.22 A
V
DS
= 15
V
,
I
D
= 4.8 A
Forward
T
r
ansconductance
a
Dynamic
b
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse
T
r
ansfer Capacitance
950
230
180
21
V
DS
= 15
V
,
V
GS
= 0
V
, f = 1
M
Hz
pF
V
DS
= 15
V
,
V
GS
= 10
V
,
I
D
= 4.8 A
32
17
Q
g
T
o
tal Gate Charge
11
nC
Q
gs
Q
gd
R
g
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
T
u
rn-On Delay Time
Rise Time
V
DS
= 15
V
,
V
GS
= 4.5
V
,
I
D
= 4.8 A
3.2
4.2
2.2
17
f = 1 MHz
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
26
113
33
18
15
57
40
14
75
V
DD
= 15
V
,
R
L
= 2.63
I
D
5.7 A, V
GEN
= 4.5
V
,
R
g
= 1
T
u
rn-Off Delay Time
Fall Time
22
12
ns
T
u
rn-On Delay Time
Rise Time
10
38
V
DD
= 15
V
,
R
L
= 2.5
I
D
6 A, V
GEN
= 10
V
,
R
g
= 1
T
u
rn-Off Delay Time
Fall Time
26
9
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
6
A
40
1.2
36
17
I
S
= 4.3 A, V
GS
= 0 V
Body Diode Voltage
0.8
24
11
9
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
ns
nC
Q
rr
t
a
I
F
= 4.3 A, dI/dt = 100 A/µs,
T
J
= 25 °C
ns
t
b
Reverse Recovery Rise Time
15
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
40
30
20
10
0
5
4
3
2
1
0
V
= 4
V
GS
V
GS
= 10 thr
u
5
V
V
= 3
V
GS
T
= 25
°C
J
T
J
= 125 °C
V
GS
= 2
V
T
J
= – 55 °C
0.0
0.6
1.2
1.
8
2.4
3.0
0.0
0.6
V
1.2
1.
8
2.4
3.0
– Drain-to-So
u
rce
V
oltage (
V
)
V
– Gate-to-So
u
rce
V
oltage (
V
)
DS
GS
Output Characteristics
Transfer Characteristics
1500
1200
900
600
300
0
0.04
0.03
0.02
0.01
C
iss
V
GS
= 4.5
V
V
GS
= 10
V
C
oss
C
rss
0
5
10
15
20
25
30
0
8
16
24
32
40
I
– Drain C
u
rrent (A)
D
V
– Drain-to-So
u
rce
V
oltage (
V
)
DS
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.
8
1.6
1.4
1.2
1.0
0.
8
0.6
10
I
D
= 6 A
8
6
4
2
0
V
GS
= 10
V
, I
= 4.
8
A
D
V
DS
= 15
V
V
DS
= 24
V
V
= 4.5
V
,
= 4.2 A
GS
I
D
– 50
– 25
0
25
50
75
100 125 150
0
6
12
1
8
24
Q
–
T
o
tal Gate Charge (nC)
T
J
– J
u
nction
T
e
mperat
u
re (°C)
g
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
3
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
20
10
0.06
0.05
0.04
0.03
0.02
0.01
0.00
I
D
= 4.
8
A
T
A
= 150 °C
1
T =
125 °C
A
T
A
= 25 °C
0.1
0.01
T
A
= 25 °C
0.001
0.0
0.2
0.4
0.6
0.
8
1.0
1.2
1.4
0
2
4
6
8
10
V
– So
u
rce-to-Drain
V
oltage (
V
)
SD
V
GS
– Gate-to-So
u
rce
V
oltage (
V
)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.0
1.
8
1.6
1.4
1.2
1.0
0.
8
0.6
0.4
50
40
30
20
10
0
I
D
= 250
µ
A
-3
-2
-1
– 50
– 25
0
25
50
75
100 125 150
10
10
10
1
10
100
600
T
J
–
T
e
mperat
u
re (°C)
Time (s)
Threshold Voltage
Single Pulse Power
100
Limited
b
y R
*
DS(on)
1 ms
10 ms
10
100 ms
1
0.1
1 s
10 s
DC
B
V
DSS Limited
0.01
T
A
= 25
C
Single P
u
lse
0.001
0.1
1
10
100
V
DS
– Drain-to-So
u
rce
V
oltage (
V
)
*
V
> minim
u
m
V
at
w
hich R
is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
4
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
8
6
4
2
0
16
12
8
Package Limited
4
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Case
T
e
mperat
u
re (°C)
T
C
– Case
T
e
mperat
u
re (°C)
Current Derating*
Power Derating
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
5
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5424DC
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
2
1
D
u
ty Cycle = 0.5
0.2
N
otes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
1. D
u
ty Cycle, D =
0.02
2
2. Per Unit Base = R
=
8
0 °C/
W
thJA
(t)
3. T
– T
= P
Z
JM DM
thJA
A
Single P
u
lse
4. S
u
rface Mo
u
nted
0.01
-4
-3
-2
-1
10
10
10
10
1
10
100
600
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
D
u
ty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single P
u
lse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
Document Number: 73776
S13-0297-Rev. C, 11-Feb-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Package Information
Vishay Siliconix
1206-8 ChipFET
R
4
L
D
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
4
E
1
E
x
S
e
b
c
Backside View
2X 0.10/0.13 R
A
DETAIL X
NOTES:
1. All
dimensions are in millimeaters.
2. Mold
gate burrs shall not exceed 0.13 mm per side.
3. Leadframe
to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4. Dimensions
exclusive of mold gate burrs.
5. No
mold flash allowed on the top and bottom lead surface.
MILLIMETERS
INCHES
Min Nom Max
Dim
A
b
c
c1
D
E
E
1
e
Min
1.00
0.25
0.1
Nom
−
Max
1.10
0.039
0.010
0.004
0
−
0.012
0.006
−
0.043
0.014
0.008
0.0015
0.122
0.078
0.067
0.30
0.35
0.15
0.20
0
−
0.038
3.10
2.95
1.825
1.55
3.05
0.116
0.072
0.061
0.120
0.075
0.065
0.0256 BSC
−
1.90
1.975
1.70
1.65
0.65 BSC
−
0.28
0.42
0.0
1
1
0.017
L
0.55 BSC
5
_
Nom
0.022 BSC
5
_
Nom
S
ECN: C-03528—Rev.
F
,
1
9-Jan-04
DWG: 5547
Document Number:
71151
15-Jan-04
1
AN811
Vishay Siliconix
Single-Channel 1206-8 ChipFET
r
Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFE
T
s
i
n the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOT
R
TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
80 mil
68 mil
This technical note discusses the single-channel ChipFET
1206-8 pin-out, package outline, pad patterns, evaluation
board layout, and thermal performance.
28 mil
26 mil
PIN-OUT
FIGURE 2.
Footprint With Copper Spreading
Figure 1
shows the pin-out description and Pin 1 identification
for the single-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thermal performance.
The legs of the device are very short, again helping to reduce
the thermal path to the external heatsink/pcb and allowing a
larger die to be fitted in the device if necessary.
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins
1,2,3,6.7,8) while remaining within the confines of the basic
footprint. The drain
copper area is 0.0054 sq. in. or
3.51 sq. mm). This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the single device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the
Vishay Siliconix
Evaluation Board described in the next
Single 1206-8 ChipFE
T
1
D
D
D
D
D
D
G
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE SINGLE 1206-8
S
Bottom View
The ChipFET 1206-08 evaluation board measures 0.6 in by
0.5 in. Its copper pad pattern consists of an increased pad area
around the six drain leads on the top-side—approximately
0.0482 sq. in. 31.1 sq. mm—and vias added through to the
underside of the board, again with a maximized copper pad
area of approximately the board-size dimensions. The outer
package outline is for the 8-pin DI
P
,
w
hich will allow test
sockets to be used to assist in testing.
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826,
Recommended Minimum Pad Patterns With Outline
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
Drawing
Access
for
Vishay Siliconix
MOSFE
T
s,
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number:
71126
12-Dec-03
1
AN811
Vishay Siliconix
Front of Board
Back of Board
ChipFET
r
vishay.com
FIGURE 3.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 45
_
C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 33
_
C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
pcb.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 15
_
C/W typical, 20
_
C/W
maximum for the single device. The “foot” is the drain lead of
the device as it connects with the body. This is identical to the
SO-8 package R
Q
jf
performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
160
120
Single EVB
Min. Footprint
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
80
40
The typical R
Q
ja
for the single-channel 1206-8 ChipFET is
80
_
C/W steady state, compared with 68
_
C/W for the SO-8.
Maximum ratings are 95
_
C/W for the 1206-8 versus 80
_
C/W
for the SO-8.
1” Square PCB
Testing
0
thermal performance on two different board sizes and three
different pad patterns. The results display the thermal
performance out to steady state and produce a graphic
account of how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of R
Q
ja
for the single 1206-8
ChipFET are :
-5
-4
-3
-2
-1
10
10
10
10
10
Time (Secs)
1
10
100
1000
FIGURE 4.
Single 1206
−
8 ChipFET
SUMMARY
The thermal results for the single-channel 1206-8 ChipFET
package display similar power dissipation performance to the
SO-8 with a footprint reduction of 80%. Careful design of the
package has allowed for this performance to be achieved. The
short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
1) Minimum recommended pad pattern (see
156
_
C/W
Figure 2
) on the evaluation board size of
0.5 in x 0.6 in.
2) The evaluation board with the pad pattern
111
_
C/W
ASSOCIATED DOCUMENT
3) Industry standard 1” square pcb with
maximum copper both sides.
78
_
C/W
1206-8 ChipFET Dual Thermal performance, AN812
Document Number:
71126
12-Dec-03
2
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2021
Document Number: 91000
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